Denon-AVR4520-avr-sm维修电路原理图.pdf

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1、D This is not a final specification. Some parametric limits are subject to change. 2 / 18 CONFIDENTIAL R2A15220FP-87D BLOCK DIAGRAM AND PIN CONFIGURATION (TOP VIEW) AGND SWC SLC INLB/RECL2 INRB/RECR2 INR11/RECR5 INL10/RECL4 RECR3 INL11/RECL5 FLIN1 RECL3 CIN1 FRIN1 SLIN1 SWIN1 AVEE MUTE FLIN2 FRIN2 S

2、LIN2 SRIN2 CIN2 SWIN2 SBLIN2 SBRIN2 AVCC TREL BASSL1 BASSL2 FLOUT FLC FROUT AGND FRC ADCR SBLIN1 SRIN1 SBRIN1 SBL OUT ADCL SBR OUT SLOUT SBRC SROUT SWOUT SRC COUTINL5 INL1 INR1 INL2 INR2 INL3 INR3 INL4 INR4 INR5 INL6 INR6 INL7 INR7 INL8 INR8 INLA/RECL1 INRA/RECR1 INL9 INR9 SUBR1 SUBL1 INR10/RECR4 DA

3、TA CLOCK BASSR1 BASSR2 AGND AGND SBRCIN SBLCIN AGND SBLC FR Pre-OUT FL Pre-OUT SBR Pre-OUT TRER SUBR2 SUBL2 SRCIN SLCIN SR Pre-OUT SL Pre-OUT SBL Pre-OUT INR12 INL12 INR13 INL13 INR14 INL14 CC AGND DGND REC ATT 0/-6/-12/-18dB Bass/ Treble -14+14dB (2dB step) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBs

4、tep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) Tone +420dB (0.5dBstep) Tone Bass/ Treble -14+14dB (2dB step) 0-95dB, - (0.5dBstep) +420dB (0.5dBstep) 0-95dB, - (0.5dBstep) MCU I/F AVEE AVCC Bypass Tone Tone+MIX Bypass Tone Tone+MIX MAIN SUB MAIN SUB

5、81828384858687888990919293949596979899100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 5049484746454443424140393837363534333231 MAIN SUB1 SUB2 200 R2A15220FP Pin Function 8-C

6、HANNEL ELECTRONIC VOLUME With 14-Input selector And Tone control R2A15220FPR2A15220FP PRELIMINARY Notice ; This is not a final specification. Some parametric limits are subject to change. 3 / 18 CONFIDENTIAL R2A15220FP-87D PIN DESCRIPTION PIN No. Name Function 49DATA Input pin of control data 50CLOC

7、KInput pin of control clock Output pin of FL/FR/C/SW/SL/SR/SBL/SBR channel FRIN2, FLIN2, SRN2,SLIN2, SWIN2,CIN2, SBRIN2,SBLIN2 43,42, 41,40, 39,38, 37,36 Multi Input pin of L/R/C/SW/SL/SR/SBL/SBR channel (Multi IN 1/2) Output pin for L/R channel REC Output Frequency characteristic setting pin of L/R

8、 channel tone control (Treble) 27,30 TREL, TRER 25,26, 28,29 22,20, 16,14, 10, 8, 2, 100 FROUT,FLOUT, COUT,SWOUT, SROUT, SLOUT, SBROUT,SBLOUT BASSL1,BASSL2 BASSR1,BASSR2 FLIN1, FRIN1, CIN1,SWIN1, SLIN1,SRIN1, SBLIN1,SBRIN1 90,91, 92,93, 94,95, 96,97 Frequency characteristic setting pin of L/R channe

9、l tone control (Bass) 24,18, 17,13, 12, 6, 4, 98 FRC,FLC, CC,SWC, SRC,SLC, SBRC,SBLC Connects capacitor for reducing click noise of L/R/C/SW/SL/SR/SBL/SBR channel volume INL1,INL2, INL3,INL4, INL5,INL6,INL7,INL8, INL9,INL12,INL13,INL14 Input pin of L/R channel (Input Selector) 57,59,61,63, 65,67,69,

10、71, 75,83,85,87 INR1,INR2, INR3,INR4, INR5,INR6,INR7,INR8, INR9,INR12,INR13,INR14 56,58,60,62, 64,6668,70, 74,82,84,86 53,54ADCL, ADCROutput pin for L/R channel ADC 88,89 1,5,9,15, 21,55,98 AGND Analog ground of internal circuit 31AVCCPositive power supply to internal circuit 48DGNDDigital ground of

11、 internal circuit 52AVEENegative power supply to internal circuit 46,47 33,32 SUBL1,SUBR1 SUBL2,SUBR2 Output pin for L/R channel SUB1/SUB2 Output RECR3,RECL3 51 MUTEOutside Mute Control PIN 72,73, 76,77, 78,79 80,81 INRA/RECR1,INLA/RECL1, INRB/RECR2,INLB/RECL2, INR10/RECR4,INL10/RECL4, INR11/RECR5,I

12、NL11/RECL5 Input pin of L/R channel (Input Selector)/ Output pin for L/R channel REC Output 44,45 34,35 SBRCIN,SBLCIN SRCIN,SLCIN 3rdMulti Input pin for SBL/SBR/SL/SR channel Volume that is able to swap SBR/SBL with SR/SL FR Pre-out,FL Pre-out, SR Pre-out, SL Pre-out, SBR Pre-out,SBL Pre-out Pre-out

13、put pin of FL/FR/SL/SR/SBL/SBR channel 23,19, 11, 7, 3, 99 201 NJW1194A (A.AUDIO/VIDEO : U3203, U3204) H27U1G8F2BTR-BC (NETWORK/DSP : U0504) NJW1194 2-CHANNEL ELECTRONIC VOLUME WITH INPUT SELECTOR AND TONE CONTROL I I I I GENERAL DESCRIPTION I I I IPACKAGE OUTLINE I I I I FEATURES G G G G G G G G G

14、G G I I I I BLOCK DIAGRAM NJW1194V Rev 1.1 / Sep. 20095 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash VCC VSS WP CLE ALE RE WE CEIO0IO7 R/B NC NC NC NCNC NCNC NC CLE ALEVss Vss Vss Vcc Vcc NC NC NC WP RE CE WERB NC NC NC NC NC NC NC NC NC NC NC NC NC I/O0 I/O1 I/O9 I/O2 I/O3 I/O10 I/O11I/O4

15、I/O15 I/O12I/O14 I/O13 I/O6 I/O7 I/O5 NC NCNCNC NC PRE I/O8 NC NCNC NCNC A B C D E F G H J K L M 1 2 3 4 5 6 7 8 9 10 ? ? ? Figure 2 : 48-TSOP1 / 63-FBGA Contact, x8 Device IO7 - IO0Data Input / Outputs CLECommand latch enable ALEAddress latch enable CEChip Enable RERead Enable WEWrite Enable WPWrit

16、e Protect R/BReady / Busy VccPower Supply VssGround NCNo Connection Figure 1 : Logic Diagram Table 1 : Signal Names ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 202 A3V56S30FTP-6G (NETWORK/DSP : U0505, U0506) A3V56S40FTP-6G (NETW

17、ORK/DSP : U0102, U0202, U0302) A3V56S30FTP A3V56S40FTP 256M Single Data Rate Synchronous DRAM Revision 1.1 Mar., 2010Page 2 / 39 CLK : Master Clock DQM : Output Disable / Write Mask (A3V56S30FTP) CKE : Clock Enable DQMU,L : Output Disable / Write Mask (A3V56S40FTP) /CS : Chip Select A0-12 : Address

18、Input /RAS : Row Address Strobe BA0,1 : Bank Address /CAS : Column Address Strobe Vdd : Power Supply /WE : Write Enable VddQ : Power Supply for Output DQ0-7 : Data I/O (A3V56S30FTP) Vss : Ground DQ0-15 : Data I/O (A3V56S40FTP) VssQ : Ground for Output BA0 BA1 Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ D

19、Q5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS A10(AP) A2 A3 Vdd A0 A1 Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0 BA1 A10(AP) A2 A3 Vdd A0 A1 DQM CKE Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE A12 A11 A8 A7 A6 A5 A4 Vss A9 Vss

20、DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC CLK A12 A11 A8 A7 A6 A5 A4 Vss A9 PIN CONFIGURATION (TOP VIEW) A3V56S30FTP-6G A3V56S40FTP-6G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2332 2431 2530 2629 2728 203

21、SAA7121 (NETWORK/DSP : U0607) SAA7121 Block Diagram SAA7120 SAA7121 MBH790 1res. SP AP LLC VDDD1 VSSD1 RCV1 RCV2 MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0 VDDD2 VSSD2 RTCI res. SA res. 2 3 4 5 6 7 8 9 10 11 33VSSA2 VSSA1 VDDA3 VDDA2 VDDA1 Y C CVBS res. res. res. 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17

22、 18 19 20 21 22 44 TTX TTXRQ SDA SCL XCLK XTALI XTALO VDDD3 VDDA4 VSSD3 RESET 43 42 41 40 39 38 37 36 35 34 handbook, full pagewidth I2C-BUS INTERFACE DATA MANAGER ENCODER SYNC CLOCK OUTPUT INTERFACE D A 40424121736843373435425, 28, 31 MP7 to MP0 TTX 5, 18, 386, 17, 39 1, 20, 22, 23, 26, 292193 30 2

23、7 24 32, 33 RESET SDA SCL RCV1 RCV2 TTXRQ XCLK XTALO XTALI LLC VDDA4 VSSA1 VSSA2 SA CVBS Y C I2C-bus control I2C-bus control I2C-bus control I2C-bus control I2C-bus control VSSD1, VSSD2, VSSD3 VDDD1, VDDD2, VDDD3 VDDA1, VDDA2, VDDA3 res. SPRTCIAP clock and timing YY C CbCr 44 9 to 16 MBH787 SAA7120

24、SAA7121 204 SAA7121 Pin Description 1997 Jan 064 Philips SemiconductorsPreliminary specification Digital Video Encoder (ConDENC)SAA7120; SAA7121 PINNING SYMBOLPINI/ODESCRIPTION res.1reserved SP2Itest pin; connected to digital ground for normal operation AP3Itest pin; connected to digital ground for

25、normal operation LLC4Iline-locked clock; this is the 27 MHz master clock for the encoder VSSD15Idigital ground 1 VDDD16Idigital supply voltage 1 RCV17I/Oraster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal RCV28I/Oraster control 2 for video port; this pin provides an HS pu

26、lse of programmable length or receives an HS pulse MP79I MPEG port; it is an input for“CCIR 656” style multiplexed Cb Y, Cr data MP610I MP511I MP412I MP313I MP214I MP115I MP016I VDDD217Idigital supply voltage 2 VSSD218Idigital ground 2 RTCI19IReal Time Control input; if the LLC clock is provided by

27、an SAA7111 or SAA7151B, RTCI should be connected to pin RTCO of the decoder to improve the signal quality res.20reserved SA21Ithe I2C-bus slave address select input pin; LOW: slave address = 88H, HIGH = 8CH res.22reserved res.23reserved C24Oanalog output of the chrominance signal VDDA125Ianalog supp

28、ly voltage 1 for the C DAC res.26reserved Y27Oanalog output of VBS signal VDDA228Ianalog supply voltage 2 for the Y DAC res.29reserved CVBS30Oanalog output of the CVBS signal VDDA331Ianalog supply voltage 3 for the CVBS DAC VSSA132Ianalog ground 1 for the DACs VSSA233Ianalog ground 2 for the oscilla

29、tor and reference voltage XTALO34Ocrystal oscillator output (to crystal) XTALI35Icrystal oscillator input (from crystal); if the oscillator is not used, this pin should be connected to ground VDDA436Ianalog supply voltage 4 for the oscillator and reference voltage XCLK37Oclock output of the crystal

30、oscillator 205 LAN8720A (NETWORK/DSP : U0706) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet SMSC LAN8720A/LAN8720Ai9Revision 1.3 (04-20-11) DATASHEET Chapter 2 Pin Description and Configuration Note:When a lower case “n” is used at the beginning of the signal n

31、ame, it indicates that the signal is active low. For example, nRST indicates that the reset signal is active low. Note:The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the buffer types is provided in Section 2.2. Figure 2.1 24-QFN Pin Assignments (TOP VIEW) VS

32、S SMSC LAN8720A/LAN8720Ai 24 PIN QFN (TOP VIEW) MDIO 1 2 3 4 5 6 7 8 9 10 11 12 18 17 16 15 14 13 24 23 22 21 20 19 VDDCR XTAL1/CLKIN XTAL2 LED1/REGOFF LED2/nINTSEL VDD2ATXD1 TXD0 TXEN nRST nINT/REFCLKO MDC VDD1A TXN TXP RXN RXP RBIAS CRS_DV/MODE2 RXER/PHYAD0 VDDIO RXD0/MODE0 RXD1/MODE1 206 LAN8720A

33、 Pin Function LAN8720A Block Diagram Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet SMSC LAN8720A/LAN8720Ai15Revision 1.3 (04-20-11) DATASHEET 2.1 Pin Assignments Table 2.8 24-QFN Package Pin Assignments PIN NUMPIN NAMEPIN NUMPIN NAME 1VDD2A13MDC 2LED2/nINTSEL14

34、nINT/REFCLKO 3LED1/REGOFF15nRST 4XTAL216TXEN 5XTAL1/CLKIN17TXD0 6VDDCR18TXD1 7RXD1/MODE119VDD1A 8RXD0/MODE020TXN 9VDDIO21TXP 10RXER/PHYAD022RXN 11CRS_DV/MODE223RXP 12MDIO24RBIAS Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Revision 1.3 (04-20-11)8SMSC LAN8720A

35、/LAN8720Ai DATASHEET Figure 1.1 System Block Diagram Figure 1.2 Architectural Overview RMII Logic Interrupt Generator LEDs PLL Receiver DSP System: Clock Data Recovery Equalizer Squeltch this pad must be robustly connected to GND. 209 MX29LV160DBTI-70G (NETWORK/DSP : U0103, U0203, U0303) MX29LV160DB

36、TI-70G Block Diagram 210 LC89057W-VF4A (DIGITAL : U0103, U0104) LC89057W-VF4A Terminl Function LC89057W-VF4A (DI: IC101) 9 Function Pin No. Pin Name 1RXOUTOInput bi-phase select data output terminal 2RX0ITTL compatible digital data input terminal 3RX1ICoaxial compatible amp built-in digital data inp

37、ut terminal 4RX2ITTL compatible digital data input terminal 5RX3ITTL compatible digital data input terminal 6DGND-Digital GND 7DVDD-Digital power 8RX4ITTL compatible digital data input terminal 9RX5/VII TTL compatible digital data/Validity fl ag input terminal for modulation 10RX6/UIITTL compatible

38、digital data/User data input terminal for modulation 11DVDD-Digital power for PLL 12DGND-Digital GND for PLL 13LPFO PLL loop fi lter connecting terminal 14AVDD-Analog power for PLL 15AGND-Analog GND for PLL 16RMCKORMCK clock output terminal (256fs, 512fs, XIN, VCO) 17RBCKO/IRBCK clock in/output term

39、inal (64fs) 18DGND-Digital GND 19DVDD-Digital power 20RLRCKO/IRLRCK clock in/output terminal (fs) 21RDATAOSerial audio data output terminal 22SBCKOSBCK clock output terminal (32fs, 64fs, 128fs) 23SLRCKOSLRCK clock output terminal (fs/2, fs, 2fs) 24SDINISerial audio data input terminal 25DGND-Digital

40、 GND 26DVDD-Digital power 27XMCKOOsc. amp output terminal I/O 36RERR1RXOUT 35INT2RX0 34CKST3RX1 33AUDIO/VO4RX2 32EMPHA/UO5RX3 31DGND6DGND 30DVDD7DVDD 29XIN8RX4 28XOUT9RX5/VI 27XMCK10RX6/UI 26DVDD11DVDD 25DGND12DGND 24SDIN37DO 23SLRCK38DI 22SBCK39CE 21RDATA40CL 20RLRCK41XMODE 19DVDD42DGND 18DGND43DVD

41、D 17RBCK44TMCK/PIO0 16RMCK45TBCK/PIO1 15AGND46TLRCK/PIO2 14AVDD47TDATA/PIO3 13LPF48TXO/PIOEN TOP VIEW 1RXOUT 32 EMPHA/UO 33 AUDIO/VO 35 INT 40 CL 39 CE 38 DI 28 XOUT 29 XIN 27 XMCK 34 CKST 41 XMODE Input Selector 2RX0 3RX1 4RX2 5RX3 8RX4 9RX5/VI 10RX6/UI 37DO 36RERR 21RDATA 24SDIN 16RMCK 17RBCK 20RL

42、RCK 22SBCK 23SLRCK 13LPF 44TMCK/PIO0 45TBCK/PIO1 46TLRCK/PIO2 47TDATA/PIO3 48TXO/PIOEN Clock Selector C bit, U bit PLL Demodulation active low MSEL3II2C/SPI select(2); active low SPI select RST14IReset(2); active low (1)Schmitt-trigger input, 5-V tolerant. (2)Schmitt-trigger input, 5-V tolerant. (3)

43、Schmitt-trigger input and output. 5-V tolerant input. In I2C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a CMOS output. (4)Schmitt-trigger input and output. 5-V tolerant input and CMOS output. 215 PCM1795 Block Diagram Table 1. TERMINAL FUNCTIONS (continued) TERMINAL

44、NAMENO.I/ODESCRIPTION SCK7ISystem clock input(2) VCC123Analog power supply, 5 V VCC2L28Analog power supply (left channel DACFF), 5 V VCC2R15Analog power supply (right channel DACFF), 5 V VCOML22Left channel internal bias decoupling pin VCOMR21Right channel internal bias decoupling pin VDD9Digital po

45、wer supply, 3.3 V ZEROL1I/OZero flag for left channel(4) ZEROR2I/OZero flag for right channel(4) Power?Supply RST SCK Advanced Segment DAC Modulator IOUTL+ IOUTL? IOUTR? IOUTR+ Bias and?VREF VCOML VCOMR AGND2 VDD VCC1 VCC2L VCC2R AGND1 I/V and?Filter x8 Oversampling Digital?Filter and Function?Contr

46、ol Audio Data?Input I/F LRCK BCK DATA MDO MDI MC MS AGND3L AGND3R DGND Current Segment DAC IREF VOUTL I/V?and?Filter VOUTR Function Control?I/F MSEL Zero Detect ZEROL ZEROR System Clock Manager Current Segment DAC PCM1795 SLES248MAY 6Submit Documentation FeedbackCopyright 2009, Texas Instruments Inc

47、orporated Product Folder Link(s): PCM1795 216 Sil9575CTUC (DIGITAL : U1001) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 120 119 1

48、18 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 99 98 97 96 95 94 93 92 91 90 89 4546474849505152535455565758596061626364656667686970717273747576 D15 D16 D17 D18 D19 DE VSYNC HSYNC IDCK R0XC- R0XC+ R0X0- R0X0+ R0X1- R0X1+ R0X2- R0X2+ R1XC- R1XC+ R1X0- R1X0+ R1X1- R1X1+ R1X2- R1X2+ R2XC- R2XC+ R2X0- R2X0+ R2X1- DSCL3 CBUS_HPD3 R3PWR5V DSCL4 DSCL5 SBVCC5 VCC3