Denon-AVRE300-avr-sm维修电路原理图.pdf

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1、START:|qzT7t3cIXfGvpSN6RPbAWw=|SEbVp1llkjf/ddOIdQCU/1/9XgnNoO2lk3dpwYeRCWI=|RtRIz5LbaS+BXuKmvA5tJg=|:END D supports TMDS logic level. 48 TXC+ HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 49 TXGND Ground TXAVDD Ground. 50 TX0 HDMI o

2、utput Diferential Output Channel 0 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 51 TX0+ HDMI output Diferential Output Channel 0 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGND Ground TX

3、AVDD Ground. 53 TX1 HDMI output Diferential Output Channel 1 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI output Diferential Output Channel 1 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic

4、 level. 55 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. 117 Pin No. Mnemonic Type Description 13 RXC_2 HDMI input Digital Input Channel 2 Complement of Port C in the HDMI Interface. 14 RXC_2+ HDMI input Digital Input Channel 2 True of Port C in the HDMI Interface. 15 HP_CTRLD Digital output Hot

5、 Plug Detect for Port D. 16 5V_DETD Digital input 5 V Detect Pin for Port D in the HDMI Interface. 17 DGND Ground DVDD Ground. 18 DVDD Power Digital Supply Voltage (1.8 V). 19 DDCD_SDA Digital I/O HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant. 20 DDCD_SCL Digit

6、al input HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant. 21 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 22 CGND Ground TVDD and CVDD Ground. 23 RXD_C HDMI input Digital Input Clock Complement of Port D in the HDMI Interface. 24 RXD_C+ HDMI input Digital Inp

7、ut Clock True of Port D in the HDMI Interface. 25 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 26 RXD_0 HDMI input Digital Input Channel 0 Complement of Port D in the HDMI Interface. 27 RXD_0+ HDMI input Digital Input Channel 0 True of Port D in the HDMI Interface. 28 CGND Ground TVDD and

8、CVDD Ground. 29 RXD_1 HDMI input Digital Input Channel 1 Complement of Port D in the HDMI Interface. 30 RXD_1+ HDMI input Digital Input Channel 1 True of Port D in the HDMI Interface. 31 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 32 RXD_2 HDMI input Digital Input Channel 2 Complement of

9、Port D in the HDMI Interface. 33 RXD_2+ HDMI input Digital Input Channel 2 True of Port D in the HDMI Interface. 34 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 35 CGND Ground TVDD and CVDD Ground. 36 TXPVDD Power 1.8 V Power Supply for Digital and I/O Power Supply. This pin supplies power

10、 to the digital logic and I/Os. It should be fltered and as quiet as possible. 37 TXPLVDD Power 1.8 V Power Supply. 38 TXGND Ground TXPVDD Ground. 39 TXPGND Ground TXPLVDD Ground. 40 EXT_SWING Analog input This pin sets the internal reference currents. Place an 887 resistor (1% tolerance) between th

11、is pin and ground. 41 HPD_ARC Analog input Hot Plug Detect Signal. This pin indicates to the interface whether the receiver is connected. It supports 1.8 V to 5 V CMOS logic levels. 42 ARC+ Analog input Audio Return Channel Input (5 V Tolerant). 43 TXDDC_SDA Digital I/O Serial Port Data I/O to Recei

12、ver. This pin serves as the master to the DDC bus. It supports a 5 V CMOS logic level. 44 TXDDC_SCL Digital output Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. It supports a 5 V CMOS logic level. 45 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. 46 TXGN

13、D Ground TXAVDD Ground. 47 TXC HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 48 TXC+ HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 49 TXGND Ground TXAVDD Ground. 50

14、 TX0 HDMI output Diferential Output Channel 0 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 51 TX0+ HDMI output Diferential Output Channel 0 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGN

15、D Ground TXAVDD Ground. 53 TX1 HDMI output Diferential Output Channel 1 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI output Diferential Output Channel 1 True. Diferential output of the red data at 10 the pixel clock rate; supports

16、 TMDS logic level. 55 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. 118 Pin No. Mnemonic Type Description 99 PGND Ground PVDD Ground. 100 PVDD Power PLL Supply Voltage (1.8 V). 101 XTAL Miscellaneous analog Input pin for 28.63636 MHz crystal or an external 1.8 V 28.63636 MHz clock oscillator sou

17、rce to clock the ADV7623. 102 XTAL1 Miscellaneous analog Crystal Output Pin. This pin should be left foating if a clock oscillator is used. 103 PVDD Power PLL Supply Voltage (1.8 V). 104 PGND Ground PVDD Ground. 105 HP_CTRLA Digital output Hot Plug Detect for Port A. 106 5V_DETA Digital input 5 V De

18、tect Pin for Port A in the HDMI Interface. 107 RTERM Miscellaneous analog This pin sets the internal termination resistance. A 500 resistor between this pin and ground should be used. 108 DDCA_SDA Digital I/O HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant. 109 D

19、DCA_SCL Digital input HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. 110 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 111 CGND Ground TVDD and CVDD Ground. 112 RXA_C HDMI input Digital Input Clock Complement of Port A in the HDMI Interface. 113 RXA_C+ HDMI

20、input Digital Input Clock True of Port A in the HDMI Interface. 114 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 115 RXA_0 HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface. 116 RXA_0+ HDMI input Digital Input Channel 0 True of Port A in the HDMI Interface. 117

21、CGND Ground TVDD and CVDD Ground. 118 RXA_1 HDMI input Digital Input Channel 1 Complement of Port A in the HDMI Interface. 119 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface. 120 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 121 RXA_2 HDMI input Digital Input

22、 Channel 2 Complement of Port A in the HDMI Interface. 122 RXA_2+ HDMI input Digital Input Channel 2 True of Port A in the HDMI Interface. 123 HP_CTRLB Digital output Hot Plug Detect for Port B. 124 5V_DETB Digital input 5 V Detect Pin for Port B in the HDMI Interface. 125 DGND Ground DVDD Ground. 1

23、26 DVDD Power Digital Supply Voltage (1.8 V). 127 DDCB_SDA Digital I/O HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant. 128 DDCB_SCL Digital input HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. 129 CVDD Power Receiver Comparator S

24、upply Voltage (1.8 V). 130 CGND Ground TVDD and CVDD Ground. 131 RXB_C HDMI input Digital Input Clock Complement of Port B in the HDMI Interface. 132 RXB_C+ HDMI input Digital Input Clock True of Port B in the HDMI Interface. 133 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 134 RXB_0 HDMI

25、input Digital Input Channel 0 Complement of Port B in the HDMI Interface. 135 RXB_0+ HDMI input Digital Input Channel 0 True of Port B in the HDMI Interface. 136 CGND Ground TVDD and CVDD Ground. 137 RXB_1 HDMI input Digital Input Channel 1 Complement of Port B in the HDMI Interface. 138 RXB_1+ HDMI

26、 input Digital Input Channel 1 True of Port B in the HDMI Interface. 139 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 140 RXB_2 HDMI input Digital Input Channel 2 Complement of Port B in the HDMI Interface. 141 RXB_2+ HDMI input Digital Input Channel 2 True of Port B in the HDMI Interface.

27、 142 HP_CTRLC Digital output Hot Plug Detect for Port C. 143 5V_DETC Digital input 5 V Detect Pin for Port C in the HDMI Interface. 144 DDCC_SDA Digital I/O HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input/output that is 5 V tolerant. 119 ADV7623Blockdiagram CH0 CH1 CH2 VIDEO DATA DE VS HS A

28、UDIO DATA VIDEO DATA DE VS HS AUDIO DATA VIDEO DATA DE VS HS AUDIO DATA VIDEO DATA DE VS HS AUDIO DATA XTAL XTAL1 RXA_C RXB_C RXC_C RXD_C RXA_0 RXA_1 RXA_2 VIDEO/AUDIO CLOCK GENERATION RX PLL CEC TXC TX0 TX1 TX2 5V DETECT COMPONENT PROCESSOR SCL SDATA ALSB CS I2C CONTROLLER PWRDN RESET GLOBAL CONTRO

29、LS DDCA_SDA DDCA_SCL DDCB_SDA DDCB_SCL DDCC_SDA DDCC_SCL DDCD_SDA DDCD_SCL AP0_IN AP1_IN AP2_IN AP3_IN AP4_IN AP5_IN SCLK_IN MCLK_IN AP0_OUT AP1_OUT AP2_OUT AP3_OUT AP4_OUT AP5_OUT SCLK_OUT MCLK_OUT ARC+ RX EDID/ REPEATER CONTROLLER RX HPD CONTROLLER EP_MISO EP_MOSI EP_CS EP_SCK SPI MASTER/ SLAVE EQ

30、UALIZER RXB_0 RXB_1 RXB_2 EQUALIZER SAMPLER SAMPLER RXC_0 RXC_1 RXC_2 EQUALIZERSAMPLER RXD_0 RXD_1 RXD_2 EQUALIZER CEC CONTROLLER EDID RAM SAMPLER HDMI RECEIVER PROCESSOR TRANSMITTER PACKET BUILDER HDCP ENCRYPTION ENGINE HDMI ENCODER SERIALIZER TMDS DRIVERS INT1 INT2 INT_TX INTERRUPT CONTROLLER TXDD

31、C_SDA TXDDC_SCL TX EDID/HDCP CONTROLLER EDID/HDCP BUFFER HPD_ARC TX HPD CONTROLLER HDCP DECRYPTION ENGINE SYNC MEASUREMENT PACKET PROCESSOR INFOFRAME PACKET MEMORY AUDIO PROCESSOR ARC RECEIVER AUDIO CAPTURE HDCP KEYS TX PLL ADV7623 5V_DETA 5V_DETB 5V_DETC 5V_DETD HP_CTRLA HP_CTRLB HP_CTRLC HP_CTRLD

32、OSD 120 PCM9211(DIGITAL:IC782) PIN Functions PIN DESCRIPTION NO.NAMEI/O 5-V TOLERANT 1ERROR/INT0ONoDIR Error detection output / Interrupt0 output 2NPCM/INT1ONoDIR Non-PCM detection output / Interrupt1 output 3MPIO_A0I/OYesMultipurpose I/O, Group A(1) 4MPIO_A1I/OYesMultipurpose I/O, Group A(1) 5MPIO_

33、A2I/OYesMultipurpose I/O, Group A(1) 6MPIO_A3I/OYesMultipurpose I/O, Group A(1) 7MPIO_C0I/OYesMultipurpose I/O, Group C(1) 8MPIO_C1I/OYesMultipurpose I/O, Group C(1) 9MPIO_C2I/OYesMultipurpose I/O, Group C(1) 10MPIO_C3I/OYesMultipurpose I/O, Group C(1) 11MPIO_B0I/OYesMultipurpose I/O, Group B(1) 12M

34、PIO_B1I/OYesMultipurpose I/O, Group B(1) 13MPIO_B2I/OYesMultipurpose I/O, Group B(1) 14MPIO_B3I/OYesMultipurpose I/O, Group B(1) 15MPO0ONoMultipurpose output 0 16MPO1ONoMultipurpose output 1 17DOUTONoMain output port, serial digital audio data output 18LRCKONoMain output port, LR clock output 19BCKO

35、NoMain output port, Bit clock output 20SCKOONoMain output port, System clock output 21DGNDGround, for digital 22DVDDPower supply, 3.3 V (typ.), for digital 23MDO/ADR0I/OYesSoftware control I/F, SPI data output / I2C slave address setting0(2) 24MDI/SDAI/OYesSoftware control I/F, SPI data input / I2C

36、data input/output(2) (3) 25MC/SCLIYesSoftware control I/F, SPI clock input / I2C clock input(2) 26MS/ADR1IYesSoftware control I/F, SPI chip select / I2C slave address setting1(2) 27MODEINoControl mode setting, (see the Serial Control Mode section, Control Mode Pin Setting) 28RXIN7/ADIN0IYesBiphase s

37、ignal, input 7 / AUXIN0, serial audio data input(2) 29RXIN6/ALRCKI0IYesBiphase signal, input 6 / AUXIN0, LR clock input(2) 30RXIN5/ABCKI0IYesBiphase signal, input 5 / AUXIN0, bit clock input(2) 31RXIN4/ASCKI0IYesBiphase signal, input 4 / AUXIN0, system clock input(2) 32RXIN3IYesBiphase signal, input

38、 3(2) 33RXIN2IYesBiphase signal, input 2(2) 34RSTIYesReset Input, active low(2) (4) 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 ERROR/INT0 NPCM/INT1 MPIO_A0 MPIO_A1 MPIO_A2 MPIO_A3 MPIO_C0 MPIO_C1 MPIO_C2 MPIO_C3 MPIO_B0 MPIO_B1 VDDRX RXIN1 RST RXIN2 RXIN3 RXIN4/ASCKIO RXIN5/ABCKI

39、O RXIN6/ALRCKIO RXIN7/ADIN0 MODE MS/ADR1 MC/SCL 4847464544434241403938 1314151617181920212223 37 24 PCM9211 VINR VINL VCCAD AGNDAD VCOM FILT VCC AGND XTO XTI GNDRX RXIN0 MPIO_B2 MPIO_B3 MPO0 MPO1 DOUT LRCK BCK SCKO DGND DVDD MDO/ADR0 MDI/SDA PCM9211 SBAS495 JUNE 2010 PIN CONFIGURATIONS PT PACKAGE LQ

40、FP-48 (TOP VIEW) PIN FUNCTIONS PIN 5-V NO.NAMEI/OTOLERANTDESCRIPTION 1ERROR/INT0ONoDIR Error detection output / Interrupt0 output 2NPCM/INT1ONoDIR Non-PCM detection output / Interrupt1 output 3MPIO_A0I/OYesMultipurpose I/O, Group A(1) 4MPIO_A1I/OYesMultipurpose I/O, Group A(1) 5MPIO_A2I/OYesMultipur

41、pose I/O, Group A(1) 6MPIO_A3I/OYesMultipurpose I/O, Group A(1) 7MPIO_C0I/OYesMultipurpose I/O, Group C(1) 8MPIO_C1I/OYesMultipurpose I/O, Group C(1) 9MPIO_C2I/OYesMultipurpose I/O, Group C(1) 10MPIO_C3I/OYesMultipurpose I/O, Group C(1) 11MPIO_B0I/OYesMultipurpose I/O, Group B(1) 12MPIO_B1I/OYesMult

42、ipurpose I/O, Group B(1) 13MPIO_B2I/OYesMultipurpose I/O, Group B(1) 14MPIO_B3I/OYesMultipurpose I/O, Group B(1) 15MPO0ONoMultipurpose output 0 (1)Schmitt trigger input Copyright 2010, Texas Instruments IncorporatedSubmit Documentation Feedback7 Product Folder Link(s): PCM9211 121 PIN DESCRIPTION NO

43、.NAMEI/O 5-V TOLERANT 35RXIN1IYesBiphase signal, input 1, built-in coaxial amplifier 36VDDRXPower supply, 3.3 V (typ.), for RXIN0 and RXIN1. 37RXIN0IYesBiphase signal, input 0, built-in coaxial amplifier 38GNDRX-Ground, for RXIN 39XTIINoOscillation circuit input for crystal resonator or external XTI

44、 clock source input(5) 40XTOONoOscillation circuit output for crystal resonator 41AGNDGround, for PLL analog 42VCCPower supply, 3.3 V (typ.), for PLL analog 43FILTONoExternal PLL loop filter connection terminal; must connect recommended filter 44VCOMONoADC common voltage output; must connect externa

45、l decoupling capacitor 45AGNDADGround, for ADC analog 46VCCADPower supply, 5.0 V (typ.), for ADC analog 47VINLINoADC analog voltage input, left channel 48VINRINoADC analog voltage input, right channel (1) Schmitt trigger input (2) Schmitt trigger input (3) Open-drain configuration in I2C mode (4) On

46、board pull-down resistor (50 k, typical) (5) CMOS Schmitt trigger input PCM9211 BLOCK DIAGRAM Clock/Data Recovery MPIO_A SELECTOR MPIO_C SELECTOR MPIO _B SELECTOR ADC Com. Supply MPO0/1 SELECTOR MPO0 MPO1 MAIN OUTPUT SCKO BCK LRCK DOUT PORT RXIN8 RXIN9 RXIN10 RXIN11 DITOUT AUTO DIR ADC AUXIN0 AUXIN1

47、 AUXIN2 AUTO DIR ADC AUXIN0 AUXIN1 AUXIN2 AUTO DIR ADC AUXIN0 AUXIN1 DIT Lock:DIR Unlock:ADC AUXIN2 AUXOUT OSC Divider XMCKO Divider XMCKO DITOUT RECOUT0 RECOUT1 AUXIN0 AUXIN1 ADC Standalone ADC Mode Control Function Control REGISTER POWER SUPPLY MC /SCL MDI/SDA MDO /ADR0 MS/ADR1 FILT PLL DIR Lock D

48、etection ERROR/INT0 NPCM/INT1 ADC Clock (SCK/BCK/LRCK) (To MPIO _A & MPO0/1) ADC MODE DIR CS (48-bit) DIT CS (48-bit) DIR Interrupt GPIO/GPO Data MPIO_A MPIO_B MPIO_C MPO0 MPO1 Divider (to MPIO_A) Secondary BCK/LRCK Selector RECOUT0 RECOUT1 SBCK/SLRCK DOUT RXIN7 SCKO/BCK/LRCK RXIN0 RXIN1 RXIN2 RXIN4

49、/ASCKI0 RXIN3 RXIN5/ABCKI0 RXIN6/ALRCKI0 RXIN7/ADIN0RXIN7 RXIN6 RXIN5 RXIN4 RXIN3 RXIN2 RXIN1 RXIN0 MPIO_A0 MPIO_A1 MPIO_A2 MPIO_A3 VINL VINR VCOM MPIO _C0 MPIO _C1 MPIO _C2 MPIO _C3 XTI XTO AGNDVDDRXGNDRXDVDDVCCADAGNDADDGNDVCC ADC ANALOG DIR ANALOG ALL DIR ANALOG SPI/I C INTERFACE 2 Reset and Mode Set All Port f Calculator S DIR f Calculator S DIR P and P CD EXTRA DIR FUNCTIONS f Calculator S ERROR DETECTION Non-PCM DETECTION Flags DTS-CD/LD Detection Validity Flag User Data Channel Status Data BFRAME Detection Interrupt System MPIO_B3 MPIO_B2 MPIO_B1