Denon-AVR2112CI-avr-sm维修电路原理图.pdf

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1、D supports TMDS logic level. 48 TXC+ HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 49 TXGND Ground TXAVDD Ground. 50 TX0 HDMI output Diferential Output Channel 0 Complement. Diferential output of the red data at 10 the pixel clock r

2、ate; supports TMDS logic level. 51 TX0+ HDMI output Diferential Output Channel 0 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGND Ground TXAVDD Ground. 53 TX1 HDMI output Diferential Output Channel 1 Complement. Diferential output of the red da

3、ta at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI output Diferential Output Channel 1 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 55 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. 144 Pin No. Mnemonic Type Description 13 RXC

4、_2 HDMI input Digital Input Channel 2 Complement of Port C in the HDMI Interface. 14 RXC_2+ HDMI input Digital Input Channel 2 True of Port C in the HDMI Interface. 15 HP_CTRLD Digital output Hot Plug Detect for Port D. 16 5V_DETD Digital input 5 V Detect Pin for Port D in the HDMI Interface. 17 DGN

5、D Ground DVDD Ground. 18 DVDD Power Digital Supply Voltage (1.8 V). 19 DDCD_SDA Digital I/O HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant. 20 DDCD_SCL Digital input HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant. 21 CVDD Power Re

6、ceiver Comparator Supply Voltage (1.8 V). 22 CGND Ground TVDD and CVDD Ground. 23 RXD_C HDMI input Digital Input Clock Complement of Port D in the HDMI Interface. 24 RXD_C+ HDMI input Digital Input Clock True of Port D in the HDMI Interface. 25 TVDD Power Receiver Terminator Supply Voltage (3.3 V).

7、26 RXD_0 HDMI input Digital Input Channel 0 Complement of Port D in the HDMI Interface. 27 RXD_0+ HDMI input Digital Input Channel 0 True of Port D in the HDMI Interface. 28 CGND Ground TVDD and CVDD Ground. 29 RXD_1 HDMI input Digital Input Channel 1 Complement of Port D in the HDMI Interface. 30 R

8、XD_1+ HDMI input Digital Input Channel 1 True of Port D in the HDMI Interface. 31 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 32 RXD_2 HDMI input Digital Input Channel 2 Complement of Port D in the HDMI Interface. 33 RXD_2+ HDMI input Digital Input Channel 2 True of Port D in the HDMI Int

9、erface. 34 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 35 CGND Ground TVDD and CVDD Ground. 36 TXPVDD Power 1.8 V Power Supply for Digital and I/O Power Supply. This pin supplies power to the digital logic and I/Os. It should be fltered and as quiet as possible. 37 TXPLVDD Power 1.8 V Pow

10、er Supply. 38 TXGND Ground TXPVDD Ground. 39 TXPGND Ground TXPLVDD Ground. 40 EXT_SWING Analog input This pin sets the internal reference currents. Place an 887 resistor (1% tolerance) between this pin and ground. 41 HPD_ARC Analog input Hot Plug Detect Signal. This pin indicates to the interface wh

11、ether the receiver is connected. It supports 1.8 V to 5 V CMOS logic levels. 42 ARC+ Analog input Audio Return Channel Input (5 V Tolerant). 43 TXDDC_SDA Digital I/O Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. It supports a 5 V CMOS logic level. 44 TXDDC_SCL Digit

12、al output Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. It supports a 5 V CMOS logic level. 45 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. 46 TXGND Ground TXAVDD Ground. 47 TXC HDMI output Diferential Clock Output. Diferential clock output at the TMDS

13、 clock rate; supports TMDS logic level. 48 TXC+ HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 49 TXGND Ground TXAVDD Ground. 50 TX0 HDMI output Diferential Output Channel 0 Complement. Diferential output of the red data at 10 the pi

14、xel clock rate; supports TMDS logic level. 51 TX0+ HDMI output Diferential Output Channel 0 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGND Ground TXAVDD Ground. 53 TX1 HDMI output Diferential Output Channel 1 Complement. Diferential output of

15、 the red data at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI output Diferential Output Channel 1 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 55 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. 145 Pin No. Mnemonic Type Descrip

16、tion 99 PGND Ground PVDD Ground. 100 PVDD Power PLL Supply Voltage (1.8 V). 101 XTAL Miscellaneous analog Input pin for 28.63636 MHz crystal or an external 1.8 V 28.63636 MHz clock oscillator source to clock the ADV7623. 102 XTAL1 Miscellaneous analog Crystal Output Pin. This pin should be left foat

17、ing if a clock oscillator is used. 103 PVDD Power PLL Supply Voltage (1.8 V). 104 PGND Ground PVDD Ground. 105 HP_CTRLA Digital output Hot Plug Detect for Port A. 106 5V_DETA Digital input 5 V Detect Pin for Port A in the HDMI Interface. 107 RTERM Miscellaneous analog This pin sets the internal term

18、ination resistance. A 500 resistor between this pin and ground should be used. 108 DDCA_SDA Digital I/O HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant. 109 DDCA_SCL Digital input HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. 110

19、 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 111 CGND Ground TVDD and CVDD Ground. 112 RXA_C HDMI input Digital Input Clock Complement of Port A in the HDMI Interface. 113 RXA_C+ HDMI input Digital Input Clock True of Port A in the HDMI Interface. 114 TVDD Power Receiver Terminator Supply

20、 Voltage (3.3 V). 115 RXA_0 HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface. 116 RXA_0+ HDMI input Digital Input Channel 0 True of Port A in the HDMI Interface. 117 CGND Ground TVDD and CVDD Ground. 118 RXA_1 HDMI input Digital Input Channel 1 Complement of Port A in th

21、e HDMI Interface. 119 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface. 120 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 121 RXA_2 HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface. 122 RXA_2+ HDMI input Digital Input Channel 2 True

22、 of Port A in the HDMI Interface. 123 HP_CTRLB Digital output Hot Plug Detect for Port B. 124 5V_DETB Digital input 5 V Detect Pin for Port B in the HDMI Interface. 125 DGND Ground DVDD Ground. 126 DVDD Power Digital Supply Voltage (1.8 V). 127 DDCB_SDA Digital I/O HDCP Slave Serial Data Port B. DDC

23、B_SDA is a 3.3 V input/output that is 5 V tolerant. 128 DDCB_SCL Digital input HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. 129 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 130 CGND Ground TVDD and CVDD Ground. 131 RXB_C HDMI input Digital Input Clock Com

24、plement of Port B in the HDMI Interface. 132 RXB_C+ HDMI input Digital Input Clock True of Port B in the HDMI Interface. 133 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 134 RXB_0 HDMI input Digital Input Channel 0 Complement of Port B in the HDMI Interface. 135 RXB_0+ HDMI input Digital I

25、nput Channel 0 True of Port B in the HDMI Interface. 136 CGND Ground TVDD and CVDD Ground. 137 RXB_1 HDMI input Digital Input Channel 1 Complement of Port B in the HDMI Interface. 138 RXB_1+ HDMI input Digital Input Channel 1 True of Port B in the HDMI Interface. 139 TVDD Power Receiver Terminator S

26、upply Voltage (3.3 V). 140 RXB_2 HDMI input Digital Input Channel 2 Complement of Port B in the HDMI Interface. 141 RXB_2+ HDMI input Digital Input Channel 2 True of Port B in the HDMI Interface. 142 HP_CTRLC Digital output Hot Plug Detect for Port C. 143 5V_DETC Digital input 5 V Detect Pin for Por

27、t C in the HDMI Interface. 144 DDCC_SDA Digital I/O HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input/output that is 5 V tolerant. 146 ADV7623 Block diagram ADV7844 (HDMI : U4) CH0 CH1 CH2 VIDEO DATA DE VS HS AUDIO DATA VIDEO DATA DE VS HS AUDIO DATA VIDEO DATA DE VS HS AUDIO DATA VIDEO DATA

28、DE VS HS AUDIO DATA XTAL XTAL1 RXA_C RXB_C RXC_C RXD_C RXA_0 RXA_1 RXA_2 VIDEO/AUDIO CLOCK GENERATION RX PLL CEC TXC TX0 TX1 TX2 5V DETECT COMPONENT PROCESSOR SCL SDATA ALSB CS I2C CONTROLLER PWRDN RESET GLOBAL CONTROLS DDCA_SDA DDCA_SCL DDCB_SDA DDCB_SCL DDCC_SDA DDCC_SCL DDCD_SDA DDCD_SCL AP0_IN A

29、P1_IN AP2_IN AP3_IN AP4_IN AP5_IN SCLK_IN MCLK_IN AP0_OUT AP1_OUT AP2_OUT AP3_OUT AP4_OUT AP5_OUT SCLK_OUT MCLK_OUT ARC+ RX EDID/ REPEATER CONTROLLER RX HPD CONTROLLER EP_MISO EP_MOSI EP_CS EP_SCK SPI MASTER/ SLAVE EQUALIZER RXB_0 RXB_1 RXB_2 EQUALIZER SAMPLER SAMPLER RXC_0 RXC_1 RXC_2 EQUALIZERSAMP

30、LER RXD_0 RXD_1 RXD_2 EQUALIZER CEC CONTROLLER EDID RAM SAMPLER HDMI RECEIVER PROCESSOR TRANSMITTER PACKET BUILDER HDCP ENCRYPTION ENGINE HDMI ENCODER SERIALIZER TMDS DRIVERS INT1 INT2 INT_TX INTERRUPT CONTROLLER TXDDC_SDA TXDDC_SCL TX EDID/HDCP CONTROLLER EDID/HDCP BUFFER HPD_ARC TX HPD CONTROLLER

31、HDCP DECRYPTION ENGINE SYNC MEASUREMENT PACKET PROCESSOR INFOFRAME PACKET MEMORY AUDIO PROCESSOR ARC RECEIVER AUDIO CAPTURE HDCP KEYS TX PLL ADV7623 5V_DETA 5V_DETB 5V_DETC 5V_DETD HP_CTRLA HP_CTRLB HP_CTRLC HP_CTRLD OSD Quad HDMI 1.4 Fast Switching Receiver with 12-Bit, 170 MHz Video and Graphics D

32、igitizer and 3D Comb Filter Decoder ADV7844 FEATURES Quad HDMI 1.4 fast switching receiver 170 MHz video and graphics digitizer 3D comb filter video decoder SCART fast blank support Adaptive HDMI equalizer Integrated CEC controller HDMI repeater support Advanced VBI data slicer 4:1 HDMI 1.4 225 MHz

33、receiver Xpressview fast switching of HDMI ports 2 ARC interfaces for ARC support SPDIF interface for ARC support 3D video format support, including frame packing 1080p 24 Hz, 720p 50 Hz, 720p 60 Hz Full colorimetry support including sYCC601, Adobe RGB, Adobe YCC 601 36-/30-bit Deep Color and 24-bit

34、 color support HDCP 1.4 support with internal HDCP keys 5 V detect and hot plug assert for each HDMI port HDMI audio support including HBR and DSD Advanced audio mute feature Flexible digital audio output interfaces Supports up to 5 S/PDIF outputs Supports up to 4 I2S outputs Video and graphics digi

35、tizer Four 170 MHz, 12-bit ADCs 12-channel analog input mux 525i-/625i-component analog input 525p-/625p-component progressive scan support 720p-/1080i-/1080p-component HDTV support Low refresh rates (24/25/30 Hz) support for 720p/1080p Digitizes RGB graphics up to 1600 1200 at 60 Hz (UXGA) 3D video

36、 decoder NTSC/PAL/SECAM color standards support NTSC/PAL 2D/3D motion detecting comb filter Advanced time-base correction (TBC) with frame synchronization Interlaced-to-progressive conversion for 525i and 625i IF compensation filters Vertical peaking and horizontal peaking filters Robust synchroniza

37、tion extraction for poor video source General Highly flexible 36-bit pixel output interface Internal EDID RAM for HDMI and graphics Dual STDI (standard identification) function support Any-to-any, 3 3 color space conversion (CSC) matrix 2 programmable interrupt request output pins Simultaneous analo

38、g processing and HDMI monitoring APPLICATIONS Advanced TVs PDP HDTVs LCD TVs (HDTV ready) LCD/DLP rear projection HDTVs CRT HDTVs LCoS HDTVs AVR video receivers LCD/DLP front projectors HDTV STBs with PVR Projectors FUNCTIONAL BLOCK DIAGRAM ADC ADC ADC ADC INPUT MUX OUTPUT MUXOUTPUT MUX CVBS SCART G

39、 SCART CVBS SCART RGB + CVBS GRAPHICS RGB CVBS YC HDMI 1 HDMI 2 HD YpbPr SD/PS YPbPr SCART B SCART R Y/G Pb/B Pb/R I2S S/PDIF DSD HBR MCLK SCLK CVBS HS/VS FIELD/DE CLKHS/VS FIELD/DE CLK 36-BIT YCbCr/RGB AUDIO OUTPUT MCLK SCLK TO AUDIO PROCESSOR DATA SDP CVBS 3D YC S-VIDEO SCART HS/VS FIELD/DE CLK DA

40、TA CP YPbPr 525p/625p 720p/1080i 1080p/ UXGA RGB 48 36 4 5 SDRAM TMDS DDC TMDS DDC HDMI 3 TMDS DDC HDMI 4 TMDS DDC S/PDIF ARC_1 ARC_2 ARC DEEP COLOR HDMI Rx FAST SWITCH HDCP KEYS ADV7844 08850-001 Figure 1. For more information on the ADV7844, email Analog Devices, Inc., at ATV_VIDEORX_A. Rev. Sp0 I

41、nformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No

42、 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 2010 Analog Dev

43、ices, Inc. All rights reserved. 147 ADV7511BSTZ (HDMI : IC12) ADV7511BSTZ Block diagram ADV7511 ADI Confidential HARDWARE USERS GUIDE Rev. PrB Rev. PrB | Page 17 of 55 SECTION 5: PIN AND PACKAGE INFORMATION This section shows the pinout of the ADV7511 100-lead LQFP package. This section also contain

44、s a brief description of the different pins as well as the mechanical drawings Figure 6100-lead LQFP configuration (top view - not to scale) PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 41 42 40 43 44 45 68 67 66 65 64 63

45、 62 61 60 59 58 57 56 55 54 53 52 51 69 70 71 72 73 74 75 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 94 95 96 97 98 99 100 ADV7511 TOP VIEW (Not to Scale) 46 47 48 49 50 GND DDCSDA DDCSCL HEAC- GND GND GND GND PVDD PVDD PVDD DVDD DVDD D18 D22 D21 D20 D19 D35 D29 D28 D27 D26 D25 D24 D23 D3

46、4 D33 D32 D31 D30 SCL SDA HEAC+ VSYNC DSD0 DSD1 DSD_CLK SPDIF MCLK I2S0 I2S3 I2S2 I2S1 SCLK LRCLK GND GND HSYNC DE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 CLK D17 DVDD DVDD DSD2 DSD5 DSD4 DSD3 CEC_CLK DVDD CEC_IN DVDD_3V SPDIF_OUT INT GND TX2+ TX2 AVDD TX1+ TX1 PD GND TX0+ TX0 AVDD

47、 TXC+ TXC GND HPD AVDD R_EXT GND BGVDD ADV7511 ADI Confidential HARDWARE USERS GUIDE Rev. PrB Rev. PrB | Page 10 of 55 SECTION 3: BLOCK DIAGRAM Figure 1ADV7511 Functional Block Diagram I2C SLAVE I2C MASTER SDA SCL INT HPD TX0+/TX0 TX1+/TX1 TX2+/TX2 TXC+/TXC DDCSDA DDCSCL ADV7511 TMDS OUTPUTS CEC_IO

48、CEC CONTROLLER/ BUFFER SPDIF DSD_CLK DSD5:0 I2S3:0 MCLK LRCLK SCLK AUDIO DATA CAPTURE D35:0 VSYNC HSYNC DE CLK VIDEO DATA CAPTURE REGISTERS AND CONFIG. LOGIC 4:2:2 4:4:4 AND COLOR SPACE CONVERTER HDCP AND EDID MICROCONTROLLER HDCP KEYS HDCP ENCRYPTION HEAC+ ARC HEAC- CEC_CLK SPDIF_OUT 148 LAN8700-AE

49、ZG-TR (HDMI : IC14) LAN8700-AEZG-TR Block Diagram nINT/TX_ER/TXD4 MDC CRS/PHYAD4 MDIO nRST TX_EN VDD_CORE VDD33 LINK/PHYAD1 ACTIVITY/PHYAD2 FDUPLEX/PHYAD3 XTAL2 CLKIN/XTAL1 RXD3/nINTSEL RXD1/MODE1 RXD2/MODE2 TXD3 RX_CLK/REGOFF TX_CLK RX_ER/RXD4 VDDIO TXD1 TXD0 TXD2 COL/RMII/CRS_DV TXP RXN VDDA3.3 EXRES1 VDDA3.3 RXP VDDA3.3 USB3300 Hi-Speed USB2 ULPI PHY 32 Pin QFN 1 2 3 4 5 6 7 8 LAN8700/LAN8700I MII/RMII Ethernet PHY 36 Pin QFN GND FLAG 10 11 12 13 14 15 16 24 23 22 21 20 19 32 31 30 29 28 SPEED100/PHYAD0