Denon-AVRS910W-avr-sm4维修电路原理图.pdf

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1、MODELJPE3E2EKEAE1E1CE1K AVR-X2200WPPPP AVR-S910WP INTEGRATED NETWORK AV RECEIVER Ver. 4 Please use this service manual with referring to the operating instructions without fail. Some illustrations using in this service manual are slightly different from the actual set. For purposes of improvement, s

2、pecifications and design are subject to change without notice. Please refer to the MODIFICATION NOTICE.e SERVICE MANUAL e D must connect recommended filter 44VCOMONoADC common voltage output; must connect external decoupling capacitor 45AGNDADGround, for ADC analog 46VCCADPower supply, 5.0 V (typ.),

3、 for ADC analog 47VINLINoADC analog voltage input, left channel 48VINRINoADC analog voltage input, right channel (1) Schmitt trigger input (2) Schmitt trigger input (3) Open-drain configuration in I2C mode (4) Onboard pull-down resistor (50 k, typical) (5) CMOS Schmitt trigger input PCM9211 BLOCK DI

4、AGRAM Clock/Data Recovery MPIO_A SELECTOR MPIO_C SELECTOR MPIO _B SELECTOR ADC Com. Supply MPO0/1 SELECTOR MPO0 MPO1 MAIN OUTPUT SCKO BCK LRCK DOUT PORT RXIN8 RXIN9 RXIN10 RXIN11 DITOUT AUTO DIR ADC AUXIN0 AUXIN1 AUXIN2 AUTO DIR ADC AUXIN0 AUXIN1 AUXIN2 AUTO DIR ADC AUXIN0 AUXIN1 DIT Lock:DIR Unlock

5、:ADC AUXIN2 AUXOUT OSC Divider XMCKO Divider XMCKO DITOUT RECOUT0 RECOUT1 AUXIN0 AUXIN1 ADC Standalone ADC Mode Control Function Control REGISTER POWER SUPPLY MC /SCL MDI/SDA MDO /ADR0 MS/ADR1 FILT PLL DIR Lock Detection ERROR/INT0 NPCM/INT1 ADC Clock (SCK/BCK/LRCK) (To MPIO _A & MPO0/1) ADC MODE DI

6、R CS (48-bit) DIT CS (48-bit) DIR Interrupt GPIO/GPO Data MPIO_A MPIO_B MPIO_C MPO0 MPO1 Divider (to MPIO_A) Secondary BCK/LRCK Selector RECOUT0 RECOUT1 SBCK/SLRCK DOUT RXIN7 SCKO/BCK/LRCK RXIN0 RXIN1 RXIN2 RXIN4/ASCKI0 RXIN3 RXIN5/ABCKI0 RXIN6/ALRCKI0 RXIN7/ADIN0RXIN7 RXIN6 RXIN5 RXIN4 RXIN3 RXIN2

7、RXIN1 RXIN0 MPIO_A0 MPIO_A1 MPIO_A2 MPIO_A3 VINL VINR VCOM MPIO _C0 MPIO _C1 MPIO _C2 MPIO _C3 XTI XTO AGNDVDDRXGNDRXDVDDVCCADAGNDADDGNDVCC ADC ANALOG DIR ANALOG ALL DIR ANALOG SPI/I C INTERFACE 2 Reset and Mode Set All Port f Calculator S DIR f Calculator S DIR P and P CD EXTRA DIR FUNCTIONS f Calc

8、ulator S ERROR DETECTION Non-PCM DETECTION Flags DTS-CD/LD Detection Validity Flag User Data Channel Status Data BFRAME Detection Interrupt System MPIO_B3 MPIO_B2 MPIO_B1 MPIO_B0 RST PCM9211 SBAS495 JUNE 2010 BLOCK DIAGRAM Copyright 2010, Texas Instruments IncorporatedSubmit Documentation Feedback9

9、Product Folder Link(s): PCM9211 150 CS49844A (HDMI : U1073) VDD3 BDI*, DAI1_SCLK1, GPIO71 BDI*, DAI1_D0, GPIO64 GNDIO4 VDDIO4 SD_D2, EXT_D10 SD_D11, EXT_D3 SD_D15, EXT_D7 SD_D12, EXT_D4 DAO3_D3, XMTA, GPIO113 SD_D14, EXT_D6 SD_D7, EXT_D15 SD_D13, EXT_D5 GND10 SD_D0, EXT_D8 SD_D3, EXT_D11 SD_D5, EXT_

10、D13 SD_D1, EXT_D9 VDD9 DAO3_D7, XMTB, GPIO115 DAO3_D2, GPIO33 SCP_MOSI, GPIO147 SCP1_MISO_SDA, GPIO146 SCP1_CLK, GPIO148 SCP2_CS SCP1_IRQ, GPIO144_OD DAI1_SCLK2, GPIO73 VDDIO1 GNDIO1 DAI1_LRCK2, GPIO72 RESET DBDA1 DBCK0 EE_CS0, GPIO1 DAI1_D4, GPIO68 BDI*, DAI1_D2, GPIO66 BDI*, DAI1_D1, GPIO65 SD_CS,

11、 EXT_OE SD_BA0, EXT_A13 SD_CAS, EXT_CS2 GND1 VDD2 DAI1_D5, GPIO69 EE_CS1. GPIO0 VDD10 BDI* DAI1_D3, GPIO67 VDD1 GND2 TEST_EN SD_BA1, EXT_A14 GND3 BDI*, DAI1_LRCK1, GPIO70 SD_A10, EXT_A12 DBDA0 DBCK1 GND8 VDD8 SCP1_CS, GPIO145 SD_D4, EXT_D12 GND9 SCP_BSY, GPIO143_OD DA03_D1, GPIO32 DA03_D5, GPIO34 DA

12、O3_D6, GPIO35 SD_DQM0, EXT_A15 SD_WE, EXT_WE SD_A3, EXT_A3, SD_A2, EXT_A2 SD_D6, EXT_D14 SD_RAS, EXT_CS1 SD_A1, EXT_A1 SD_A0, EXT_A0 1 5 9 10 13 18 21 24 27 33 36 15 25 30 35 101 98 94 91 86 83 76 73 75 80 85 90 95 100 105 108 CS49844A 144-Pin LQFP Package (with Thermal Pad) 151 W9864G6KH-5 (HDMI :

13、U1023) W9864G6KH-5 Pin description W9864G6KH Publication Release Date: Nov. 12, 2013 - 4 - Revision A02 4. PIN CONFIGURATION 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 DQ0 DQ1 DQ2 DQ3 DQ4 DQ

14、5 DQ6 DQ7 LDQM CAS RAS CS BS0 BS1 A10/AP A0 A1 A2 A3 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VDDQ VDDQ VSSQ VSSQ VDD VDD VSS VSSQ VSSQ VDDQ VSS VSS WE VDD VDDQ W9864G6KH Publication Release Date: Nov. 12, 2013 - 5 - Revision A02 5. PIN DESCRIPTION PIN NUMBERPIN

15、 NAME FUNCTION DESCRIPTION 23 26, 22, 29 35 A0 A11 Address Multiplexed pins for row and column address. Row address: A0 A11. Column address: A0 A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. 20, 21BS0, BS1 Bank Select Select

16、 bank to activate during row address latch time, or bank to read/write during address latch time. 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 DQ0 DQ15 Data Input/ Output Multiplexed pins for data output and input. 19 CS Chip Select Disable or enable the command decoder. When command de

17、coder is disabled, new command is ignored and previous operation continues. 18 Row Address Strobe Command input. When sampled at the rising edge of the clock , CAS and WE define the operation to be executed. 17 CAS Column Address Strobe Referred to 16 WE Write Enable Referred to 39, 15 UDQM LDQM Inp

18、ut/output mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. 38 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. 37 CKE Clock Enable C

19、KE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. 1, 14, 27 VDD Power Power for input buffers and logic circuit inside DRAM. 28, 41, 54 VSS Ground Ground for input buffers and logic circuit inside DRAM. 3, 9, 43, 49 VD

20、DQ Power for I/O buffer Separated power from VDD, to improve DQ noise immunity. 6, 12, 46, 52VSSQ Ground for I/O buffer Separated ground from VSS, to improve DQ noise immunity. 36, 40 NC No ConnectionNo connection. 152 W9864G6KH-5 Block diagram W9864G6KH Publication Release Date: Nov. 12, 2013 - 6 -

21、 Revision A02 6. BLOCK DIAGRAM CLK CKE A10 CLOCK BUFFER COMMAND DECODER ADDRESS BUFFER REFRESH COUNTER COLUMN COUNTER CONTROL SIGNAL GENERATOR MODE REGISTER COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #2 COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #0 COLUMN DECODER SENSE AMPLIFIER CELL ARRAY B

22、ANK #3 DATA CONTROL CIRCUIT DQ BUFFER COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #1 NOTE: The cell array configuration is 4096 * 256 * 16 A0 A9 BS0 BS1 CS RAS CAS WE A11 153 PCM1690 (HDMI : U1048) PCM1690 Pin Function TERMINAL I/O PULL- DOWN 5-V TOLERANT DESCRIPTION NAMEPIN RSV21Reserved, tied t

23、o analog ground RSV12Reserved, left open RSV23Reserved, tied to analog ground RSV14Reserved, left open RSV25Reserved, tied to analog ground LRCK6IYesNoAudio data word clock input BCK7IYesNoAudio data bit clock input DIN18INoNoAudio data input for DAC1 and DAC2 DIN29INoNoAudio data input for DAC3 and

24、 DAC4 DIN310INoNoAudio data input for DAC5 and DAC6 DIN411INoNoAudio data input for DAC7 and DAC8 VDD12Digital power supply, +3.3 V DGND13Digital ground SCKI14INoYesSystem clock input RST15IYesYesReset and power-down control input with active low ZERO116ONoNoZero detect flag output 1 ZERO217ONoNoZer

25、o detect flag output 2 AMUTEI18INoYesAnalog mute control input with active low AMUTEO19ONoYesAnalog mute status output(1) with active low MD/SDA/DEMP20I/ONoYesInput data for SPI, data for I2C(1), de-emphasis control for hardware control mode MC/SCL/FMT21INoYesClock for SPI, clock for I2C, format sel

26、ect for hardware control mode MS/ADR0/RSV22IYesYes Chip Select for SPI, address select 0 for I2C, reserve (set low) for hardware control mode TEST/ADR1/RSV23I/ONoYes Test (factory use, left open) for SPI, address select 1 for I2C, reserve (set low) for hardware control mode MODE24INoNoControl port m

27、ode selection. Tied to VDD: SPI, left open: H/W mode, tied to DGND: I2C VCC125Analog power supply 1, +5 V VCOM26Voltage common decoupling AGND127Analog ground 1 RSV228Reserved, tied to analog ground VOUT8+29ONoNoPositive analog output from DAC8 VOUT8-30ONoNoNegative analog output from DAC8 VOUT7+31O

28、NoNoPositive analog output from DAC7 VOUT7-32ONoNoNegative analog output from DAC7 VOUT6+33ONoNoPositive analog output from DAC6 VOUT6-34ONoNoNegative analog output from DAC6 VOUT5+35ONoNoPositive analog output from DAC5 VOUT5-36ONoNoNegative analog output from DAC5 VOUT4+37ONoNoPositive analog outp

29、ut from DAC4 VOUT4-38ONoNoNegative analog output from DAC4 VOUT3+39ONoNoPositive analog output from DAC3 VOUT3-40ONoNoNegative analog output from DAC3 VOUT2+41ONoNoPositive analog output from DAC2 VOUT2-42ONoNoNegative analog output from DAC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

30、23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 RSV2 VCC2 AGND2 RSV2 VOUT1? VOUT1+ VOUT2? VOUT2+ VOUT3? VOUT3+ VOUT4? VOUT4+ VOUT5? VOUT5+ VOUT6? VOUT6+ VOUT7? VOUT7+ VOUT8? VOUT8+ RSV2 AGND1 VCOM VCC1 RSV2 RSV1 RSV2 RSV1 RSV2 LRCK BCK DIN1 DIN2 DIN3 DIN4 VDD DGND SCKI

31、RST ZERO1 ZERO2 AMUTEI AMUTEO MD/SDA/DEMP MC/SCL/FMT MS/ADR0/RSV TEST/ADR1/RSV MODE PCM1690 Thermal?Pad PCM1690 SBAS448AOCTOBER 2008REVISED JANUARY DCA PACKAGE HTSSOP-48 (12 mm x 8 mm) (TOP VIEW) TERMINAL FUNCTIONS TERMINAL PULL-5-V NAMEPINI/ODOWNTOLERANTDESCRIPTION RSV21Reserved, tied to analog gro

32、und RSV12Reserved, left open RSV23Reserved, tied to analog ground RSV14Reserved, left open RSV25Reserved, tied to analog ground LRCK6IYesNoAudio data word clock input BCK7IYesNoAudio data bit clock input DIN18INoNoAudio data input for DAC1 and DAC2 DIN29INoNoAudio data input for DAC3 and DAC4 DIN310

33、INoNoAudio data input for DAC5 and DAC6 DIN411INoNoAudio data input for DAC7 and DAC8 6Submit Documentation FeedbackCopyright 20082009, Texas Instruments Incorporated Product Folder Link(s): PCM1690 154 TERMINAL I/O PULL- DOWN 5-V TOLERANT DESCRIPTION NAMEPIN VOUT1+43ONoNoPositive analog output from

34、 DAC1 VOUT1-44ONoNoNegative analog output from DAC1 RSV245Reserved, tied to analog ground AGND246Analog ground 2 VCC247Analog power supply 2, +5 V RSV248Reserved, tied to analog ground (1) Open-drain configuration in out mode. PCM1690 FUNCTIONAL BLOCK DIAGRAM DAC VOUT1+ VOUT1? DAC VOUT2+ VOUT2? DAC

35、VOUT3+ VOUT3? DAC VOUT4+ VOUT4? DAC VOUT5+ VOUT5? DAC VOUT6+ VOUT6? AGND2 VDD DGND VCOM VCC1 AGND1 VCC2 DAC VOUT7+ VOUT7? DAC VOUT8+ VOUT8? Digital?Filter and Volume Power?Supply?and Common?Voltage SCKI SCK?Manager RST AMUTEO AMUTEI ZERO2 ZERO1 MODE MD/SDA/DEMP MC/SCL/FMT MS/ADR0/RSV TEST/ADR1/RSV C

36、ontrol?Interface (SPI/I C/HW) 2 LRCK BCK DIN4 DIN3 DIN2 DIN1 Audio?Interface PCM1690 SBAS448AOCTOBER 2008REVISED JANUARY 8Submit Documentation FeedbackCopyright 20082009, Texas Instruments Incorporated Product Folder Link(s): PCM1690 155 PCM5100 (HDMI:U1052) PCM5100 Block Diagram PCM5100, PCM5101, P

37、CM5102 SLAS764 MAY DEVICE INFORMATION TERMINAL FUNCTIONS, PCM510 x PCM510X (top view) Table 2. TERMINAL FUNCTIONS, PCM510 x TERMINAL I/ODESCRIPTION NAMENO. CPVDD1-Charge pump power supply, 3.3V CAPP2OCharge pump flying capacitor terminal for positive rail CPGND3-Charge pump ground CAPM4OCharge pump

38、flying capacitor terminal for negative rail VNEG5ONegative charge pump rail terminal for decoupling, -3.3V OUTL6OAnalog output from DAC left channel OUTR7OAnalog output from DAC right channel AVDD8-Analog power supply, 3.3V AGND9-Analog ground DEMP10IDe-emphasis control for 44.1kHz sampling rate(1):

39、 Off (Low) / On (High) FLT11IFilter select : Normal latency (Low) / Low latency (High) SCK12ISystem clock input BCK13IAudio data bit clock input DIN14IAudio data input LRCK15IAudio data word clock input FMT16IAudio format selection : I2S (Low) / Left justified (High) XSMT17ISoft mute control : Soft

40、mute (Low) / soft un-mute (High) LDOO18-Internal logic supply rail terminal for decoupling DGND19-Digital ground DVDD20-Digital power supply, 3.3V (1)Failsafe LVCMOS Schmitt trigger input Audio Interface 8x Interpolation Filter 32bit Modulator Current Segment DAC Current Segment DAC I/VI/V Analog Mu

41、te Analog Mute Zero Data Detector UVP/Reset PLL Clock Power Supply Ch. PumpPOR Clock Halt Detection Advanced Mute Control MCK BCK LRCK CAPP CAPM VNEG LINE OUT DIN (i2s) PCM510 x CPVDD (3.3V) AVDD (3.3V) DVDD (3.3V) GND Figure 1. PCM510 x Functional Block Diagram 156 BD34704KS2 (INPUT : IC4200) PIN N

42、o.SYMBOLPIN No.SYMBOLPIN No.SYMBOLPIN No.SYMBOL 1DA21GND61SBLIN41INR9(SBRIN2) 2CL22GND62SRIN42INL9(SBLIN2) 3VCC23GND63SLIN43INR8 4DGND24GND64CIN44INL8 5VEE125GND65SWIN45INR7 6N.C.26GND66FRIN46INL7 7VEE227GND67FLIN47INR6 8OUTFL28SUBR68FRIN348INL6 9N.C.29SUBL69FLIN349INR5 10OUTFR30RECR70GND50INL5 11N.

43、C.31RECL71ADCR51INR4 12OUTSW32GND72ADCL52INL4 13N.C.33INR12(FRIN2)73GND53INR3 14OUTC34INL12(FLIN2)74GND54INL3 15OUTSL35INR11(CIN2)75GND55INR2 16OUTSR36INL11(SWIN2)76GND56INL2 17OUTSBL37INR10(SRIN2)77GND57INR1 18OUTSBR38INL10(SLIN2)78GND58INL1 19OUTPL39GND79GND59GND 20OUTPR40N.C.80CHIP60SBRIN Datashe

44、et 製品構造：集積回路 耐放射線設計。 1/32 Target Specification 2015 ROHM Co., Ltd. All rights reserved. 2015.2.25 Rev.002 www.rohm.co.jp TSZ2211114001 用 搭載 7.1ch 高音質 BD34704KS2 概要 音質向上、使用特性 素子配置配線見直、入出力間 音質劣化 8ch 独立実現。 独自技術搭載 、音楽再生中切替場合 極力抑制、高品位 最適。最大 3 対応可能 12 入力、2 系統入力内蔵 、多数信号源接続。 特長 12 入力内蔵 (入力、REC 出力、SUB 出力使用場合

45、 最大 18 入力拡張可能) 、 不快切替軽減 3 対応 用 2ch 搭載 2 線、3.3/5V 対応 用途 AV 、最適。 重要特性 全高調波歪率: 0.0004%(Typ) 最大出力電圧: 4.2Vrms(Typ) 出力雑音電圧: 1.2Vrms(Typ) 残留雑音電圧: 1.0Vrms(Typ) 間: -105dB(Typ) 間: -105dB(Typ) W(Typ) x D(Typ) x H(Max) SQFP-T80C 16.00mm x 16.00mm x 1.60mm SQFP-T80C 基本回路 Figure 1. 応用回路例 TARGET SPECIFICATION 157

46、NJM2595MTE1 (VIDEO:IC5001) NJM2586AVC3(VIDEO:IC5002) NJM2595 - 1 - 5-INPUT 3-OUTPUT VIDEO SWITCH I GENERAL DESCRIPTION I PACKAGE OUTLINE I FEATURES G 5-input 3-output G Operating Voltage 4.0 to 6.5V G Operating current 15mAtyp. at Vcc=5V G Crosstalk -65dBtyp. G Internal 6dB Amplifier G Internal 75 D

47、river G Bipolar Technology G Package Outline DIP16,DMP16 I PIN CONFIGURATION and BLOCK DIAGRAM 13 9 7 5 3 20k 20k 20k 20k 1610 14 2 1 15 11 81264 6dB Amp 75 Driver S3 S2 S4 S1 20k 20k 20k S5 S6 S7 Vin1 Vin2 Vin3 Vin4 Vin5 SW3SW4 SW5SW1SW2V+ GND V- Vout3 Vout2 Vout1 6dB Amp 6dB Amp 75 Driver 75 Drive

48、r Ver.4 NJM2586A - 1 - WIDE BAND 3-INPUT 1-OUTPUT 3-CIRCUIT VIDEO AMPLIFIER ?GENERAL DESCRIPTION ?PACKAGE OUTLINE The NJM2586A is a wide band 3-input 1-output 3-circuit video amplifier. It is suitable for Y, Pb, and Pr signal because frequency range is 50MHz.The NJM2586A is suitable for AV receiver,

49、 STB, and other high quality AV systems. ? FEATURES ? Operating Voltage 4.5 to 5.5V ? Wide frequency range 0dB at 50MHz typ. ? Internal 3 input-1output 3-circuit video switch ? Internal 6dB Amplifier ? Internal 75 Driver Circuit (2-system drive) ? Power Save Circuit ? Bipolar Technology ? Package Outline SDIP22, SSOP20-C3 (under development) ?BLOCK DIA