Denon-AVRX1200W-avr-sm维修电路原理图.pdf

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1、MODELJPE3E2EKEAE1E1CE1K AVR-X1200WPPPP AVR-S710WP INTEGRATED NETWORK AV RECEIVER Ver. 1 Please use this service manual with referring to the operating instructions without fail. Some illustrations using in this service manual are slightly different from the actual set. For purposes of improvement, s

2、pecifications and design are subject to change without notice. e SERVICE MANUAL e D supports TMDS logic level. 48 TXC+ HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 49 TXGND Ground TXAVDD Ground. 50 TX0 HDMI output Diferential Outpu

3、t Channel 0 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 51 TX0+ HDMI output Diferential Output Channel 0 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGND Ground TXAVDD Ground. 53 TX1 HDM

4、I output Diferential Output Channel 1 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI output Diferential Output Channel 1 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 55 TXAVDD Power

5、 1.8 V Power Supply for TMDS Outputs. 123 Pin No. Mnemonic Type Description 13 RXC_2 HDMI input Digital Input Channel 2 Complement of Port C in the HDMI Interface. 14 RXC_2+ HDMI input Digital Input Channel 2 True of Port C in the HDMI Interface. 15 HP_CTRLD Digital output Hot Plug Detect for Port D

6、. 16 5V_DETD Digital input 5 V Detect Pin for Port D in the HDMI Interface. 17 DGND Ground DVDD Ground. 18 DVDD Power Digital Supply Voltage (1.8 V). 19 DDCD_SDA Digital I/O HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant. 20 DDCD_SCL Digital input HDCP Slave Ser

7、ial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant. 21 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 22 CGND Ground TVDD and CVDD Ground. 23 RXD_C HDMI input Digital Input Clock Complement of Port D in the HDMI Interface. 24 RXD_C+ HDMI input Digital Input Clock True of Port D

8、 in the HDMI Interface. 25 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 26 RXD_0 HDMI input Digital Input Channel 0 Complement of Port D in the HDMI Interface. 27 RXD_0+ HDMI input Digital Input Channel 0 True of Port D in the HDMI Interface. 28 CGND Ground TVDD and CVDD Ground. 29 RXD_1 H

9、DMI input Digital Input Channel 1 Complement of Port D in the HDMI Interface. 30 RXD_1+ HDMI input Digital Input Channel 1 True of Port D in the HDMI Interface. 31 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 32 RXD_2 HDMI input Digital Input Channel 2 Complement of Port D in the HDMI Inte

10、rface. 33 RXD_2+ HDMI input Digital Input Channel 2 True of Port D in the HDMI Interface. 34 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 35 CGND Ground TVDD and CVDD Ground. 36 TXPVDD Power 1.8 V Power Supply for Digital and I/O Power Supply. This pin supplies power to the digital logic a

11、nd I/Os. It should be fltered and as quiet as possible. 37 TXPLVDD Power 1.8 V Power Supply. 38 TXGND Ground TXPVDD Ground. 39 TXPGND Ground TXPLVDD Ground. 40 EXT_SWING Analog input This pin sets the internal reference currents. Place an 887 resistor (1% tolerance) between this pin and ground. 41 H

12、PD_ARC Analog input Hot Plug Detect Signal. This pin indicates to the interface whether the receiver is connected. It supports 1.8 V to 5 V CMOS logic levels. 42 ARC+ Analog input Audio Return Channel Input (5 V Tolerant). 43 TXDDC_SDA Digital I/O Serial Port Data I/O to Receiver. This pin serves as

13、 the master to the DDC bus. It supports a 5 V CMOS logic level. 44 TXDDC_SCL Digital output Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. It supports a 5 V CMOS logic level. 45 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. 46 TXGND Ground TXAVDD Ground.

14、 47 TXC HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 48 TXC+ HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 49 TXGND Ground TXAVDD Ground. 50 TX0 HDMI output Difere

15、ntial Output Channel 0 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 51 TX0+ HDMI output Diferential Output Channel 0 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGND Ground TXAVDD Ground.

16、 53 TX1 HDMI output Diferential Output Channel 1 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI output Diferential Output Channel 1 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 55 T

17、XAVDD Power 1.8 V Power Supply for TMDS Outputs. 124 Pin No. Mnemonic Type Description 99 PGND Ground PVDD Ground. 100 PVDD Power PLL Supply Voltage (1.8 V). 101 XTAL Miscellaneous analog Input pin for 28.63636 MHz crystal or an external 1.8 V 28.63636 MHz clock oscillator source to clock the ADV762

18、3. 102 XTAL1 Miscellaneous analog Crystal Output Pin. This pin should be left foating if a clock oscillator is used. 103 PVDD Power PLL Supply Voltage (1.8 V). 104 PGND Ground PVDD Ground. 105 HP_CTRLA Digital output Hot Plug Detect for Port A. 106 5V_DETA Digital input 5 V Detect Pin for Port A in

19、the HDMI Interface. 107 RTERM Miscellaneous analog This pin sets the internal termination resistance. A 500 resistor between this pin and ground should be used. 108 DDCA_SDA Digital I/O HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant. 109 DDCA_SCL Digital input H

20、DCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. 110 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 111 CGND Ground TVDD and CVDD Ground. 112 RXA_C HDMI input Digital Input Clock Complement of Port A in the HDMI Interface. 113 RXA_C+ HDMI input Digital Input Clo

21、ck True of Port A in the HDMI Interface. 114 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 115 RXA_0 HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface. 116 RXA_0+ HDMI input Digital Input Channel 0 True of Port A in the HDMI Interface. 117 CGND Ground TVDD and CV

22、DD Ground. 118 RXA_1 HDMI input Digital Input Channel 1 Complement of Port A in the HDMI Interface. 119 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface. 120 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 121 RXA_2 HDMI input Digital Input Channel 2 Complement o

23、f Port A in the HDMI Interface. 122 RXA_2+ HDMI input Digital Input Channel 2 True of Port A in the HDMI Interface. 123 HP_CTRLB Digital output Hot Plug Detect for Port B. 124 5V_DETB Digital input 5 V Detect Pin for Port B in the HDMI Interface. 125 DGND Ground DVDD Ground. 126 DVDD Power Digital S

24、upply Voltage (1.8 V). 127 DDCB_SDA Digital I/O HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant. 128 DDCB_SCL Digital input HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. 129 CVDD Power Receiver Comparator Supply Voltage (1.8 V).

25、130 CGND Ground TVDD and CVDD Ground. 131 RXB_C HDMI input Digital Input Clock Complement of Port B in the HDMI Interface. 132 RXB_C+ HDMI input Digital Input Clock True of Port B in the HDMI Interface. 133 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 134 RXB_0 HDMI input Digital Input Cha

26、nnel 0 Complement of Port B in the HDMI Interface. 135 RXB_0+ HDMI input Digital Input Channel 0 True of Port B in the HDMI Interface. 136 CGND Ground TVDD and CVDD Ground. 137 RXB_1 HDMI input Digital Input Channel 1 Complement of Port B in the HDMI Interface. 138 RXB_1+ HDMI input Digital Input Ch

27、annel 1 True of Port B in the HDMI Interface. 139 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 140 RXB_2 HDMI input Digital Input Channel 2 Complement of Port B in the HDMI Interface. 141 RXB_2+ HDMI input Digital Input Channel 2 True of Port B in the HDMI Interface. 142 HP_CTRLC Digital o

28、utput Hot Plug Detect for Port C. 143 5V_DETC Digital input 5 V Detect Pin for Port C in the HDMI Interface. 144 DDCC_SDA Digital I/O HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input/output that is 5 V tolerant. 125 ADV7623 Block diagram CH0 CH1 CH2 VIDEO DATA DE VS HS AUDIO DATA VIDEO DATA

29、DE VS HS AUDIO DATA VIDEO DATA DE VS HS AUDIO DATA VIDEO DATA DE VS HS AUDIO DATA XTAL XTAL1 RXA_C RXB_C RXC_C RXD_C RXA_0 RXA_1 RXA_2 VIDEO/AUDIO CLOCK GENERATION RX PLL CEC TXC TX0 TX1 TX2 5V DETECT COMPONENT PROCESSOR SCL SDATA ALSB CS I2C CONTROLLER PWRDN RESET GLOBAL CONTROLS DDCA_SDA DDCA_SCL

30、DDCB_SDA DDCB_SCL DDCC_SDA DDCC_SCL DDCD_SDA DDCD_SCL AP0_IN AP1_IN AP2_IN AP3_IN AP4_IN AP5_IN SCLK_IN MCLK_IN AP0_OUT AP1_OUT AP2_OUT AP3_OUT AP4_OUT AP5_OUT SCLK_OUT MCLK_OUT ARC+ RX EDID/ REPEATER CONTROLLER RX HPD CONTROLLER EP_MISO EP_MOSI EP_CS EP_SCK SPI MASTER/ SLAVE EQUALIZER RXB_0 RXB_1 R

31、XB_2 EQUALIZER SAMPLER SAMPLER RXC_0 RXC_1 RXC_2 EQUALIZERSAMPLER RXD_0 RXD_1 RXD_2 EQUALIZER CEC CONTROLLER EDID RAM SAMPLER HDMI RECEIVER PROCESSOR TRANSMITTER PACKET BUILDER HDCP ENCRYPTION ENGINE HDMI ENCODER SERIALIZER TMDS DRIVERS INT1 INT2 INT_TX INTERRUPT CONTROLLER TXDDC_SDA TXDDC_SCL TX ED

32、ID/HDCP CONTROLLER EDID/HDCP BUFFER HPD_ARC TX HPD CONTROLLER HDCP DECRYPTION ENGINE SYNC MEASUREMENT PACKET PROCESSOR INFOFRAME PACKET MEMORY AUDIO PROCESSOR ARC RECEIVER AUDIO CAPTURE HDCP KEYS TX PLL ADV7623 5V_DETA 5V_DETB 5V_DETC 5V_DETD HP_CTRLA HP_CTRLB HP_CTRLC HP_CTRLD OSD 126 DIGITAL_HDMI_

33、ADV7623 : IC732 MX25L3206EM2I-12G (except : E2) MX25L6406EM2I-12G (ONLY E2) SN74CBT3251PWR (DIGITAL_HDMI_ADV7623 : IC733) Block diagram CS#1 2 3 4 8 7 6 5 SO/SIO1 WP# GND VCC HOLD# SCLK SI/SIO0 SYMBOL CS# SI/SIO0 SO/SIO1 SCLK WP# HOLD# VCC GND Chip Select Serial Data Input (for 1 x I/O)/ Serial Data

34、 Input AECQ100 Qualified and PPAP Capable. MC14094B 5 3STATE TEST CIRCUIT FOR tPHZ AND tPZH VSS FOR tPLZ AND tPZL VDD R1 OUTPUT 50 pF O.E. CLOCK ST DATA Figure 1. R1 = 1 k = tPHL, tPLH R1 = 10 k = tPHZ, tPZH, tPLZ, tPZL REGISTER STAGE 1 BLOCK DIAGRAM LATCH 13-STATE BUFFER 1 15 2 SERIAL DATA IN OUTPU

35、T ENABLE CLOCKCLOCKSTROBE CLOCK CLOCKCLOCK CLOCK STROBE STROBE STROBE VDD 4 5 6 7 14 13 12 11 10 9 Q1 Q2 QS Q3 Q4 Q5 Q6 Q7 Q8 QS 2 3 4 5 6 7 8 REGISTER STAGE 2 REGISTER STAGE 3 REGISTER STAGE 4 REGISTER STAGE 5 REGISTER STAGE 6 REGISTER STAGE 7 REGISTER STAGE 8 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH

36、6 LATCH 7 LATCH 8 3-STATE BUFFER2 3-STATE BUFFER3 3-STATE BUFFER4 3-STATE BUFFER5 3-STATE BUFFER6 3-STATE BUFFER7 3-STATE BUFFER8 CLOCKCLOCKSTROBE STROBE CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK STROBE STROBE CLOCK STROBE 3 1 *Input Protection Diodes * * * * 133 R1EX24128BSASOI (DIGITAL_MCU : IC752) Bloc

37、k diagram Pin Function Descriptions SN74LVC244APWR (DIGITAL_MCU LEVEL CHG : IC761) (DIGITAL_DSP : IC783) Block diagram Orderable Part numbers Internal organization Package Shipping tape and reel Halogen free Inner wire ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Orderable Par

38、t numbers Internal organization Package Shipping tape and reel Halogen free Inner wire ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Orderable Part numbers Internal organization Package Shipping tape and reel Halogen free Inner wire ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?

39、 ? ? ? ? ? ? ? ? ? ? ? FEATURES DESCRIPTION/ORDERING INFORMATION 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW) SN74LVC244A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS41

40、4XNOVEMBER 1992REVISED MARCH 2005 Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Specified From 40C to 85C and 40C to 125C Max tpdof 5.9 ns at 3.3 V Typical VOLP(Output Ground Bounce) 2 V at VCC= 3.3 V, TA= 25C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltag

41、e With 3.3-V VCC) IoffSupports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) This octal buffer/line driver is operational at 1.5-V to 3.

42、6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCCoperation. ORDERING INFORMATION TAPACKAGE(1)ORDERABLE PART NUMBERTOP-SIDE MARKING QFN RGYReel of 1000SN74LVC244ARGYRLC244A 40C to 85CVFBGA GQNSN74LVC244AGQNR Reel of 1000LC244A VFBGA ZQN (Pb-Free)SN74LVC244AZQNR PDIP NTube of 20SN74LVC244A

43、NSN74LVC244AN Tube of 25SN74LVC244ADW SOIC DWLVC244A Reel of 2000SN74LVC244ADWR SOP NSReel of 2000SN74LVC244ANSRLVC244A 40C to 125CSSOP DBReel of 2000SN74LVC244ADBRLC244A Tube of 70SN74LVC244APW TSSOP PWReel of 2000SN74LVC244APWRLC244A Reel of 250SN74LVC244APWT TVSOP DGVReel of 2000SN74LVC244ADGVRLC

44、244A (1)Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclai

45、mers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright 19922005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessaril

46、y include testing of all parameters. 1 218 1Y1 1OE 1A1 416 1Y21A2 614 1Y31A3 812 1Y41A4 19 119 2Y1 2OE 2A1 137 2Y22A2 155 2Y32A3 173 2Y42A4 Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages. Absolute Maximum Ratings(1) SN74LVC244A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS414

47、XNOVEMBER 1992REVISED MARCH 2005 LOGIC DIAGRAM (POSITIVE LOGIC) over operating free-air temperature range (unless otherwise noted) MINMAXUNIT VCCSupply voltage range0.56.5V VIInput voltage range(2)0.56.5V VOVoltage range applied to any output in the high-impedance or power-off state(2)0.56.5V VOVolt

48、age range applied to any output in the high or low state(2)(3)0.5VCC+ 0.5V IIKInput clamp currentVI 050mA IOKOutput clamp currentVO 050mA IOContinuous output current50mA Continuous current through VCCor GND100mA DB package(4)70 DGV package(4)92 DW package(4)58 GQN/ZQN package(4)78 JAPackage thermal impedanceC/W N package(4)69 NS package(4)60 PW pac