Denon-DVD5910-dvd-sm维修电路原理图.pdf

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1、SERVICE MANUAL DVD AUDIO-VIDEO / SUPER AUDIO PLAYER MODELDVD-5910 For U.S.A. read only during reset. TDMDR28ITDM receive data input. TDMCLK29ITDM clock input. TDMFS30ITDM frame sync input. TDMTSC#31OTDM output enable (active-low). TWS 32 OAudio transmit frame sync output. SEL_PLL2ISystem and DSCK ou

2、tput clock frequency selection is made at the rising edge of RESET#. The matrix below lists the available clock frequencies and their respective PLL bit settings. Strapped to VCC or ground via 4.7-k resistor; read only during reset. RSELSelection 016-bit ROM 18-bit ROM SEL_PLL2SEL_PLL1SEL_PLL0PLL Se

3、ttings 000DCLK 4.5 001DCLK 5.0 010Bypass 011DCLK 4.0 100DCLK 4.25 101DCLK 4.75 110DCLK 5.5 111DCLK 6.0 43 DVD-5910/DVD-A1XV TSD0 33 OAudio transmit serial data port 0. SEL_PLL0IRefer to the description and matrix for SEL_PLL2 pin 32. TSD1 36 OAudio transmit serial data port 1. SEL_PLL1IRefer to the

4、description and matrix for SEL_PLL2 pin 32. TSD237OAudio transmit serial data output 2. TSD338OAudio transmit serial data output 3. NC48No connect pins. Leave open. MCLK39I/OAudio master clock for audio DAC. TBCK40OAudio transmit bit clock. SEL_PLL3 41 IClock source select. Strapped to VCC or ground

5、 via 4.7-k resistor; read only during reset. SPDIF_OUTOS/PDIF output. SPDIF_IN42IS/PDIF input. RSD45IAudio receive serial data. RWS46IAudio receive frame sync. RBCK47IAudio receive bit clock. XIN49I27-MHz crystal input. XOUT50O27-MHz crystal output. AVEE51PAnalog power for PLL. AVSS52GAnalog ground

6、for PLL. DMA11:053:58, 61:66ODRAM address bus. DCAS#69ODRAM column address strobe. DOE# 70 ODRAM output enable (active-low). DSCK_ENODRAM clock enable. DWE#71ODRAM write enable (active-low). DRAS#72ODRAM row address strobe (active-low). DMBS073ODRAM bank select 0. DMBS174ODRAM bank select 1. DB15:07

7、7:82, 85:90, 93:96I/ODRAM data bus. DCS1:0#97,100ODRAM chip select (active-low). DQM101OData input/output mask. ES6138F Pin Description (Continued) NamePin NumbersI/ODefinition SEL_PLL3Clock Source 0Crystal oscillator 1DCLK input 44 DVD-5910/DVD-A1XV DSCK102OOutput clock to DRAM. DCLK105IClock input

8、 to PLL. YUV0 106 OYUV pixel 2 output data. CAMIN2ICamera YUV 2. UDACOVideo DAC output. F: CVBS/chroma signal for simultaneous mode. Y: Luma component for YUV and Y/C processing. C: Chrominance signal for Y/C processing. U: Chrominance component signal for YUV mode. V: Chrominance component signal f

9、or YUV mode. YUV1 107 OYUV pixel 1 output data. VREFIInternal voltage reference to video DAC. Bypass to ground with 0.1-F capacitor. YUV2 108 OYUV pixel 2 output data. CDACOVideo DAC output. Refer to description and matrix for UDAC pin 106. YUV3 109 OYUV pixel 3 output data. COMPICompensation input.

10、 Bypass to ADVEE with 0.1-F capacitor. YUV4 110 OYUV pixel 4 output data. RSETIDAC current adjustment resistor input. ADVEE111PAnalog power for video DAC. ES6138F Pin Description (Continued) NamePin NumbersI/ODefinition Pin115114113108106 ValueF DACV DACY DACC DACU DAC 0CVBS/ChromaCVBS1YCN/A 1CVBS/C

11、hromaCVBS1YCCVBS2 2CVBS/ChromaN/AYCN/A 3CVBS/ChromaCVBS1N/AN/ACVBS2 4CVBS/ChromaCVBS1N/AN/AN/A 5CVBS/ChromaCVBS1YPbPr 6CVBS/ChromaN/AYPbPr 7N/ASYNCGBR 8CVBS/ChromaChromaYPbPr 9CVBSCVBS1GBR 10CVBSCVBS1GRB 11N/ASYNCGRB 12CVBS/ChromaN/AYPrPb 13CVBS/ChromaCVBS1YPrPb 14ChromaYGRB 45 DVD-5910/DVD-A1XV ADV

12、SS112GAnalog ground for video DAC. YUV5 113 OYUV pixel 5 output data. YDACOVideo DAC output. Refer to description and matrix for UDAC pin 106. YUV6 114 OYUV pixel 6 output data. VDACOVideo DAC output. Refer to description and matrix for UDAC pin 106. YUV7 115 OYUV pixel 7 output data. FDACOVideo DAC

13、 output. Refer to description and matrix for UDAC pin 106. CAMIN3ICamera YUV 3. PCLK2XSCN 116 I/O27-MHz video output pixel clock. CAMIN4ICamera YUV 4. PCLKQSCN 117 O13.5-MHz video output pixel clock. CAMIN5ICamera YUV 5. AUX32I/OAux3 data I/O. VSYNC# 118 I/OVertical sync (active-low). CAMIN6ICamera

14、YUV 6. AUX31I/OAux3 data I/O. HSYNC# 119 I/OHorizontal sync (active-low). CAMIN7ICamera YUV 7. AUX30I/OAux3 data I/O. HD5:0 122:127 I/OHost data bus lines 5:0. DCI5:0I/ODVD channel data I/O. AUX15:0I/OAux1 data I/O. HD6 128 I/OHost data bus line 6. DCI6I/ODVD channel data I/O. AUX16I/OAux1 data I/O.

15、 VFD_DOUTIVFD data output. HD7 131 I/OHost data bus line 7. DCI7I/ODVD channel data I/O. AUX17I/OAux1 data I/O. VFD_DINIVFD data input. HD8 132 I/OHost data bus line 8. DCI_FDS#I/ODVD input sector start (active-low). AUX20I/OAux2 data I/O. VFD_CLKIVFD clock input. ES6138F Pin Description (Continued)

16、 NamePin NumbersI/ODefinition 46 DVD-5910/DVD-A1XV CXD2753R (MA: IC405) () Pin Assignment Block Diagram 47 DVD-5910/DVD-A1XV PIN Description Pin NameI/OFunctions 1VSC-It fixed to ground.( for Core) 2XMSLATILatch input for COM serial communication. 3MSCKIShift clock input for COM serial communication

17、. 4MSDATIIData input for COM serial communication. 5VDC-+2.5V Power for Core. 6MSDATOOData output for COM serial communication. “Hi-Z” potential except the output mode. 7MSREADYOCompletion flag of output preparation for COM serial communication. “L” is outputted at the time of completion. 8XMSDOEOOu

18、tput enable pin for COM serial communication. “L” is outputted at the time of MSDATO mode. 9XRSTIReset pin. The whole IC is reset by at the time of “L” potential. 10SMUTEIpdSoft Mute. Soft mute of the audio output is carried out at the time of “H” potential. It releases at the time of “L” potential.

19、 11MCKIIMaster Clock input. 12VSIO-It fixed to Ground. Ground for I/O. 13EXCKO1OExternal output Clock 1. 14EXCKO2OExternal output Clock 2. 15LRCKO44.1kHz, 1Fs Clock output. 16FRAMEOFrame signal output. 17VDIO-+3.3V Power for I/O. 18MNT0OMonitor output. 19MNT1OMonitor output. 20MNT2OMonitor output. 2

20、1MNT3OMonitor output. 22TESTOOOutput terminal for a Test. (open) 23TESTOOOutput terminal for a Test.(open) 24TESTOOOutput terminal for a Test.(open) 25TESTOOOutput terminal for a Test.(open) 26TCKIClock input for a Test. It fixed to “L” potential. 27TDIIpuInput pin(pull-up) for a Test.(open) 28VSC-I

21、t fixed to Ground. Ground for CORE. 29TDOOOutput for a Test.(open). 30TMSIpuInput pin(pull-up) for a Test.(open) 31TRSTIpuReset pin(pull-up) for a Test. Input the Power-on reset signal or fixed to “L” potential. 32TEST1ITest input pin. It fixed to “L” potential. 33TEST2ITest input pin. It fixed to “

22、L” potential. 34TEST3ITest input pin. It fixed to “L” potential. 35VDC-+2.5V Power for CORE. 36TESTOOOut put for TEST. It fixed to open. 37XBITODST monitor. 38SUPDT0OSupplementary data output. (LSB) 39SUPDT1OSupplementary data output. 40SUPDT2OSupplementary data output. 41SUPDT3OSupplementary data o

23、utput. 42VSIO-Ground for I/O. 43SUPDT4OSupplementary data output. 44SUPDT5OSupplementary data output. 45VDIO-+3.3V Power for I/O. 46SUPDT6OSupplementary data output. 47SUPDT7OSupplementary data output. (MSB) 48XSUPAKOSupplementary data Acknowledge output terminal. 49VSC-Ground for CORE. 48 DVD-5910/

24、DVD-A1XV 50TESTOOOutput for TEST. (open) 51TESTIIInput for TEST. It fixed to “L” potential. 52TESTIIInput for TEST. It fixed to “L” potential. 53TESTOOOutput for TEST. (open) 54VDC-+2.5V Power for CORE. 55DSADMLODSD Data output terminal for Lch Down Mix. 56DSADMRODSD Data output terminal for Rch Dow

25、n Mix. 57BCKASLII/O selection terminal of the Bit clock for DSD data output. L=input (Slave), H=output (Master) 58VSDSD-Ground terminal for DSD data output. 59BCKAIIBit clock input terminal for DSD data output. Input a Bit clock into this terminal at the time of BCKASL=”L” potential. 60BCKAOOBit clo

26、ck output terminal for DSD data output. Bit clock output from this terminal at the time of BCKASL=”H” potential. 61PHREFIIReference phase signal input terminal for DSD output phase modulation. 62PHREFOOReference phase signal output terminal for DSD output phase modulation. 63ZDFLOLch zero-data detec

27、tion flag (at the time of com setup). It will be set to “H” if non-sound data continues 300 msecs. 64DSALODSD data output terminal for Lch speaker. 65ZDFRORch zero-data detection flag (at the time of com setup). It will be set to “H” if non-sound data continues 300 msecs. 66DSARODSD data output term

28、inal for Rch speaker. 67VDDSD-+3.3V Power for DSD data output. 68ZDFCOCch zero-data detection flag (at the time of com setup). It will be set to “H” if non-sound data continues 300 msecs. 69DSACODSD data output terminal for Cch speaker. 70ZDFLFEOLFEch zero-data detection flag (at the time of com set

29、up). It will be set to “H” if non-sound data continues 300 msecs. 71DSASWODSD data output terminal for SWch speaker. 72VSDSD-Ground for DSD data output. 73ZDFLSOLSch zero-data detection flag (at the time of com setup). It will be set to “H” if non-sound data continues 300 msecs. 74DSALSODSD data out

30、put terminal for LSch speaker. 75ZDFRSORSch zero-data detection flag (at the time of com setup). It will be set to “H” if non-sound data continues 300 msecs. 76DSARSODSD data output terminal for RSch speaker. 77VDDSDO+3.3V Power for DSD data output. 78IOUT0OData output terminal 0 for IEEE1394 link c

31、hip I/F. 79IOUT1OData output terminal 1 for IEEE1394 link chip I/F. 80VSC-Ground for CORE. 81IOUT2OData output terminal 2 for IEEE1394 link chip I/F. 82IOUT3OData output terminal 3 for IEEE1394 link chip I/F. 83VDC-+2.5V Power for CORE. 84IOUT4OData output terminal 4 for IEEE1394 link chip I/F. 85IO

32、UT5OData output terminal 5 for IEEE1394 link chip I/F. 86VSIO-Ground for I/O. 87IANCOOTransmission information data output terminal for IEEE1394 link chip I/F. 88IFULLIData transmission hold request signal input terminal for IEEE1394 link chip I/F. 89IEMPTYIHigh speed transmission request signal inp

33、ut terminal for IEEE1394 link chip I/F. 90VDIO-+3.3V Power for I/O. 91IFRMOFrame reference signal output terminal for IEEE1394 link chip I/F. 92IOUTEOEnable signal output terminal for IEEE1394 link chip I/F. 93IBCKOData transmission clock output terminal for IEEE1394 link chip I/F. 94VSC-Ground for

34、CORE. 95TESTIITEST input terminal. It fixed to “H” potential. Pin NameI/OFunctions 49 DVD-5910/DVD-A1XV 96TESTIITEST input terminal. It fixed to “L” potential. 97TESTIIpuTEST input terminal. It fixed to “H” potential. 98TESTOOTEST output terminal. (open) 99VDC-+2.5V Power for CORE. 100TESTIITEST inp

35、ut terminal. It fixed to “L” potential. 101TESTIITEST input terminal. It fixed to “L” potential. 102TESTIITEST input terminal. It fixed to “L” potential. 103TESTIITEST input terminal. It fixed to “L” potential. 104TESTIITEST input terminal. It fixed to “L” potential. 105TESTIITEST input terminal. It

36、 fixed to “L” potential. 106VSIO-Ground for I/O. 107TESTIITEST input terminal. It fixed to “L” potential. 108TESTIITEST input terminal. It fixed to “L” potential. 109TESTIITEST input terminal. It fixed to “L” potential. 110VDIO-+3.3V Power for I/O. 111WAD0IExternal A/D data input terminal(LSB) for P

37、SP physical disc mark detection. 112WAD1IExternal A/D data input terminal for PSP physical disc mark detection. 113WAD2IExternal A/D data input terminal for PSP physical disc mark detection. 114WAD3IExternal A/D data input terminal for PSP physical disc mark detection. 115VSIO-Ground for I/O. 116VSC

38、-Ground for CORE. 117WAD4IExternal A/D data input terminal for PSP physical disc mark detection. 118WAD5IExternal A/D data input terminal for PSP physical disc mark detection. 119WAD6IExternal A/D data input terminal for PSP physical disc mark detection. 120WAD7IExternal A/D data input terminal(MSB)

39、 for PSP physical disc mark detection. 121VDC-+2.5V Powe for CORE. 122TESTIITEST input terminal. It fixed to “L” potential. 123WCKIOperation clock for PSP physical disc mark detection. 124WAVDD-+2.5V Power. A/D Power supply for PSP physical disc mark detection. 125WAVDD-+2.5V Power. A/D Power supply

40、 for PSP physical disc mark detection. 126WARFIAiAnalog RF signal input terminal for PSP physical disc mark detection. 127WAVRBAiA/D bottom reference terminal for PSP physical disc mark detection. 128WAVSS-A/D Ground terminal for PSP physical disc mark detection. 129WAVSS-A/D Ground terminal for PSP

41、 physical disc mark detection. 130VSIO-Ground for I/O. 131DQ7I/OSDRAM data input/output terminal. (MSB) 132DQ6I/OSDRAM data input/output terminal. 133DQ5I/OSDRAM data input/output terminal. 134DQ4I/OSDRAM data input/output terminal. 135VDIO-+3.3V Power for I/O. 136DQ3I/OSDRAM data input/output termi

42、nal. 137DQ2I/OSDRAM data input/output terminal. 138DQ1I/OSDRAM data input/output terminal. 139DQ0I/OSDRAM data input/output terminal. (LSB) 140VSIO-Ground for I/O. 141DCLKOClock output terminal for SDRAM. 142DCKEOClock enable output terminal for SDRAM. 143XWEOWrite enable output terminal for SDRAM.

43、144XCASOColomn address strobe output terminal for SDRAM. 145XRASORow address strobe output terminal for SDRAM. 146VDIO-+3.3V Power for I/O. 147TESTOOOutput terminal for TEST. (open) Pin NameI/OFunctions 50 DVD-5910/DVD-A1XV Ipu: Pull-up input Ipd: Pull-down input Ai: Analog input 148A11OAddress outp

44、ut terminal for SDRAM. (MSB) 149A10OAddress output terminal for SDRAM. 150VSC-Ground for CORE. 151A9OAddress output terminal for SDRAM. 152A8OAddress output terminal for SDRAM. 153VDC-+2.5V Power for CORE. 154A7OAddress output terminal for SDRAM. 155A6OAddress output terminal for SDRAM. 156A5OAddres

45、s output terminal for SDRAM. 157A4OAddress output terminal for SDRAM. 158VSIO-Ground for I/O. 159A3OAddress output terminal for SDRAM. 160A2OAddress output terminal for SDRAM. 161A1OAddress output terminal for SDRAM. 162A0OAddress output terminal for SDRAM. (LSB) 163VDIO-+3.3V Power for I/O. 164XSRQ

46、OOutput terminal of the Data Request signal inputted a front-end processor. 165XSHDIInput terminal of the header Flag outputted from a front-end processor. 166SDCKIInput terminal of the data conveyance Clock outputted from a front-end processor. 167XASKIInput terminal of the data valid Flag outputte

47、d from a front-end processor. 168SDEFIInput terminal of the error Flag outputted from a front-end processor. 169SD0IInput terminal of the stream Data outputted from a front-end processor. 170SD1IInput terminal of the stream Data outputted from a front-end processor. 171SD2IInput terminal of the stre

48、am Data outputted from a front-end processor. 172SD3IInput terminal of the stream Data outputted from a front-end processor. 173SD4IInput terminal of the stream Data outputted from a front-end processor. 174SD5IInput terminal of the stream Data outputted from a front-end processor. 175SD6IInput term

49、inal of the stream Data outputted from a front-end processor. 176SD7IInput terminal of the stream Data outputted from a front-end processor. Pin NameI/OFunctions 51 DVD-5910/DVD-A1XV ADSP-21266SKSTZ1B-DVD (SY: IC305) Terminal Function 1 3 6 37 73 72 108 144109 TOP VIEW PIN 1 INDICATOR Pin Name LQFP Pin #Pin Name LQFP Pin #Pin Name LQFP Pin #Pin Name LQFP Pin # VDDINT1VDDINT37VDDEXT73GND109 CLKCFG02GND38GND74VDDINT110 CLKCFG13RD39VDDINT75GND111 BOOTCFG04ALE40GND76 VDDINT112 BOOTCFG15AD1541DAI_P10 (SD2B)77GND113 GND6AD1442DAI_P11 (SD3A)78VDDINT114 VDDEXT7AD1343DAI_P12