Denon-S302-hts-sm维修电路原理图.pdf

《Denon-S302-hts-sm维修电路原理图.pdf》由会员分享，可在线阅读，更多相关《Denon-S302-hts-sm维修电路原理图.pdf（155页珍藏版）》请在收音机爱好者资料库上搜索。

1、TOKYO, JAPAN Denon Brand Company, D (5V tolerant input). TDMDX 25 OTDM transmit data output. RSELILCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-k? resistor; read only during reset. TDMDR28ITDM receive data input; (5V tolerant input). TDMCLK29ITDM clock input; (5V tolerant input)

2、. TDMFS30ITDM frame sync input; (5V tolerant input). TDMTSC#31OTDM output enable. TWS 32 OAudio transmit frame sync output. SEL_PLL2ISystem and DSCK output clock frequency selection is made at the rising edge of RESET#. The matrix below lists the available clock frequencies and their respective PLL

3、bit settings. Strapped to VCC or ground via 4.7-k? resistor; read only during reset. RSELSelection 016-bit ROM 18-bit ROM SEL_PLL2SEL_PLL1SEL_PLL0PLL Settings 000DCLK ? ?.5 001DCLK ? 5.0 010Bypass 011DCLK ? 4.0 100DCLK ? 4.25 101DCLK ? 4.75 110DCLK ? 5.5 111DCLK ? 6.0 49 S-302 TSD0 33 OAudio transmi

4、t serial data output 0. SEL_PLL0IRefer to the description and matrix for SEL_PLL2 pin 32. TSD1 36 OAudio transmit serial data output 1. SEL_PLL1IRefer to the description and matrix for SEL_PLL2 pin 32. TSD237OAudio transmit serial data output 2. This pin must be pulled down to VSS via a 4.7-k? resis

5、tor for proper operation. TSD338OAudio transmit serial data output 3. MCLK39I/OAudio master clock for audio DAC. TBCK40I/OAudio transmit bit clock. TBCK is an input during reset and subsequently is programmed as an output via the AUDIOXMT register (addr 0 x2000D00Ch, bit 4). SEL_PLL3 41 IClock sourc

6、e select. Strapped to VCC or ground via 4.7-k? resistor; read only during reset. SPDIF_OUTOS/PDIF output. SPDIF_IN42IS/PDIF input; (5V tolerant input). RSD45IAudio receive serial data; (5V tolerant input). RWS46IAudio receive frame sync; (5V tolerant input). RBCK47IAudio receive bit clock; (5V toler

7、ant input). CAMIN3 48 ICamera YUV 3. PIXIN3ICCIR656 input pixel 3. XIN49I27-MHz crystal input. XOUT50O27-MHz crystal output. AVEE51PAnalog power for PLL. AVSS52GAnalog ground for PLL. DMA11:053-58, 61-66ODRAM address bus. DCAS#69ODRAM column address strobe. DOE# 70 ODRAM output enable. DSCK_ENODRAM

8、clock enable. DWE#71ODRAM write enable. DRAS#72ODRAM row address strobe. DMBS073ODRAM bank select 0. DMBS174ODRAM bank select 1. DB15:077-82, 85-90, 93-96I/ODRAM data bus. DCS1:0#97,100ODRAM chip select. DQM101OData input/output mask. DSCK102OOutput clock to DRAM. NamePin NumbersI/ODefinition SEL_PL

9、L3Clock Source 0Crystal oscillator 1DCLK input 50 S-302 DCLK105IClock input to PLL; (5V tolerant input). UDAC 106 OVideo DAC output. F: CVBS/chroma signal for simultaneous mode. Y: Luma component for YUV and Y/C processing. C: Chrominance signal for Y/C processing. U: Chrominance component signal fo

10、r YUV mode. V: Chrominance component signal for YUV mode. YUV0OYUV pixel 0 output data. PIXOUT0OCCIR656 output pixel 0. VREF 107 IInternal voltage reference to video DAC. Bypass to ground with 0.1-?F capacitor. YUV1OYUV pixel 1 output data. PIXOUT1OCCIR656 output pixel 1. CDAC 108 OVideo DAC output.

11、 Refer to description and matrix for UDAC pin 106. YUV2OYUV pixel 2 output data. PIXOUT2OCCIR656 output pixel 2. COMP 109 ICompensation input. Bypass to ADVEE with 0.1-?F capacitor. YUV3OYUV pixel 3 output data. PIXOUT3OCCIR656 output pixel 3. RSET 110 IDAC current adjustment resistor input. YUV4OYU

12、V pixel 4 output data. PIXOUT4OCCIR656 output pixel 4. NamePin NumbersI/ODefinition Value F DAC (pin 115) V DAC (pin 114) Y DAC (pin 113) C DAC (pin 108) U DAC (pin 106) 0CVBS/ChromaCVBS1YCN/A 1CVBS/ChromaCVBS1YCCVBS2 2CVBS/ChromaN/AYCN/A 3CVBS/ChromaCVBS1N/AN/ACVBS2 4CVBS/ChromaCVBS1N/AN/AN/A 5CVBS

13、/ChromaCVBS1YPbPr 6CVBS/ChromaN/AYPbPr 7N/ASYNCGBR 8CVBS/ChromaChromaYPbPr 9CVBSCVBS1GBR 10CVBSCVBS1GRB 11N/ASYNCGRB 12CVBS/ChromaN/AYPrPb 13CVBS/ChromaCVBS1YPrPb 14ChromaYGRB 51 S-302 ADVEE111PAnalog power for video DAC. ADVSS112GAnalog ground for video DAC. YDAC 113 OVideo DAC output. Refer to des

14、cription and matrix for UDAC pin 106. YUV5OYUV pixel 5 output data PIXOUT5OCCIR656 output pixel 5. VDAC 114 OVideo DAC output. Refer to description and matrix for UDAC pin 106. YUV6OYUV pixel 6 output data. PIXOUT6OCCIR656 output pixel 6. FDAC 115 OVideo DAC output. Refer to description and matrix f

15、or UDAC pin 106. YUV7OYUV pixel 7 output data. PIXOUT7OCCIR656 output pixel 7. PCLK2XSCN 116 I/O27-MHz video output pixel clock. CAMIN4ICamera YUV 4. PIXIN4ICCIR656 input pixel 4. PCLKQSCN 117 O13.5-MHz video output pixel clock. AUX32I/OAux3 data I/O; (5V tolerant input). CAMIN5ICamera YUV 5. PIXIN5

16、ICCIR656 input pixel 5. VSYNC# 118 I/OVertical sync; (5V tolerant input). AUX31I/OAux3 data I/O; (5V tolerant input). CAMIN6ICamera YUV 6. PIXIN6ICCIR656 input pixel 6. HSYNC# 119 I/OHorizontal sync; (5V tolerant input). AUX30I/OAux3 data I/O; (5V tolerant input). CAMIN7ICamera YUV 7. PIXIN7ICCIR656

17、 input pixel 7. HD5:0 122-127 I/OHost data bus lines; (5V tolerant input). DCI5:0I/ODVD channel data I/O; (5V tolerant input). AUX15:0I/OAux1 data I/O; (5V tolerant input). HD6 128 I/OHost data bus line; (5V tolerant input). DCI6I/ODVD channel data I/O; (5V tolerant input). AUX16I/OAux1 data I/O; (5

18、V tolerant input). VFD_DOUTIVFD data output. HD7 131 I/OHost data bus line; (5V tolerant input). DCI7I/ODVD channel data I/O; (5V tolerant input). AUX17I/OAux1 data I/O; (5V tolerant input). VFD_DINIVFD data input. NamePin NumbersI/ODefinition 52 S-302 HD8 132 I/OHost data bus line; (5V tolerant inp

19、ut). DCI_FDS#I/ODVD input sector start; (5V tolerant input). AUX20I/OAux2 data I/O; (5V tolerant input). VFD_CLKIVFD clock input. HD9 133 I/OHost data bus line; (5V tolerant input). AUX21I/OAux2 data I/O; (5V tolerant input). HD10 134 I/OHost data bus line; (5V tolerant input). AUX22I/OAux2 data I/O

20、; (5V tolerant input). HD11 135 I/OHost data bus line; (5V tolerant input). AUX23I/OAux2 data I/O; (5V tolerant input). IRQOIRQ. HD12 136 I/OHost data bus line; (5V tolerant input). AUX24I/OAux2 data I/O; (5V tolerant input). C2POIC2PO error correction flag from CD-ROM; (5V tolerant input). HD13 137

21、 I/OHost data bus line; (5V tolerant input). AUX25I/OAux2 data I/O; (5V tolerant input). SPI16550 UART serial port input. HD14 140 I/OHost data bus line; (5V tolerant input). AUX26I/OAux2 data I/O; (5V tolerant input). HD15 141 I/OHost data bus line; (5V tolerant input). AUX27I/OAux2 data I/O; (5V t

22、olerant input). IRIIR remote control input; (5V tolerant input). HWRQ# 142 OHost write request. DCI_REQ#ODVD control interface request. AUX41I/OAux4 data I/O; (5V tolerant input). HRRQ# 143 OHost read request. AUX40I/OAux4 data I/O; (5V tolerant input). CAMIN2ICamera YUV 2. PIXIN2ICCIR656 input pixe

23、l 2. HIRQ 144 I/OHost interrupt. DCI_ERR#I/ODVD channel data error; (5V tolerant input). AUX47I/OAux4 data I/O; (5V tolerant input). HRST# 145 OHost reset. AUX35I/OAux3 data I/O; (5V tolerant input). HIORDY 146 IHost I/O ready. AUX33I/OAux3 data I/O; (5V tolerant input). NamePin NumbersI/ODefinition

24、 53 S-302 HWR# 149 I/OHost write. DCI_CLKI/ODVD channel data clock; (5V tolerant input). AUX45I/OAux4 data I/O; (5V tolerant input). HRD# 150 OHost read. DCI_ACK#I/ODVD channel data valid; (5V tolerant input). AUX46I/OAux4 data I/O; (5V tolerant input). HIOCS16# 151 IDevice 16-bit data transfer. AUX

25、34I/OAux3 data I/O; (5V tolerant input). CAMCLKICamera port pixel clock input. PIXIN_CLKICCIR656 input pixel clock. HCS1FX# 152 OHost select 1. AUX37I/OAux3 data I/O; (5V tolerant input). HCS3FX# 153 OHost select 3. AUX36I/OAux3 data I/O; (5V tolerant input). HA2:0 154, 155, 158 I/OHost address bus.

26、 AUX44:2I/OAux4 data I/Os; (5V tolerant input). AUX0 160 I/OAuxiliary port 0 (open collector); (5V tolerant input). I2CDATAI/OI2C data I/O; (5V tolerant input). AUX1 161 I/OAuxiliary port 1 (open collector); (5V tolerant input). I2C_CLKI/OI2C clock I/O; (5V tolerant input). AUX2 162 I/OAuxiliary por

27、t; (5V tolerant input). IOW#OI/O write strobe (LCS1). AUX3 165 I/OAuxiliary port; (5V tolerant input). IOR#OI/O read strobe (LCS1). AUX4-7166-169I/OAuxiliary ports; (5V tolerant input). LOE#170ORISC port output enable. LCS0# 173 ORISC port chip select 0. PIXOUT_CLKOCCIR656 output pixel clock. LCS3:1

28、#174-176ORISC port chip select 3:1. LD15:0 178-182, 185-191, 194-197 I/ORISC port data bus; (5V tolerant input). LWRLL#198ORISC port low-byte write enable. LWRHL#199ORISC port high-byte write enable. CAMIN0 202 ICamera YUV 0. PIXIN0ICCIR656 input pixel 0. CAMIN1 203 ICamera YUV 1. PIXIN1ICCIR656 inp

29、ut pixel 1. NamePin NumbersI/ODefinition 54 S-302 BCOIC-DM850E-CQL (IC101: 1U-3777) 55 S-302 PinNamePinNamePinNamePinName 1VSSIO53USBREF105A19157VSSIO 2AV0CLK54VSSIOUSB106A20158VDDIO 3VDDIO55VDDIOUSB107A21159A5 4AV0DATA056VDDUSBPLL108NWE160A6 5AV0DATA157VSSUSBPLL109NCS2161AV1DATA0 6AV0DATA258VSSIO11

30、0NCS1162AV1DATA1 7AV0DATA359USBXTALI111NCS0163AV1DATA2 8GPIO060USBXTALO112VSSIO164AV1DATA3 9GPIO661VDDIO113VDDIO165A7 10GPIO1162GPIO3114VDDC166A8 11GPIO1063RXD0115NOE167AV4CTRL0 12AV2DATA064GPIO1116VSSC168AV4CTRL1 13AV2DATA165TXD0117MEMCKE169A9 14AV2DATA266GPIO2118D0170A10 15VSSIO67SYNC119D1171A11 1

31、6VDDIO68MIIRXER120D2172A12 17VSSC69MIIRXCLK121D3173VSSC 18VDDC70MIIRXDV122D4174VDDC 19GPIO971VDDC123D5175VSSIO 20GPIO872VSSC124VSSIO176VDDIO 21AV4DATA073MIIRXD0125VDDIO177A13/RAS 22AV4DATA174MIIRXD1126D6178A14/CAS 23AV4DATA275MIIRXD2127D7179A15/BA0 24AV4DATA376MIIRXD3128VDDC180A16/BA1 25MIITXD377VSS

32、IO129VSSC181A17/DQM0 26MIITXD278VDDIO130D8182A18/DQM1 27MIITXD179RXD1131D9183NWAIT 28MIITXD080TXD1132D10184VCO1 29MIITXEN81MIIPHYCLK133D11185PDOUT1 30CLKOUT82MIIDC134D12186TEST1 31VSSIO83MIIDIO135MEMCLK187NTEST2 32VDDIO84TMS136VDDIO188VSSC 33AV3CLK85TCK137VSSIO189VDDC 34AV3CTRL086VDDC138D13190NRESET

33、 35AV3CTRL187VSSC139D14191VSSIO 36VSSC88VSSIO140D15192VDDIO 37USBVBUSDRV89VDDIO141SPICLK193VCO0 38VDDC90NC142SPINCS1194PDOUT0 39AV3DATA091TEST5143SPINCS0195AV4CLK 40AV3DATA192NC144VDDC196AV0CTRL0 41MIITXCLK93TDI145VSSC197AV0CTRL1 42MIITXER94TDO146SPIMISO198AV2CLK 43VDDIO95VDDC147SPIMOSI199AV2CTRL0 4

34、4AV3DATA296VSSC148NTEST3200AV2CTRL1 45VSSIO97MIICRS149NTEST4201VDDIO 46AV3DATA398MIICOL150VSSIO202VSSIO 47VDDUSB99GPIO15151VDDIO203XTALI 48USBD+100GPIO14152A0204XTALO 49USBD-101GPIO13153A1205VDDPLL 50VSSUSB102GPIO12154A2206VSSPLL 51USBVBUS103VDDIO155A3207VDDDCO 52USBID104VSSIO156A4208VSSDCO 56 S-302

35、 DSP21367 (IC401: 1U-3808) 57 S-302 M3087BFKBGP (IC201: 1U-3808) Pin No FunctionPort name Port setting INITPUExplanation 1P96N.C.O-OPEN 2P95N.C.O-OPEN 3P94ON/_STBYO-ON/OFF control of MAIN POWER 4P93OSD_ACKIPuOSD controller communication ACK input 5P92OSD_MTXDSOPuOSD controller communication data out

36、put 6P91OSD_DRXDSIPu OSD controller communication data intput 7P90OSD_CLKSO-OSD controller communication clock output 8P146N.C.O-OPEN 9P145N.C.O-OPEN 10P144N.C.O-OPEN 11P143N.C.O-OPEN 12P142_TEMP_DETIPuTemperature malfunction detection signal (malfunction detection : L) 13P141AUX_SWIFRPuPlug inserti

37、on detection signal of front AUX input (Connected: H) 14P140HP_SWIFRPuHeadphone insertion detection signal (Connected: H) 15-Connect to GND 16CNVSS1IPdInternal flash memory update choice signal 17P87RESERVE 32.768KO-Sub clock circuit (OPEN) 32.768kHz 18P86RESERVE 32.768KO-Sub clock circuit (OPEN) 32

38、.768kHz 58 S-302 19Pu DNS RESET 20O-24MHz 21-Connect to GND 22I-24MHz 23-Connect to 3.3V 24P85NMII-Connect to VCC 25P84_REMOTEINTFRPu DNS Remote control signal interruption Pu is built in Photo Detectors. 26P83_PROTECTINTPu DNS Protect detection interruption of main (Protect:L) 27P82E_REQINTPdDM850

39、communications need interruption 28P81P_DOWN( 50/60Hz )ECPu DNS Power supply 50/60Hz pulse signal input 29P80IPOD_MRXDSIPu DNS Rxd data input from iPod connect 30P77N.C.O-OPEN 31P76IPOD_MTXDSOPu DNS Txd data output to of iPod connect 32P75VOL_BIFRPu DNS JOG pulse input B for VOL 33P74VOL_AIFRPu DNS

40、JOG pulse input A for VOL 34P73PWB_CHKIPdP.W.B check mode (H:P.W.B check mode) 35P72BE_CLKSIBEpdSCI CLK input from ESS 36P71BE_MRXDSIBEPuSCI DATA input from ESS 37P70BE_MTXDSOBEPuSCI DATA output to ESS 38P67SYS_MTXD(AMX TXD)SOPu DNS TxD data output to AMX 39-Connect to +3.3V 40P66SYS_MRXD(AMX RXD)SI

41、Pu DNS RxD data input to AMX 41-Connect to GND 42P65_E_RSTOPdReset of DM850 43P64E_MODEIPdEMODE input from DM850 44P63IPOD_D_MTXDSOPu DNS TxD data output to of iPod Dock 45P62IPOD_D_MRXDSIPu DNS Rxd data input from of iPod Dock 46P61F_EXT_CKOFR-FRONT PANEL extended output port IC (BU2090F) for seria

42、l clock output LED lighting 47P60F_EXT_DAOFR-FRONT PANEL extended output port IC (BU2090F) for serial data output LED lighting 48P137_E_SPICSO-SCI CE signal output to DM850 49P136E_CLKSO-SCI CLK output to DM850 50P135E_DINSI-SCI DATA input from DM850 51P134E_DOUTSO-SCI DATA output to DM850 52P57DC/D

43、C_ONOON/OFF control output of DC/DC CONV. ( ON: H) 53P56N.C.O-OPEN 54P55F_EPM1O-Flash rewriting 55P54IPOD_IDO-iPod Accessary ID control signal(H:Connected, L:Unconnected) 56P133_SAN_RSTOPdReset output to of tuner RDS IC (L:Reset) 57-Connect to GND 58P132_TU_MUOPdMute output of tuner (L:MUTE, H:MUTE

44、OFF) 59-Connect to +3.3V 60P131TU_POWEROPdPower supply of tuner (+12V/+5V) ON/OFF H:P.ON 61P130IPOD_CNTIPu DNS Connected detection of iPod (H:Unconnected, L:Connected) 62P53IPOD_ONO-iPod Charge POWER control (Charge ON:H) 63P52_CHOP_ONOpdPOWER ON/OFF control output of peripheral circuit (H:OFF, L:ON

45、) 64P51_OSD_RSTOPdReset to OSD uCom 65P50F_CE1O- 66P127FAN ON/OFFOPdFAN ON/OFF control H:FAN ON 67P126FAN SPEEDO-FAN SPEED control H:Slow L:Fast 68P125N.C.O-OPEN 69P47N.C.O-OPEN 70P46N.C.O-OPEN 71P45N.C.O-OPEN 72P44N.C.O-OPEN 73P43N.C.O-OPEN 74-Connect to +3.3V 75P42IPOD_PROTECTIPuiPod protect detec

46、tion (H:FNormal, L:GProtect) 76-Connect to GND 77P41N.C.O-OPEN 78P40H/P MUTE_MAINOPuHeadphone MUTE signal(MUTE:H) 79P37PRE_MUTE_MAINOPuPreOut MUTE signal (MUTE:H) 80P36SP_CONIpuSpeaker connection detection (SP connected:H) 81P35SP_RLOPuRelay MUTE signal for FRONT/SW speaker (Relay ON:H) 82P34IPod MU

47、TEOPuiPod output MUTE (MUTE:H) 83P33DRV_ONOBE-DVD (ESS) power supply ON/OFF control of unit (ON:H) 84P32SYS_REQOBE-Communication start request signal to ESS Pin No FunctionPort name Port setting INITPUExplanation 59 S-302 85P31N.C.-OPEN 86P124_BE RSTOBEPdDVD (ESS) reset signal of unit 87P123BE ONIBE

48、PdInput of ESS IC Active state output signal 88P122N.C.-OPEN 89P121N.C.O-OPEN 90P120N.C.O-OPEN 91- 92P30OSD_VUPO-OSD version up change selecting signal 93- 94P27VUP_SEL2O-Version upgrade UART switching selection 2 95P26VUP_SEL1O-Version upgrade UART switching selection 1 96P25TU_STEREOIPuStereo indi

49、cator input of tuner 97P24TUNEDIPuBureau existence detection input of tuner 98P23SAN_CEO-Communication chip enable output to tuner PLL/RDS IC/FUNCTION IC(SANYO BUS) 99P22SAN_MOSIO-Cereal data output to tuner PLL/RDS IC/FUNCTION IC(SANYO BUS) 100P21SAN_CKO-Cereal clock output to tuner PLL/RDS IC/FUNCTION(SANYO BUS) 101P20SAN_MISOIPuCereal data input from tuner PLL/RDS IC(SANYO BUS) 102P17BE_CSINTBEPdCS interrupt of communication with ESS 103P16_BE_AUDIO_RSTINTBEPuAudio reset interrupt from ESS 104P15SUB_REQINTAUPuSUB uCom (AUDIO/VIDEO) communication demand interrupt 105P14E2P