HarmanKardon-AVR354-avr-sm3维修电路原理图.pdf

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1、MK2302S-01 MDS 2302S-01 B Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 Multiplier and Zero Delay Buffer Description The MK2302S-01is a high performance Zero Delay Buffer (ZDB) which integrates ICS proprietary analog/digital Phase Locked Loop (PLL) technique

2、s. The chip is part of ICS ClockBlocksTM family and was designed as a performance upgrade to meet todays higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no d

3、elay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other output. The MK2302S-01 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. By allowing off-chip feedback paths,

4、the device can eliminate the delay through other devices. Features 8 pin SOIC package Low input to output skew of 250ps max Absolute jitter 500ps Propagation Delay 350ps Ability to choose between different multipliers from 0.5X to 16X Output clock frequency up to 133 MHz at 3.3V Can recover degraded

5、 input clock duty cycle Output clock duty cycle of 45/55 Full CMOS clock swings with 25mA drive capability at TTL levels Advanced, low power CMOS process Operating voltage of 3.3V or 5V Industrial temperature version available Block Diagram Phase Detector, Charge Pump, and Loop Filter divide by N CL

6、K1 External feedback can come from CLK1 or CLK2 (see table on page 2) ICLK FBIN S1:0 VCO CLK2 /2 130 AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 Multiplier and Zero Delay Buffer MDS 2302S-01 B Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 MK230

7、2S-01 Pin Assignment Clock Multiplier Decoding Table 1 (Multiplies Input clock by shown amount) Pin Descriptions FBIN ICLK GND VDD S0 CLK1 CLK21 2 3 4 8 7 6 5 GND S1 1 2 3 4 8 7 6 5 8 pin (150 mil) SOIC FBINS1S0CLK1CLK2 CLK1002 X ICLKICLK CLK1014 X ICLK2 X ICLK CLK110ICLKICLK/2 CLK1118 X ICLK4 X ICL

8、K CLK2004 X ICLK2 X ICLK CLK2018 X ICLK4 X ICLK CLK2102 X ICLKICLK CLK21116 X ICLK8 XICLK Pin Number Pin Name Pin Type Pin Description 1FBINInputFeedback clock input. 2ICLKInputReference clock input. 3GNDPowerConnect to ground. 4S0InputSelect 0 for output clock per decoding table above. Pull-up. 5S1

9、InputSelect 1 for output clock per decoding table above. Pull up. 6CLK1OutputClock output per table above. 7VDDPowerConnect to +3.3V or +5.0V. 8CLK2OutputClock output per table above. Low skew divide by two of pin 6 clock. 131 AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 Multiformat Vid

10、eo Encoder Six, 11-Bit, 297 MHz DACs ADV7342/ADV7343 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from

11、 its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-910

12、6, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 2006 Analog Devices, Inc. All rights reserved. FEATURES 74.25 MHz 20-/30-bit high definition input support Compliant with SMPTE 274M (1080i), 296M (720p), and 240M (1035i) 6, 11-bit, 297 MHz video DACs 16 (216 MHz) DAC oversampling for SD 8 (216 MHz) DAC

13、 oversampling for ED 4 (297 MHz) DAC oversampling for HD 37 mA maximum DAC output current NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz) Multiformat video input support 4:2:2 YCrCb (SD, ED, and HD) 4:4:4 YCrCb (ED and HD) 4:4:4 RGB (SD, ED, and HD)

14、 Multiformat video output support Composite (CVBS) and S-Video (Y/C) Component YPrPb (SD, ED, and HD) Component RGB (SD, ED, and HD) Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant Simultaneous SD and ED/HD operation EIA/CEA-861B compliance support Programmable features Luma and chroma filter

15、 responses Vertical blanking interval (VBI) Subcarrier frequency (FSC) and phase Luma delay Copy generation management system (CGMS) Closed captioning and wide screen signaling (WSS) Integrated subcarrier locking to external video source Complete on-chip video timing generator On-chip test pattern g

16、eneration On-board voltage reference (optional external input) Serial MPU interface with dual I2C and SPI compatibility 3.3 V analog operation 1.8 V digital operation 3.3 V I/O operation Temperature range: 40C to +85C APPLICATIONS DVD recorders and players High definition Blu-ray DVD players HD-DVD

17、players FUNCTIONAL BLOCK DIAGRAM R GND_IO VDD_IO 10-BIT SD VIDEO DATA 20-BIT ED/HD VIDEO DATA S_HSYNCP_HSYNC P_VSYNC P_BLANKS_VSYNC 11-BIT DAC 1 DAC 1 11-BIT DAC 2 DAC 2 11-BIT DAC 3 DAC 3 11-BIT DAC 4 DAC 4 11-BIT DAC 5 DAC 5 11-BIT DAC 6 DAC 6 MULTIPLEXER REFERENCE AND CABLE DETECT 16x/4x OVERSAMP

18、LING DAC PLL VIDEO TIMING GENERATOR POWER MANAGEMENT CONTROL CLKIN (2) PVDDPGND EXT_LF (2) VREFCOMP (2) RSET (2) ED/HD INPUT DEINTERLEAVE PROGRAMMABLE HDTV FILTERS SHARPNESS AND ADAPTIVE FILTER CONTROL YCbCr HDTV TEST PATTERN GENERATOR YCbCr TO RGB MATRIX G/B RGB ASYNC BYPASS RGB DGND (2)VDD (2) SCL

19、/ MOSI SDA/ SCLK ALSB/ SPI_SS SFL/ MISO MPU PORT SUBCARRIER FREQUENCY LOCK (SFL) YUV TO YCrCb/ RGB PROGRAMMABLE CHROMINANCE FILTER ADD BURST RGB/YCrCb TO YUV MATRIX 4:2:2 TO 4:4:4 HD DDR DEINTERLEAVE SIN/COS DDS BLOCK 16 FILTER 16 FILTER 4 FILTER AGNDVAA ADD SYNC VBI DATA SERVICE INSERTION PROGRAMMA

20、BLE LUMINANCE FILTER 06399-001 ADV7342/ADV7343 Figure 1. Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights. Protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. 132 AVR354 harman/kardonharman/kardon Rad

21、ioFans.CN 收音机爱 好者资料库 ADV7342/ADV7343 Rev. 0 | Page 18 of 88 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 GND_IO 63 CLKIN_B 62 S7 61 S6 60 S5 59 S4 58 S3 57 DGND 56 VDD 55 S2 54 S1 53 S0 52 TEST5 51 TEST4 50 S_HSYNC 49 S_VSYNC 47RSET1 46VREF 45COMP1 42DAC 3 43DAC 2 44DAC 1 48SFL/MISO 41VAA 40AGND 3

22、9DAC 4 37DAC 6 36RSET2 35COMP2 34PVDD 33EXT_LF1 38DAC 5 2TEST0 3TEST1 4 Y0 7Y3 6Y2 5Y1 1 VDD_IO 8Y4 9Y5 10VDD 12Y6 13Y7 14 TEST2 15 TEST3 16 C0 11 DGND 17 C1 18 C2 19 ALSB/SPI_SS 20 SDA/SCLK 21 SCL/MOSI 2223 P_HSYNC 24 P_VSYNC 25 P_BLANK 26 C4 C3 27 C5 28 C6 29 C7 30 CLKIN_A 3132 PGND PIN 1 ADV7342/

23、ADV7343 TOP VIEW (Not to Scale) EXT_LF2 06399-021 Figure 21. Pin Configuration Table 13. Pin Function Descriptions Pin No. Mnemonic Input/ Output Description 13, 12, 9 to 4 Y7 to Y0 I 8-Bit Pixel Port. Y0 is the LSB. Refer to Table 31 for input modes. 29 to 25, 18 to 16 C7 to C0 I 8-Bit Pixel Port.

24、C0 is the LSB. Refer to Table 31 for input modes. 62 to 58, 55 to 53 S7 to S0 I 8-Bit Pixel Port. S0 is the LSB. Refer to Table 31 for input modes. 52, 51, 15, 14, 3, 2 TEST5 to TEST0 I Unused. These pins should be connected to DGND. 30 CLKIN_A I Pixel Clock Input for HD Only (74.25 MHz), ED1 Only (

25、27 MHz or 54 MHz) or SD Only (27 MHz). 63 CLKIN_B I Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a 74.25 MHz reference clock for HD operation. 50 S_HSYNC I/O SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or

26、HD horizontal synchronization signal. See the External Horizontal and Vertical Synchronization Control section. 49 S_VSYNC I/O SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD vertical synchronization signal. See the External Horizontal and Vertical Sync

27、hronization Control section. 22 P_HSYNC I ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical Synchronization Control section. 23 P_VSYNC I ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization Control section. 24 P_BLANK I ED/H

28、D Blanking Signal. See the External Horizontal and Vertical Synchronization Control section. 48 SFL/MISO I/O Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data Output. The SFL input is used to drive the color subcarrier DDS system, timing reset, or subcarrier reset. 47 RSET1 I This

29、pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive operation (for example, into a 37.5 load), a 510 resistor must be connected from RSET1 to AGND. For low drive operation (for example, into a 300 load), a 4.12 k resistor must be connected from RSET1 to AGND.

30、 133 AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 ADV7342/ADV7343 Rev. 0 | Page 19 of 88 Pin No. Mnemonic Input/ Output Description 36 RSET2 I This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 k resistor must be connected from RSET2 to AGND. 45, 3

31、5 COMP1, COMP2 O Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to VAA. 44, 43, 42 DAC 1, DAC 2, DAC 3 O DAC Outputs. Full and low drive capable DACs. 39, 38, 37 DAC 4, DAC 5, DAC 6 O DAC Outputs. Low drive only capable DACs. 21 SCL/MOSI I Multifunctional Pin: I2C Clock Input/SPI

32、Data Input. 20 SDA/SCLK I/O Multifunctional Pin: I2C Data Input/Output. Also, SPI clock input. 19 ALSB/SPI_SS I Multifunctional Pin: This signal sets up the LSB2 of the MPU I2C address. Also, SPI slave select. 46 VREF Optional External Voltage Reference Input for DACs or Voltage Reference Output. 41

33、 VAA P Analog Power Supply (3.3 V). 10, 56 VDD P Digital Power Supply (1.8 V). For dual-supply configurations, VDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering. 1 VDD_IO P Input/Output Digital Power Supply (3.3 V). 34 PVDD P PLL Power Supply (1.8 V). For dual

34、-supply configurations, PVDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering. 33 EXT_LF1 I External Loop Filter for On-Chip PLL 1. 31 EXT_LF2 I External Loop Filter for On-Chip PLL 2. 32 PGND G PLL Ground Pin. 40 AGND G Analog Ground Pin. 11, 57 DGND G Digital G

35、round Pin. 64 GND_IO G Input/Output Supply Ground Pin. 1 ED = enhanced definition = 525p and 625p. 2 LSB = least significant bit. In the ADV7342, setting the LSB to 0 sets the I2C address to 0 xD4. Setting it to 1 sets the I2C address to 0 xD6. In the ADV7343, setting the LSB to 0 sets the I2C addre

36、ss to 0 x54. Setting it to 1 sets the I2C address to 0 x56. 134 AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 135 AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 IC51 XM IC 136 AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 137 AVR354 harman/kardonharman/kardon Radio

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38、rdon RadioFans.CN 收音机爱 好者资料库 143 AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 144 AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 145 AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 146 AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 147 AVR354 harman/kardo

39、nharman/kardon RadioFans.CN 收音机爱 好者资料库 148 AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 ST232 5V POWERED MULTI-CHANNEL RS-232 DRIVERS AND RECEIVERS February 2001 ISUPPLYVOLTAGERANGE: 4.5TO5.5V ISUPPLYCURRENT NOLOAD(TYP):5mA ITRANSMITTEROUTPUT VOLTAGESWING (TYP):7.8V ICONTROLLEDOUTPUTSLE

40、WRATE IRECEIVERINPUTVOLTAGERANGE: 30V IDATARATE(TYP):220Kbps IOPERATINGTEMPERATURERANGE: -40TO85 oC,0TO70oC ICOMPATIBLEWITH MAX232ANDMAX202 DESCRIPTION The ST232 is a 2 driver, 2 receiver device following EIA/TIA-232 and V.28 communication standard.It is particularly suitable for applications where

41、12V is not available. The ST232 uses a single 5V power supply and only four external capacitors (0.1F). Typical applications are in: PortableComputers,LowPowerModems, Interfaces Translation, Battery Powered RS-232 System,Multi-Drop RS-232 Networks. D (Micro Package) N (Plastic Package) W (Micro Pack

42、age Large) T (TSSOPPackage) ORDER CODES TypeTemperature Range PackageComments ST232CN0 to 70 oC DIP-1625 parts per tube / 40 tubeper box ST232BN-40 to 85 oC DIP-1625 parts per tube / 40 tubeper box ST232CD0 to 70 oC SO-16 (Tube)50 parts per tube / 20 tubeper box ST232BD-40 to 85 oC SO-16 (Tube)50 pa

43、rts per tube / 20 tubeper box ST232CDR0 to 70 oC SO-16 (Tape 300 16 ; 300 16 ; 500 40 +85 40 +125 () +/ I I I I ELECTRICAL CHARACTERISTICS (Ta=25 C,V+/V- = +7V/-7V, RL=47k ) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX.UNIT NN NN Power Supply 1 + 4.5 7.0 7.5 2 7.5 7.0 4.5 1 4.5 9.0 2 4.5 9.0 NN NN

44、Input/Output Characteristics (BOUTL : 2pin, BOUTR : 4pin) =1,=1% =0 3.0 4.0 =1, =1 =0 0.5 0 0.5 1 1 =1, =1 =0 0.5 0 0.5 2 2 =1, =1 =60 1.0 0 1.0 =1, =1 =95, 95 =1, =1 =, 110 =0, =0, 105 (5.6) 95 (17.8) () =1, =1, =0, =40030 0.005 0.05 % =1, =1, =0, =0 100 90 1 8 9 16 . 1 2 3 _ 4 5 6 _ 7 + + 8 9 10 1

45、10 0 121 1 13 14 15 16 177 AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 NJW1159 PIN NO. SYMBOL FUNCTION EQUIVALENT CIRCUIT TERMINAL DC VOLTAGE 3 6 _ _ 2.5 (_) 2.5 (_) 1 5 0 0 2 4 0 0 7 + + + ! TERMINAL DESCRIPTION () + () + 400 + () () 300 + 50 178 AVR354 harman/kardonharman/kardon Radi

46、oFans.CN 收音机爱 好者资料库 NJW1159 PIN NO. SYMBOL FUNCTION EQUIVALENT CIRCUIT TERMINAL DC VOLTAGE 9 10 0 11 12 13 14 15 0 1 0 1 0 16 0 () 300 + 50 + 8 () + () 179 AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 1/11September 2004 I5V TOLERANT INPUTS IHIGH SPEED: tPD = 5.2ns (MAX.) at VCC = 3V IPO

47、WER DOWN PROTECTION ON INPUTS AND OUTPUTS ISYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V IPCI BUS LEVELS GUARANTEED AT 24 mA IBALANCED PROPAGATION DELAYS: tPLH tPHL IOPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) IPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 32 ILATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) IESD PERFORMANCE: HBM 2000V (MIL STD 883 method 3015); MM 200V DESCRIPTION The 74LCX32 is a low voltage CMOS QUAD 2-INPUT OR GATE fabricated with sub-micron silicon gate an