Hitachi-DVP345E-cd-sm维修电路原理图.pdf

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1、CAUTION: Before servicing this chassis, it is important that the service technician read the “Safety Precautions” and “Product Safety Notices” in this service manual. ATTENTION: Avant deffectuer lentretien du chassis, le technicien doit lire les Prcautions de scurit et les Notices de scurit du produ

2、it prsents dans le prsent manuel. VORSICHT: Vor ffnen des Gehuses hat der Service-Ingenieur die Sicherheitshinweise“ und Hinweise zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen. SERVICE MANUAL MANUEL DENTRETIEN WARTUNGSHANDBUCH Data contained within this Service manual is subject to alte

3、ration for improvement. Les donnes fournies dans le prsent manuel dentretien peuvent faire lobjet de modifications en vue de perfectionner le produit. Die in diesem Wartungshandbuch enthaltenen Spezifikationen knnen sich zwecks Verbesserungen ndern. SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR

4、 IMPROVEMENT Digital Versatile Disk August 2004 No. 9403 DV-P345UK DV-P345E Downloaded Free from http:/www.free-service- RadioFans.CN 收音机爱 好者资料库 2 1. GENERAL DESCRIPTION 1.1 ZR36768 The ZR36768 Disc Loader Controller and Decoder Device can control disc loaders and read bitstreams using the following

5、 media: DVD-ROM, DVDRW, CD-DA, CD-ROM, CD-R and CD-R/W discs. The device can decode bitstreams and process navigation data of the following formats: DVD-Video, DVD-Audio, CD-DA, VCD (Video-CD), SVCD (Super Video-CD) and MP3. The features of this chip can be listed as follows: Disc loader control and

6、 bitstream processing 8 analog inputs (low frequency) for servo errors and RF signals envelope monitoring 11 actuators drive or control outputs. Two analog outputs through 11 bits DACs (e.g. for the tracking and focus coils), and 9 PWM outputs divided into two type groups: High frequency, “uniform”

7、type PWMs (e.g. for the spindle and sled motor drives), and lower frequency “regular” type PWMs, which can be used e.g. for programmed tray motion or RF amplifier parameter setting. Processing of spindle and sled position read-back devices All servo loop closure, closed loop control and error handli

8、ng. Bitstream extraction using AGC, bit clock frequency detection and phase lock loop, adaptive threshold calculations, Viterbi bit decision, defect detection, frame sync detection and EFM/P conversion. CD sub-code extraction and processing. CD ECC for all CD types. CD EDC for Mode 1 discs DVD ECC a

9、nd EDC. Track buffer and re-try management Decoding Single chip solution for playback of DVD-Video, DVD-Audio Video-CD, Super Video-CD, CD- DA, and MP3 from CD-ROM, CD-R or CD-R/W. Decoding and display of high resolution MPEG 1 and MPEG 2 still image sequences (including ASVs from DVD-Audio but with

10、out the transition effects). Decoding of Dolby AC-3, DTS or MLP multi-channel audio. Decoding of MPEG 1 or MPEG 2 layer II mono, stereo, or multi-channel audio. Decoding of MPEG 1 or MPEG 2 Layer 3 (MP3) mono and stereo audio. PCM and LPCM audio playback from DVD-Video, DVD-Audio, Video-CD and CD-DA

11、. Decoding and playback of sub-picture (including Highlight), and closed captions (“line 21”) data from DVD-Video discs. Interlaced digital and analog video output or progressive analog video output. NTSC and PAL standards. PAL playback of NTSC discs and NTSC playback of PAL discs. Special modes sup

12、port like pause, slow motion, fast forward and reverse. Post Processing Audio down mixing, sample rate conversion, Dolbys pro-logic and 3D enhancement. Karaoke mixing of decoded audio and two channels of input audio. On-chip OSD engine with 32 color (24-bit YUV) palette, up to 8 levels of transparen

13、cy; and capability of blinking regions and vertical scrolling. On-screen and off-screen OSD memory regions for animation support. 1/4 pixel and 1/4 line pan (high, low) - Flash+SRAM (for debug monitor); (low, high) - First debug UART; (low, low) - Flash (low) or Level sampled during RESET MEMAD0 / O

14、 / PNVM/SRAM address bus output / 49 BOOTSEL1 I CPU SW boot (and execute) source selection - Flash (low) or first debug UART (high). Level sampled during RESET 23 MEMWR# O PNVM/SRAM write enable (active low) output. 44 MEMRD# O PNVM/SRAM read enable (active low) output. Downloaded Free from http:/ww

15、w.free-service- 11 47 MEMCS0# O PNVM/SRAM chip select (active low) output MEMCS1# / O / PNVM/SRAM chip select (active low) output/ 2 GPCI/O18 I/O General purpose input/output pin, monitored/controlled by the CPU or DSP SW Power Signals (56 pins) 12,32,50 ,62,72,8 3,91,101 ,107,125 ,151,202 GNDP S Di

16、gital periphery ground of 3.3 V supply (12 pins) 3,21,41, 52,58,68 ,76,87,9 7,105,12 7,144,20 4 VDDP S 3.3 V Digital periphery power supply. (13 pins) 51,154 VDDP-IP S 3.3 V periphery reference voltage (2 pins) 117 GNDP-A2 S Digital ground of filtered 3.3 V supply for AMCLK 119 VDDP-A2 S 3.3 V filte

17、red digital power supply for AMCLK 79 GNDPCLK S Digital ground of filtered 3.3 V supply for PCLK 81 VDDPCLK S 3.3 V filtered digital power supply for PCLK 29,66,95 ,121,190 GNDC S Digital core ground of 1.8 V supply (5 pins) 25,64,93 ,123,192 VDDC S 1.8 V Digital core power supply. (5 pins) 138 GNDA

18、 S Ground plane of internal PLL circuit 140 VDDA S 1.8 V Power supply for internal PLL circuit 160 VDDDAC S 3.3 V Analog power supply for the video DACs 164 GNDDACP / S Grounds for the video DACs 3.3 V analog power supply (2 pins) 157 GNDDACD 165 GNDDABS2 S Common Ground for the video and SERVO DACs

19、 166 GNDDACPS / S Grounds for the SERVO DAC 3.3 V analog power supply (2 pins) 170 GNDDACDS 174 GNDAFERF S Analog RF (AFE) ground of 3.3 V supply 171 VDDAFERF S 3.3 V Analog RF (AFE) power supply 186 GNDAFES S Analog SERVO (AFE) ground of 3.3 V supply 175 VDDAFES S 3.3 V Analog SERVO (AFE) power sup

20、ply 168 VDDDACS S 3.3 V SERVO DACs power supply 195 GNDPWMS S SERVO PWMs ground of 3.3 V supply 197 VDDPWMS S 3.3 V SERVO PWM power supply Downloaded Free from http:/www.free-service- 12 2.1 SYSTEM BLOCK DIAGRAM A sample system block diagram for the MT1379 DVD player board design is shown in the fol

21、lowing figure: 3. AUDIO OUTPUT The ZR36768 supports two-channel to eight-channel analog audio output. This version has two- channel output. The ZR36768 also provides digital output in S/PDIF format. The board supports both optical and coaxial SPDIF outputs. 4. AUDIO DACS The ZR36768 supports several

22、 variations of an I2S type bus. The I2S format uses four stereo data lines and three clock lines. The I2S data and clock lines can be connected directly to one or more audio DAC to generate analog audio output. The two-channel DAC is a Cirrus Logic CS4392. The DACs support up to 192kHz sampling rate

23、. The outputs of the DACs are differential, not single ended so a buffering circuit is required. The buffer circuit use a National LM833 op-amp to perform the low-pass filtering and the buffering. 5 .VPU - VIDEO PROCESSING UNIT The VPU is responsible for all video output processing and timing. It ou

24、tputs 8 bit (CCIR 656 type) digital interlaced video and separate syncs. It can also output interlaced composite, S- or component analog video, or progressive components analog video. The VPU units have two operating modes: Interlaced when the output is interlaced and Progressive when the output is

25、progressive. A two fields Deinterlacer can be used (as needed) for the decoded image. The VPU has a sync generator and output unit. The sync signals are used by the sync receiver unit to generate all video timing for all other VPU units and timing signals for the CPU and PDU. Downloaded Free from ht

26、tp:/www.free-service- 13 The image post-processing unit can scale the stored image (horizontally and vertically with scale ratios of 1/2 to 2) and shift it with 1/4 pixel resolution. Then, it can enhance the image and pad it with background colour. In addition, the VPU has a DVD sub-picture decoding

27、 unit. The sub-picture is blended with the enhanced image. The resulting image is blended with an OSD image generated by a 2, 4 or 8 bits per pixel OSD Decoder. Finally, closed captions is added to generate the final digital video. The final interlaced digital video is processed by the video encoder

28、 to generate six 10 bit video streams. One stream is composite video, the next two are the luma and composite chroma components of the Svideo format. The three other streams are color components, either Y,U,V or R,G,B. Four of the sixstreams are converted to analog by four on-chip 54 MHz DACs. For t

29、hree of the four DACs, the selected combination can be: (a) Interlaced composite and S-video; (b) Three interlaced components (either Y,U,V or R,G,B); (c) Three progressive Y,U,V components. For cases (a) and (b), the fourth DAC can output either the composite signal, the luma (Y) signal, or the chr

30、oma (C) signal of the S-Video. The final progressive digital video is processed by the video encoder to generate three 10 bit video color components streams, either Y,U,V or R,G,B. The streams are converted to analog by three on-chip 54 MHz DACs. The fourth DAC has no output. 6. FLASH MEMORY The dec

31、oder board supports 70ns Flash memories. The CPU executes from a NOR type Flash memory with 16 bit data bus. Alternately, a compatible EPROM, PROM, OTPROM or masked ROM can be connected. 7. SERIAL EEPROM MEMORY An I2C serial EEPROM is used to store user configuration (i.e. language preferences, spea

32、ker setup, etc.) and software configuration. Industry standard EEPROM range in size from 1kbit to 256kbit and share the same IC footprint and pinout. The default device is 2kbit, 256kx 8, SOIC8 CSI 24WC02 or equivalent. 8. ADP - AUDIO DATA PROCESSOR The ADP is the audio processing unit of the I64. I

33、t is based on a 20 bits data and 32 bits instruction ADP44 core. The ADP core has attached to it 24 KWords (32 bits) instruction and data ROM, 5 Kwords (32 bits) instruction RAM, 8 KWords (20 bits) data RAM, 1 KWords (20 bits) data DMA caches, and several peripheral units mentioned below. The periph

34、erals are DMA interface unit, audio code interface unit, CPU and DVP interface unit, realtime clock unit, serial port unit, serial port PLL unit and interrupt handler. All the ADP peripheral units are connected to the ADP core through the AP_Bus (audio peripherals bus). The interrupt handler is also

35、 connected directly to the interrupt port of the ADP core. Several external pins (multiplexed with the digital video pins) can be used for debugging. This interface is usually called ICE (which is of course a mis-nomer as ICE means In-Circuit Emulation) but they are similar to JTAG. Downloaded Free

36、from http:/www.free-service- 14 9. PLL - PROCESSING CLOCK GENERATION UNIT The PLL unit consists of three sub-units: The PLLa unit generates (under ADP control) the audio interface master clock (AMCLK). It has 13 bits of frequency multiply and divide factors. Its input can be a separate clock generat

37、or or be (externally) tied to the clock generator or crystal input to the processing clock PLL (see below). An external control pin can indicate by-pass of this PLL unit to be used mainly for testing or for low jitter operation. The PLLp unit generates (under CPU control) the processing clocks. It h

38、as 8 bits of frequency multiply and 6 bits of divide ratios. In most cases the input clock frequency will be 27 MHz multiplied by 5 and divided by 1 to generate clk and PCLK with frequency of 135 MHz. An external control pin can indicate by-pass of this PLL unit to be used mainly for testing. The PL

39、L also generates the 27 MHz video clock signal (clk27 and VCLKx2), the encoder and DACs 54 MHz processing signal (clk54), the RF channel ADC sampling clock (rf_clk) and the servo ADC and DACs sampling clock (adc_servo_clk). The third unit is responsible to generate the internal reset signals to all

40、I64 units after detecting a proper power-up condition or a proper external reset input signal. 10. FRONT PANEL 10.1 VFD CONTROLLER The VFD controller is a PTC PT6311. This controller is not a processor, but does include a simple state machine, which scans the VFD and reads the front panel button mat

41、rix. The 6311 also includes RAM so it can store the current state of all the VFD icons and segments. Therefore, the 6311 needs only be accessed when the VFD status changes and when the button status is read. The ZR36768 can control this chip directly using PIO pins or can allow the front panel PIC t

42、o control the VFD. 11. CONNECTORS 11.1 SCART CONNECTORS Pinout of the scart connector: 1 ? Audio Right Out 2 ? Audio Right In 3 ? Audio Left / Monu Out 4 ? Audio Gnd 5 ? Blue Gnd 6 ? Audio Left / Mono In 7 ? Blue 8 ? Control Voltage 9 ? Green Gnd 10 ? Comms Data 2 11 ? Green 12 ? Comms Data 1 13 ? R

43、ed Gnd 14 ? Comms Data Gnd 15 ? Red Downloaded Free from http:/www.free-service- 15 16 ? Fast Blanking 17 ? Video Gnd 18 ? Fast Blanking Gnd 19 ? Composite Video In 20 ? Composite Video Out 21 ? Shield Some cheaper SCART cables use unshielded wires, which is just about acceptable for short cable len

44、gths. For longer lengths, shielded co-ax cable become essential. Scart Signals: Audio signals 0.5V RMS, 10K input impedance. Red, Green, Blue 0.7Vpp 2dB, 75R input and output impedance. Note that the Red connection (pin 20) can alternatively carry the S-Video Chrominance signal, which is 0.3V. Compo

45、site Video / CSync 1Vpp including sync, 2dB, 75R input and output impedance.Bandwidth = 25Hz to 4.8MHz for normal TV Video de-emphasis to CCIR 405.1 (625-line TV) Fast Blanking 75R input and output impedance. This control voltage allows devices to over-ride the composite video input with RGB inputs,

46、 for example when inserting closed caption text. It is called fast because this can be done at the same speeds as other video signals, which is why it requires the same 75R impedances. 0 to 0.4V: TV is driven by the composite video input signal (pin 19). Left unconnected, it is pulled to 0V by its 7

47、5R termination. 1V to 3V: the TV is driven by the signals Red, Green, Blue and composite sync. The latter is sent to the TV on pin 19. This signal is useful when using a TV to display the RGB output of devices such as home computers with TV-compatible frame rates. Tying the signal to 5V via 100R for

48、ms a potential divider with the 75R termination, holding the signal at around 2V. Alternatively, if a TTL level (0 to 5V) negative sync pulse is available, this will be high during the display periods, so this can drive the blanking signal via a suitable resistor. Control Voltage 0 to 2V = TV, Norma

49、l. 5 to 8V = TV wide screen 9.5 to 12V = AV mode Downloaded Free from http:/www.free-service- 16 12. CIRCUIT DESCRIPTION 12.1 POWER SUPPLY: Socket PL2 is the 220VAC input. 2.5A fuse F1 is used to protect the device against short circuit. Line filters and capacitors L1, C1, L5 and L6 are used to block the parasitic coming from the mains. They also prevent the noise, produced in the circuit, from being injected to the line. Voltage is re