Hitachi-HTDK170E-mc-sm维修电路原理图.pdf

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1、CAUTION: Before servicing this chassis, it is important that the service technician read the “Safety Precautions” and “Product Safety Notices” in this service manual. ATTENTION: Avant deffectuer lentretien du chassis, le technicien doit lire les Prcautions de scurit et les Notices de scurit du produ

2、it prsents dans le prsent manuel. VORSICHT: Vor ffnen des Gehuses hat der Service-Ingenieur die Sicherheitshinweise“ und Hinweise zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen. SERVICE MANUAL MANUEL DENTRETIEN WARTUNGSHANDBUCH Data contained within this Service manual is subject to alte

3、ration for improvement. Les donnes fournies dans le prsent manuel dentretien peuvent faire lobjet de modifications en vue de perfectionner le produit. Die in diesem Wartungshandbuch enthaltenen Spezifikationen knnen sich zwecks Verbesserungen ndern. SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR

4、 IMPROVEMENT DVD DIGITAL THEATRE SYSTEM July 2003 No. 0153 HTDK170E HTDK170EUK RadioFans.CN 收音机爱 好者资料库 2 1. GENERAL DESCRIPTION 1.1 ES60X8 The ES6008/ES6018 Vibratto DVD processor is a single-chip MPEG video decoding chip that integrates audio/video stream data processing, TV encoder, four video DAC

5、s with Macrovision. copy protection, DVD system navigation, system control and housekeeping functions. The Vibratto DVD processor is built on the ESS proprietary dual CPU Programmable Multimedia Processor (PMP) core consists of 32-bit RISC and 64-bit DSP processors and offers the best DVD feature se

6、t. These features can be listed as follows: General Features: Single-chip DVD processor based on ESS proprietary dual CPU PMP core. Integrated NTSC/PAL encoder. Four integrated 10-bit video DACs. DVD-Video, VCD 1.1, 2.0, and SVCD Interface for ATAPI devices and A/V DVD loaders. Interface for Compact

7、 Flash, Memory Stick and SmartMedia cards. Direct interface of 8- or 16-bit SDRAM up to 128-Mb capacity. Direct interface for up to four banks of 8-/16-bit EPROM or Flash EPROM for up to 16-MB capacity. Video Related Features: Macrovision 7.1 for NTSC/PAL interlaced video. Simultaneous composite vid

8、eo and S-video outputs, or composite and YUV outputs, or composite and RGB outputs. 8-bit CCIR 601 YUV 4:2:2 output. On-Screen Display (OSD) controller with 3-bit blending provides display with 256 colors in 8 degrees of transparency. Subpicture Unit (SPU) decoder supports karaoke lyric, subtitles,

9、and EIA-608 compliant Line 21 Captioning. Audio Related Features: Dolby Digital (AC-3) and Dolby Pro Logic. RadioFans.CN 收音机爱 好者资料库 3 High-Definition Compatible Digital. (HDCD) decoding. Dolby Digital Class A and HDCD certified. CD-DA. MP3. 1.2 MEMORY 1.2.1 System SRAM Interface The system SRAM inte

10、rface controls access to optional external SRAM, which can be used for RISC code, stack, and data. The SRAM bus supports four independent address spaces, each having programmable bus width and wait states. The interface can support not only SRAM, ROM/EPROM and memory-mapped I/O ports for standalone

11、applications are also supported. 1.2.2DRAM Memory Interface The Vibratto provides a glueless 16-bit interface to DRAM memory devices used as video memory for a DVD player. The maximum amount of memory supported is 16 MB of Synchronous DRAM (SDRAM). The memory interface is configurable in depth to su

12、pport 128-Mb addressing. The memory interface controls access to both external SDRAM or EDO memories, which can be the sole unified external read/write memory acting as program and data memory as well as various decoding and display buffers. 1.3 DRIVE INTERFACES The Vibratto supports the AT Attachme

13、nt Packet Interface (ATAPI), Integrated Drive Electronics (IDE), and other parallel and serial port interfaces used by many types of DVD loaders. These interfaces meet the specifications of many DVD loader manufacturers. An ATAPI drive is connected via the standard 34 pin dual row PC style IDE heade

14、r 1.4 FRONT PANEL The front panel is based around an Futaba VFD and a common NEC front panel controller chip, (uPD16311). The ES6008/ES6018 controls the uPD16311 using several control signals, (clock, data, chip select). The infrared remote control signal is passed directly to the ES60X8 and 8051 fo

15、r decoding. 1.5 REAR PANEL Outputs and Inputs at the AV1000 rear panel: - Left, Right and Subwoofer (active) audio outputs. - Left, Right and CVBS input. - Composite, S-Video, and SCART outputs. - Input SCART - 5x15W 8ohms (L,R,SL,SR,C) + 1x25W 4ohms Subwoofer outputs. - AM / FM Tuner Antenna input

16、- 220-240 V 50Hz AC Power input The six-video signals used to provide CVBS, S-Video, and RGB are generated by the ES60X8s internal video DAC. The video signals are buffered by external circuitry. Six channel audio output by the ES6018 in the form of three I2S (or similar) data streams. The S/PDIF se

17、rial stream is also generated by the ES60X8 output by the rear panel. A six channel audio DAC (AK4356) are used for six channel audio output with ES6018, and similarly one AK4362A Audio DAC is used for two channel audio output with ES6008 or ES6018. 4 2. SYSTEM BLOCK DIAGRAM and ES6008/18 PIN DESCRI

18、PTION 2.1 ES6008/18 PIN DESCRIPTION 5 6 7 8 9 10 2.1 SYSTEM BLOCK DIAGRAM System block diagram is shown in the following figure: 3. AUDIO OUTPUT The ES6008 supports two-channel analog audio output while ES6018 supports six-channel analog audio output. In a system configuration with six analog output

19、s, the front left and right channels can be configured to provide the stereo (2 channel) outputs and Dolby Surround, or the left and right front channels for a 5.1 channel surround system. The ES6008 also provides digital output in S/PDIF format. The board supports both optical and coaxial S/PDIF ou

20、tputs. AV1000 Has also 5.1 channel Class-D amplifier outputs to 8 ohms satelites and 4 ohms subwoofer. 4 AUDIO DACS The ES6008/18 supports several variations of an I2S type bus, varying the order of the data bits (leading or no leading zero bit, left or right alignment within frame, and MSB or LSB f

21、irst) is possible using the ES6008/18 internal configuration registers. The I2S format uses four stereo data lines and three clock lines. The I2S data and clock lines can be connected directly to one or more audio DAC to generate analog audio output. The two-channel DAC is an AKM AK4382A. The DACs s

22、upport up to 192kHz sampling rate. The outputs of the DACs are differential, not single ended so a buffering circuit is required. The buffer circuits use National LM833 op-amps to perform the low-pass filtering and the buffering. 11 5 VIDEO INTERFACE 5.1 Video Display Output The video output section

23、 controls the transfer of video frames stored in memory to the internal TV encoder of the Vibratto. The output section consists of a programmable CRT controller capable of operating either in Master or Slave mode. The video output section features internal line buffers which allow the outgoing lumin

24、ance and chrominance data to match the internal clock rates with external pixel clock rates, easily facilitating YUV4: 2:2 to YUV4: 2:0 component and sample conversion. A polyphase filter achieves arbitrary horizontal decimation and interpolation. Video Bus The video bus has 8 YUV data pins that tra

25、nsfer luminance and chrominance (YUV) pixels in CCIR601 pixel format (4:2:2). In this format, there are half as many chrominance (U or V) pixels per line as luminance (Y) pixels; there are as many chrominance lines as luminance. Video Post-Processing The Vibratto video post-processing circuitry prov

26、ides support for the color conversion, scaling, and filtering functions through a combination of special hardware and software. Horizontal up- sampling and filtering is done with a programmable, 7-tap polyphase filter bank for accurate non-integer interpolations. Vertical scaling is achieved by repe

27、ating and dropping lines in accordance with the applicable scaling ratio. Video Timing The video bus can be clocked either by double pixel clock and clock qualifier or by a single pixel clock. The double clock typically is used for TV displays, the single for computer displays. Video Interface Regis

28、ters VID_SCN_HSTART The write-only Video Screen Horizontal Start Address register contains the 13-bit horizontal pixel starting address of the active video display. VID_SCN_HEND The write-only Video Screen Horizontal End Address register contains the 13-bit horizontal pixel ending address of the act

29、ive video display. VID_SCN_VSTART The write-only Video Screen Vertical Start Address register contains the 13-bit vertical scan line starting address of the active video display. VID_SCN_VEND The write-only Video Screen Vertical End Address register contains the 13-bit vertical scan line ending addr

30、ess of the active video display. VID_SCN_VERTIRQ The write-only Video Screen Vertical Line Interrupt register is selectable by software and contains the line in which a vertical interrupt will occur. Line 0 is the top of the screen, as defined by the leading edge of the VSYNC pin. Typically, an inte

31、rrupt is set either just before or just after the active video display. VID_SCN_HBLANK_START The write-only Video Screen Horizontal Blanking Interval Start Address register contains the 13- bit starting address of the horizontal blanking interval for the active video display. 12 VID_SCN_HBLANK_STOP

32、The write-only Video Screen Horizontal Blanking Interval End Address register contains the 13-bit ending address of the horizontal blanking stop interval for the active video display. VID_SCN_VBLANK_START The Video Screen Vertical Blanking Interval Start Address register contains the 13-bit starting

33、 address of the vertical blanking interval for the active video display. VID_SCN_VBLANK_STOP The write-only Video Screen Vertical Blanking Interval Stop Address register contains the 13-bit ending address of the vertical blanking stop interval for the active video display. VID_SCN_HSYNCWIDTH The wri

34、te-only Video Screen Horizontal Sync Width Pulse register contains the 13-bit value of the horizontal sync pulse width for the active video display. This register is needed only if sync direction is output VID_SCN_HSYNCPERIOD The write-only Video Screen Horizontal Sync Period register contains the 1

35、3-bit value for the period of the horizontal sync pulse used by the active video display. It is needed only if sync direction is output. VID_SCN_VSYNCPERIOD The write-only Video Screen Video Sync Period register contains the 13-bit value for the period of the vertical sync pulse used by the active v

36、ideo display. This register is needed only if sync direction is output. VID_SCN_VSYNCPIXEL The write-only Video Screen Vertical Sync Pixel register defines which pixel VSYNC will change on for the active video display. The number of pixels delayed from HSYNC that VSYNC will change on either the risi

37、ng or falling edge of VSYNC. This register is needed only if sync direction is output VID_SCN_VSYNCWIDTH The write-only Video Screen Vertical Sync Pulse Width register defines the width of the 6-bit vertical sync pulse. It is needed only if sync direction is output VID_SCN_VERTCOUNT The read-only Vi

38、deo Screen Verital Counter register contains the current line of the vertical counter, and starts its counting at VSYNC line 0. This register is typically used for testing only. VID_SCN_HORIZCOUNT The read-only Video Screen Horizontal Counter register contains the current pixel of the horizontal cou

39、nter, and starts its counting at HSYNC pixel 0. This register is typically used for testing only. VID_SCN_COUNTER_CTL The write-only Video Screen Counter Control register contains counter control bits for the inverted blank sync, inverted horizontal sync, and inverted vertical sync functions. This r

40、egister initializes to 0 x00 after reset. VID_SCN_OUTPUTCNTL The Video Screen Output Control register contains the control logic used to control the clamping and filtering characteristics of the signal being output to the video display. 13 VID_SCN_ITERFACECNTL The Video Screen Interface Control regi

41、ster contains the control logic used to determine the signal output characteristics to the video display. VID_SCN_RESETS The Video Screen Reset register contains the control logic for reset events, including the reset pan and scan, horizontal filtering and DMA enabling functions. This register is se

42、t to 1 on reset. VID_SCN_STATUS The Video Screen Status register contains the status bits for the video section. VID_SCN_OSD_HSTART The OSD Video Screen Horizontal Start Address register contains the horizontal starting address value for the OSD, as referenced from the active display window. VID_SCN

43、_OSD_HEND The OSD Video Screen Horizontal End Address register contains the 13-bit horizontal ending address value for the OSD, as referenced from the active video display. VID_SCN_OSD_VSTART The OSD Video Screen Vertical Start Address register contains the 13-bit vertical starting address value for

44、 the OSD, as referenced from the active video display. VID_SCN_OSD_VEND The OSD Video Screen Vertical End Address register contains the 13-bit vertical ending address value for the OSD, as referenced from the active video display. VID_SCN_OSD_MISC The OSD Video Screen Miscellaneous register contains

45、 the control logic and status bits for the OSD controller. VID_SCN_OSD_PALETTE These 16 registers contain the OSD palette. 6 SDRAM MEMORY The memory bus interface generates all the control signals to interface with external memory. The Vibratto supports different configurations using the memory conf

46、iguration bits SDCFG1:0 (bits 12:11), the SD8BIT bit (bit 14), and SD64M bit (bit 15) in the BUSCON_DRAM_CONTROL register. Configurations can be implemented in many ways. The following table lists the typical SDRAM configurations used by the Vibratto. 14 Typical SDRAM Configurations: The memory inte

47、rface controls access to both external SDRAM or EDO memories, which can be the sole unified external read/write memory acting as program and data memory as well as various decoding and display buffers. At high clock speeds, the Vibratto memory bus interface has sufficient bandwidth to support the de

48、coding and displaying of CCIR601 resolution images at full frame rate. 7 FLASH MEMORY The decoder board supports AMD class Flash memories. Currently 4 configurations are supported: FLASH_512K_8b FLASH_1024K_8b FLASH_512Kx2_8b FLASH_512Kx2_16b The Vibratto permits both 8- and 16-bit common memory I/O

49、 accesses with a removable storage card via the host interface. 8 SERIAL EEPROM MEMORY An I2C serial EEPROM is used to store user configuration (i.e. language preferences, speaker setup, etc.) and software configuration. Industry standard EEPROM range in size from 1kbit to 256kbit and share the same IC footprint and pinout. The default device is 2kbit, 256kx 8, SOIC8 SGS Thomson ST24C02M1 or equivalent. 15 9 ATA/IDE LOADER INTERFACE The host interface can directly support ATAPI devices such a