Onkyo-DT9904S-cd-sm维修电路原理图.pdf

《Onkyo-DT9904S-cd-sm维修电路原理图.pdf》由会员分享，可在线阅读，更多相关《Onkyo-DT9904S-cd-sm维修电路原理图.pdf（71页珍藏版）》请在收音机爱好者资料库上搜索。

1、SERVICE MANUAL DT9904S RadioFans.CN 收音机爱 好者资料库 CONTENTS 1. SAFETY PRECAUTIONS1 2. PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO ELECTROSTATICALLY SENSITIVE(ES)DEVICES1 4. PREVERTION OF STATIC ELECTRICITY DISCHARGE3 5. ASSEMBLING AND DISASSEMBLING THE MECHANISM UNIT4 5.1 OPTICAL PICKUP UNIT EXPLOSED

2、VIEW AND PART LIST 4 5.2 BRACKET EXPLOSED VIEW AND PART LIST 6 6. ELECTRICAL CONFIRMATION8 6.1 VIDEO OUTPUT (LUMINANCE SIGNAL) CONFIRMATION8 6.2 VIDEO OUTPUT(CHROMINANCE SIGNAL) CONFIRMATION9 7. MPEG BOARD CHECK WAVEFORM10 8. AM29LV160D11 9. SCHEMATIC 2, 3 Clocks 8.1 HY57V641620HG 16 HY57V641620HG P

3、IN CONFIGURATION PIN DESCRIPTION PINPIN NAMEDESCRIPTION CLKClock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK CKEClock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self r

4、efresh CSChip SelectEnables or disables all inputs except CLK, CKE and DQM BA0,BA1 Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 A11Address Row Address : RA0 RA11, Column Address : CA0 CA7 Auto-precharge flag : A10 RAS, CAS, WE R

5、ow Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the operation Refer function truth table for details LDQM, UDQMData Input/Output MaskControls output buffers in read mode and masks input data in write mode DQ0 DQ15Data Input/OutputMultiplexed data input / output pin VDD/

6、VSSPower Supply/GroundPower supply for internal circuits and input buffers VDDQ/VSSQData Output Power/GroundPower supply for output buffers NCNo ConnectionNo connection VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS 1 2 3 4 5 6 7 8 9 10

7、 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 54pin TSOP II 400mil x 875mil 0.8mm pin pitch 17 HY57

8、V641620HG FUNCTIONAL BLOCK DIAGRAM 1Mbit x 4banks x 16 I/O Synchronous DRAM X decoders State Machine A0 A1 A11 BA0 BA1 Address buffers Address Registers Mode Registers Row Pre Decoders Column Pre Decoders Column Add Counter Row active Column Active Burst Counter Data Out Control CAS Latency Internal

9、 Row counter DQ0 DQ1 DQ14 DQ15 refresh Self refresh logic for VDD-VEElevel differences above 13V, a VDD-VSS of at least 4.5V is required). For example, if VDD = +4.5V, VSS = 0V, and VEE= -13.5V, analog signals from -13.5V to +4.5V can be controlled by digital inputs of 0V to 5V. These multiplexer ci

10、rcuits dissipate extremely low quiescent power over the full VDD-VSS and VDD-VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic “1” is present at the inhibit input terminal, all channels are off. The CD4051B is a single 8-Channel multiplexer having three b

11、inary control inputs, A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to the output. The CD4052B is a differential 4-Channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary

12、 input signals select 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs. The CD4053B is a triple 2-Channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are c

13、onnected in a single-pole, double-throw confi guration. When these devices are used as demultiplexers, the “CHANNEL IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs. Features Wide Range of Digital and Analog Signal Levels - Digital . . . . . . . . . . . . . . . . .

14、. . . . . . . . . . . . . 3V to 20V - Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20VP-P Low ON Resistance, 125 (Typ) Over 15VP-PSignal Input Range for VDD-VEE = 18V High OFF Resistance, Channel Leakage of 100pA (Typ) at VDD-VEE = 18V Logic-Level Conversion for Digital Addres

15、sing Signals of 3V to 20V (VDD-VSS = 3V to 20V) to Switch Analog Signals to 20VP-P (VDD-VEE = 20V) Matched Switch Characteristics, rON = 5 (Typ) for VDD-VEE = 15V Very Low Quiescent Power Dissipation Under All Digital- Control Input and Supply Conditions, 0.2W (Typ) at VDD-VSS = VDD-VEE = 10V Binary

16、 Address Decoding on Chip 5V, 10V and 15V Parametric Ratings 10% Tested for Quiescent Current at 20V Maximum Input Current of 1A at 18V Over Full Package Temperature Range, 100nA at 18V and 25oC Break-Before-Make Switching Eliminates Channel Overlap Applications Analog and Digital Multiplexing and D

17、emultiplexing A/D and D/A Conversion Signal Gating Ordering Information PART NUMBER TEMP.RANGE (oC)PACKAGE CD4051BF, CD4052BF, CD4053BF -55 to 12516 Ld CERAMIC DIP CD4051BE, CD4052BE, CD4053BE -55 to 12516 Ld PDIP CD4051BM, CD4051BNS-55 to 12516 Ld SOIC CD4051BPW, CD4052BPW, CD4053BPW -55 to 12516 L

18、d TSSOP August 1998 - Revised March 2000 /Title (CD405 1B, CD4052 B, CD4053 B) /Sub- ject (CMOS Analog Multi- plex- ers/Dem ultiplex- ers with Logic Level Conver- sion) /Author () /Key- words (Harris Semi- conduc- tor, CD4000 8.3 CD4052B 22 Pinouts CD4051B (PDIP, CDIP, SOIC, TSSOP) TOP VIEW CD4052B

19、(PDIP, CDIP, TSSOP) TOP VIEW CD4053B (PDIP, CDIP, TSSOP) TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 4 6 COM OUT/IN 7 5 INH VSS VEE VDD 1 0 3 A B C 2 CHANNELS IN/OUT CHANNELS IN/OUT CHANNELS IN/OUT 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 0 2 COMMON “Y” OUT/IN 3 1 INH VSS VEE VDD 1 COMMON “X” OUT/

20、IN 0 3 A B 2 Y CHANNELS IN/OUT Y CHANNELS IN/OUT X CHANNELS IN/OUT X CHANNELS IN/OUT 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 by bx cy OUT/IN CX OR CY IN/OUT CX INH VSS VEE VDD OUT/IN ax OR ay ay ax A B C OUT/IN bx OR by IN/OUT IN/OUT Functional Block Diagrams CD4051B 11 10 9 6 A B C INH 134251121514

21、TG TG TG TG TG TG TG TG 3 COMMON OUT/IN 01234567 BINARY TO 1 OF 8 DECODER WITH INHIBIT LOGIC LEVEL CONVERSION 87VSSVEE 16 V DD CHANNEL IN/OUT All inputs are protected by standard CMOS protection network. CD4051B, CD4052B, CD4053B 23 CD4052B CD4053B Functional Block Diagrams (Continued) 12111514 0123

22、 3210 X CHANNELS IN/OUT Y CHANNELS IN/OUT BINARY TO 1 OF 4 DECODER WITH INHIBIT 13 3 COMMON Y OUT/IN COMMON X OUT/IN 78 16 6 9 10 A B INH VSSVEE VDD TG TG TG TG TG TG TG TG 4251 LOGIC LEVEL CONVERSION 11 10 9 6 A B C INH 12351213 TG TG TG TG TG TG 4 COMMON OUT/IN axaybxbycxcy 8 7VSSVEE 16 V DD IN/OU

23、T 15 14 BINARY TO 1 OF 2 DECODERS WITH INHIBIT LOGIC LEVEL CONVERSION VDD All inputs are protected by standard CMOS protection network. COMMON OUT/IN COMMON OUT/IN ax OR ay bx OR by cx OR cy CD4051B, CD4052B, CD4053B 24 TRUTH TABLES INPUT STATES “ON” CHANNEL(S)INHIBITCBA CD4051B 00000 00011 00102 00

24、113 01004 01015 01106 01117 1XXXNone CD4052B INHIBITBA 0000 x, 0y 0011x, 1y 0102x, 2y 0113x, 3y 1XXNone CD4053B INHIBITA OR B OR C 00ax or bx or cx 01ay or by or cy 1XNone X = Dont Care CD4051B, CD4052B, CD4053B 25 123 1234 56 A B C D E A B C D E F 1 2 3 U403 HS0038A2 K403 K401 K402 D401 1N4148 KEY3

25、 KEY2 KEY1 S9 C403 104 R415 100 IR VCC TC402 100uF/16V C402 104 C401 104 LEDST LEDCK LEDAT VCC R401 51K R404 10K R402 10K R403 10K IR OSC 1 DOUT 2 DIN 3 CLK 4 STB 5 K1 6 K2 7 K3 8 VDD 9 NC 13 SEG1/KS1 10 SEG2/KS2 11 SEG3/KS3 12 SEG4/KS4 14 SEG5/KS5 15 GR6 23 SEG6/KS6 16 SEG7/KS7 17 SEG8/KS8 18 SEG9/

26、KS9 19 SEG10/KS10 20 SEG11 21 SEG12/GR7 22 VDD 25 GND 26 GR5 24 GR4 27 GR3 28 GND 29 GR2 30 GR1 31 GND 32 U401 PT6961 LEDAT LEDCK LEDST KEY1 KEY2 KEY3 S1 S2 S3 S4 S5S6 S7 S8 G1 G2 G3 G4 G5 G6 G7 VCC VCC VCC TC401 100uF/16VS9 G1 1 G2 2 G3 3 G4 4 G5 5 G6 6 G7 7 S1 8 S2 9 S3 10 S4 11 S5 12 S6 13 S7 14

27、S8 15 S9 16 LED401 ZDC6-2102YGB-A G1 G2 G3 G4 G5 G6 G7 S1 S2 S3 S4 S5 S6 S7 S8 S9 2 3 4 1 5 6 XS401 XS6 Q402 8050 R405 10K R406 470R VCC 12 LED402 R407 0R LEDB LEDB LEDA 12 LED403 R419 270R 12 LED404 VCC R420 1K LEDAQ401 8050 12 R421 330R 12 R422 330R FRONT SCHEMATIC DIAGRAM 26 9. SCHEMATIC & PCB WI

28、RING DIAGRAM FRONT SCHEMATIC DIAGRAM 27 123 1234 56 A B C D E A B C D E F U503 LM431A C515 104 L505 10uH/1A C506 223 L507 10uH/2A L506 10uH/2A R K A ! ! ! R510 4.7K R509 10K R508 3.3K R506 330 R505 33ohm R502 120K/2W R503 39K/2W U502 2501 TC502 47UF/50 TC501 47uF/400V D505 HER107 C502 103/1KV C503 1

29、01/1KV L503 FB BC503 400V 221 C505 101 C513 101 C509 101 C514 101 C511 101 +9V C504 104 TC504 470uF/16V TC511 100uF/16V TC512 47uF/50V TC506 1000uF/10V TC505 1000uF/10V TC509 1000uF/10V TC510 1000uF/10V D508 HER105 C507 101 TC503 470uF/16V R511 220R/1W FB 4 GND 1 D 2 VCC 3 U501 5L0380R R507 1K R504

30、1M IN 1 GND 2 OUT 3 U504 LM7805 TC508 100uF/16V SA+5V D510 HER303 ZD501 5.1V D506 HER105 D509 SR303 D511 HER105 D512 HER105 +3.3V 2 3 4 6 7 10 11 9 12 13 14 15 16T501 EI28/8 TC513 100uF/16V D502 1N4007 D503 1N4007 D501 1N4007 D504 1N4007 C508 104 C510 104 -9V +5V ZD502 9.1V/1W R512 10R/2W AGND OK -2

31、1V 2 3 4 1 5 6 8 9 10 7 11 12 13 CN501 XS13 2.0MM FL+ FL- -9V +9V DET GND SA+5V GND -9V GND +3.3V +5V GND +9V SA+5V GND 2 3 4 1 5 6 8 9 10 7 11 12 13 CN502 XS13 2.5MM DET OK AGND OPEN OPEN OPEN BC501 275V 104 L502 F501 T1.6A/250V ! ! R501680K2W ! ! ! BCN501 220V IN BCN502 SW-SPST L501 BC502 275V 104

32、 SA+5V POWER BOARD SCHEMATIC DIAGRAM 28 POWER BOARD SCHEMATIC DIAGRAM 29 123 1234 56 A B C D E A B C D E F R620 10K R611 1K C604 103 R604 560R R606 10K R610 22K C606 100p R608 1K R602 22K TC606 22uF/16V TC604 4.7uF/16V TC602 4.7u R621 10ohm1/6W TC615 47uF/16V C601 104 R622 10ohm1/6W TC616 47uF/16V C

33、602 104 +9V+9VA-9V-9VA 5 4 3 2 1 6 7 8 9 MIC601 L601 TC611 47uF/16V R615 100K R616 330 R619 1K VD601 1N4148 VD602 1N4148 VD603 1N4158 DET R618 10K +5V C608 102 R617 100K FROM MPEG BOARD C609 104 TC621 100uF/16V C613 104 R6313.9K R627 3.9K TC618 47uF/16V TC619 100uF/16V C614 104 R630 3.9K R632 3.9K T

34、C617 47uF/16V TL +5V R636 4.7R R635 4.7R AGND C612 104 OUT1 1 IN1- 2 IN1+ 3 GND 4 VDD 8 OUT2 7 IN2- 6 IN2+ 5 U602 TDA1308 R628 3.3K R629 3.9K AGND R634 10K R633 10K C611 104(DNS) C610104(DNS) TC620 100uF/16V(DNS) AGND TR C616 104 C615 104 R623 20K R624 30K R625 20K R626 30K R6371KR6381K JK603 HP R63

35、9100KR640100K +9VA -9VA 1 2 3 4 5 6 7 8 XS602 XS08 * TR TL AGND MUTE-2 -9V +9V AGND +5V 1 2 3 XS601 XS03 * OK DET AGND TO POWER AND AV BOARD OK 3 2 1 84 U601A 4558 5 6 7 U601B 4558 MUTE-2 +5V +5V Q601 8050 +9V OK SCHEMATIC DIAGRAM 30 OK SCHEMATIC DIAGRAM 31 123 1234 56 A B C D E A B C D E F CC AGND

36、LFE SL SR L R RED WHITE 12 L701 FB 12 L702 FB 12 L703 FB 12 L704 FB 12 L705 FB 12 L706 FB 12 C701 102 12 C702 102 12 C703 102 12 C704 102 12 C705 102 12 C706 102 1 2 3 4 5 6 7 8 9 10 11 12 JK701 AV8 A(B)OUT 1 A(A)OUT 3 RETURN 5 BLUE I/O 7 RETURN 9 GREEN I/O 11 RETURN 13 RED I/O 15 RETURN 17 V-OUT 19

37、 GND 21 A(B)IN 2 A-COM 4 A(A)IN 6 FUNC SW 8 CONT 10 NC 12 RETURN 14 BLK I/O 16 TRTURN 18 V-IN 20 JK706 VJS3921 12 R704 4.7K 12 R705 75R B CE V701 8050 B CE V702 8050 12 R708 33R 12 R709 330R 12 R710 2.2K +10VA+10V AGND PDAT0 B CE V703 8050 12 R711 1K 12 R712 2.2K A+10V PDAT2 12 C716 104 AGND VCC AGN

38、D 12 R707 A+10V AGND AGND VCC VGNDVGND Pr 12 L709 FBSMT 12 L708 FBSMT 12 L707 FBSMT Y1 Pb VGND GREEN BLUE RED B G R 1 2 3 4 5 6 JK702 RCA-407 BLACK 12 TC7021000uF/10V 12TC703220uF/16V 12TC704220uF/16V 12 L710 FBSMT SPDIF12 R701 220R 12C710 104 12 L713FCM 12 L714FCM 12 C707 105 VGND 12 R713 0R AGNDVG

39、ND 12 R703 68R VIN 1 VCC 2 GND 3 JK705 OPTICAL VCC VGND 12 C711 104 SPDIF 12 L712 0R 12 L711 0R 12 R706 2.2R 12 TC701220uF 12 R702100R VIEDO 12 TC705220uF/16V 12TC706220uF/16V Y C VGND VGND 12 L716FBSMT 12 L715FBSMT 12 C712 20P VGND 12 C713 20P 12C723105 12C722 105 12C720 105 12 C721105 12 C724 105

40、12 C719 105 AGND VGND LFE CC SR SL R L VIEDO Pb Y1 Pr PDAT1 PDAT2 VCC SPDIF Y C PDAT0 +10V 2 3 4 1 5 6 8 9 10 7 11 12 14 15 16 13 17 18 20 21 22 19 23 24 25 26 28 27 29 30 XS701 XS30 TR TL 12 R714 1K 12 R715 1K B CE V704 8050 B CE V705 8050 AGND AGND TL TR MUTE-2 1 1 2 3 1 4 XS702 XS04 * MUTE-2 AGND

41、 TL TR 12 R718 1K 12 R717 1K 12 R716 0R AGND MUTE-2 125220uF/16V 121 220uF/16V 124220uF/16V 122220uF/16V 123220uF/16V 5 7 6 JK703A V-OUT5 43 2 1 JK703B S-VIDEO 12 C717 104 12 C718 104 AGND OUTPUT BOARD SCHEMATIC DIAGRAM 32 OUTPUT BOARD SCHEMATIC DIAGRAM 33 123 1234 56 A B C D E F A B C D E F DVDA 2

42、CEQP 250 DVDB 3 DVDC 4 DVDD 5 AGND 1 OSP 252 OSN 253 DVDRFIP 6 DVDRFIN 7 MA 8 MB 9 MC 10 MD 11 SA 12 SB 13 SC 14 SD 15 CDFON 16 CDFOP 17 TNI 18 TPI 19 MDI1 20 MDI2 21 LDO2 22 LDO1 23 AVDD3 256 V2REFO 28 SGND 27 VREFO 30 V20 29 TEO 32 FEO 31 USB_VSS 43 RFLVL/RFON 26 CSO/RFOP 25 TEZISLV 33 OP_OUT 34 O

43、P_INN 35 OP_INP 36 FOO 42 TRO 41 USBM 45 TROPENPWM 39 PWMOUT1/V_ADIN9 40 USB_VDD3 46 FMO 38 DMO 37 HIGHA0 59 HIGHA1 75 HIGHA2 74 HIGHA3 72 HIGHA4 71 HIGHA5 70 HIGHA6 69 HIGHA7 68 DVDD18 52 AD7 91 DVSS 62 APLLCAP 63 AD5 87 AD4 86 APLLVSS 64 APLLVDD3 65 AD3 84 AD2 83 AD1 82 AD0 81 DVDD3 73 IOA0 93 IOA

44、2 53 IOA3 54 IOA4 55 IOA5 56 DVDD3 80 IOA6 57 IOA7 58 A16 67 A17 92 DVSS 85 IOA18 60 IOA19 61 IOA20 76 IOA1 78 ALE 90 IOOE 79 IOWR 66 IOCS 77 DVSS 94 UWR 95 URD 96 DVDD18 97 UP1_2 98 UP1_3 99 UP1_4 100 UP1_5 101 UP1_6 102 UP1_7 103 UP3_0 104 UP3_1 105 DVSS 116 UP3_4 106 UP3_5 107 RFVDD3 244 RFRPDC 2

45、45 DVDD3 108 ICE 109 PRST 110 IR 111 INT0 112 DVDD18 122 DQM0 113 DQS0 114 RD7 115 RD6 117 RD5 118 RD4 120 DVSS 119 RD3 121 RD2 123 RD1 124 RD0 125 RD15 126 RD14 128 DVDD3 127 RD13 129 YUV0/CIN 192 FS 191 VREF 190 DACVDDC 189 RD16 188 RD17 187 RD18 186 RD19 185 RD20 184 RD21 183 DVDD3 182 RD22 181 R

46、D23 180 DQM2 179 DQM3 178 RD24 177 RD25 176 DVSS 175 RD26 174 DVDD18 173 RD27 172 RD28 171 RD29 170 RD30 169 DVDD3 167 RD31/ASDATA5 168 RA4 166 RA5 165 RA6 164 DVSS 163 RA7 162 DVSS 161 RA8 160 RA9 159 RA11 158 RCLK 156 CKE 157 DVDD3 155 RCLKB 154 RVREF/V_ADIN3 153 DVDD18 152 RA3 151 RA2 150 DVSS 14

47、8 RA1 149 RA0 147 RA10 146 BA1 145 DVSS 144 BA0 143 DVDD3 141 RCS 142 RAS 140 CAS 139 RWE 138 DQM1 137 DQS1 136 DVSS 134 RD8 135 RD9 133 RD10 132 RD11 131 DR12 130 RFGND 249 IREF 255 SVDD3 24 RFGC 254 JITFN 231 JITFO 230 LPFOP 238 LPFIN 237 CRTPLP 248 HRFZC 247 LPFIP 236 CEQN 251 RFRPAC 246 S_VREFN

48、243 ADCVSS 241 S_VREFP 242 S_VCM 240 ADCVDD3 239 PLLVDD3 234 LPFON 235 PLLVSS 232 MC_DATA 224 SPDIF 225 ASDATA4 222 DVDD18 221 ASDATA3 220 ASDATA2 219 RFGND18 226 ASDATA1 218 ASDATA0 217 ACLK 215 ALRCK 213 ABCK 214 DVDD3 204 SPBCK/ASDATA5 211 SPLRCK 210 SPDATA 209 SPMCLK 208 DVDD3 212 HSYNC/V_ADIN2

49、207 YUV7/ASDATA5 206 VSYNC/V_ADIN1 205 YUV6/R 203 YUV5/B 202 DACVSSA 201 YUV4/G 200 DACVDDA 199 YUV3/CVBS 198 DACVSSB 197 YUV2/C 196 DACVDDB 195 YUV1/Y 194 DACVSSC 193 IDACEXLP 233 USBP 44 FG/V_ADIN8 47 TDI/V_ADIN4 48 TMS/V_ADIN5 49 TCK/V_ADIN6 50 TDO/V_ADIN7 51 AD6 88 IOA21/V_ADIN0 89 DVSS 216 DVSS 223 XTALO 228 XTALI 229 RFVDD18 227 U201 MT1389 C2011uF C2021uF C2031uF C2041uF C205DNSC206 120p C