HarmanKardon-AVR354-avr-sm3维修电路原理图.pdf

《HarmanKardon-AVR354-avr-sm3维修电路原理图.pdf》由会员分享，可在线阅读，更多相关《HarmanKardon-AVR354-avr-sm3维修电路原理图.pdf（79页珍藏版）》请在收音机爱好者资料库上搜索。

1、MK2302S-01MDS 2302S-01 BIntegrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 Multiplier and Zero Delay BufferDescriptionThe MK2302S-01is a high performance Zero Delay Buffer (ZDB) which integrates ICS proprietary analog/digital Phase Locked Loop (PLL) techniques. T

2、he chip is part of ICS ClockBlocksTM family and was designed as a performance upgrade to meet todays higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay

3、 through the device. There are two outputs on the chip, one being a low-skew divide by two of the other output. The MK2302S-01 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. By allowing off-chip feedback paths, the

4、device can eliminate the delay through other devices.Features8 pin SOIC packageLow input to output skew of 250ps max Absolute jitter 500psPropagation Delay 350psAbility to choose between different multipliers from 0.5X to 16XOutput clock frequency up to 133 MHz at 3.3VCan recover degraded input cloc

5、k duty cycleOutput clock duty cycle of 45/55Full CMOS clock swings with 25mA drive capability at TTL levelsAdvanced, low power CMOS processOperating voltage of 3.3V or 5VIndustrial temperature version availableBlock DiagramPhaseDetector,ChargePump,and LoopFilterdivideby NCLK1External feedback can co

6、me from CLK1 or CLK2 (see table on page 2)ICLKFBINS1:0VCOCLK2/2130AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 Multiplier and Zero Delay BufferMDS 2302S-01 BIntegrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 MK2302S-01Pin AssignmentClock Multiplier D

7、ecoding Table 1(Multiplies Input clock by shown amount)Pin DescriptionsFBINICLKGNDVDDS0CLK1CLK212348765GNDS1123487658 pin (150 mil) SOICFBINS1S0CLK1CLK2CLK1002 X ICLKICLKCLK1014 X ICLK2 X ICLKCLK110ICLKICLK/2CLK1118 X ICLK4 X ICLKCLK2004 X ICLK2 X ICLKCLK2018 X ICLK4 X ICLKCLK2102 X ICLKICLKCLK21116

8、 X ICLK8 XICLKPinNumberPinNamePin TypePin Description1FBINInputFeedback clock input.2ICLKInputReference clock input.3GNDPowerConnect to ground.4S0InputSelect 0 for output clock per decoding table above. Pull-up.5S1InputSelect 1 for output clock per decoding table above. Pull up.6CLK1OutputClock outp

9、ut per table above.7VDDPowerConnect to +3.3V or +5.0V.8CLK2OutputClock output per table above. Low skew divide by two of pin 6 clock.131AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs ADV7342/ADV7343 Rev. 0 Information furnished by Analog

10、 Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implica

11、tion or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 Fax: 781.461.3113 2006 Analog Devices, Inc. All rights reserved.

12、 FEATURES 74.25 MHz 20-/30-bit high definition input support Compliant with SMPTE 274M (1080i), 296M (720p), and 240M (1035i) 6, 11-bit, 297 MHz video DACs 16 (216 MHz) DAC oversampling for SD 8 (216 MHz) DAC oversampling for ED 4 (297 MHz) DAC oversampling for HD 37 mA maximum DAC output current NT

13、SC M, PAL B/D/G/H/I/M/N, PAL 60 support NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz) Multiformat video input support 4:2:2 YCrCb (SD, ED, and HD) 4:4:4 YCrCb (ED and HD) 4:4:4 RGB (SD, ED, and HD) Multiformat video output support Composite (CVBS) and S-Video (Y/C) Component YPrPb (SD, ED

14、, and HD) Component RGB (SD, ED, and HD) Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant Simultaneous SD and ED/HD operation EIA/CEA-861B compliance support Programmable features Luma and chroma filter responses Vertical blanking interval (VBI) Subcarrier frequency (FSC) and phase Luma delay

15、Copy generation management system (CGMS) Closed captioning and wide screen signaling (WSS) Integrated subcarrier locking to external video source Complete on-chip video timing generator On-chip test pattern generation On-board voltage reference (optional external input) Serial MPU interface with dua

16、l I2C and SPI compatibility 3.3 V analog operation 1.8 V digital operation 3.3 V I/O operation Temperature range: 40C to +85C APPLICATIONS DVD recorders and players High definition Blu-ray DVD players HD-DVD players FUNCTIONAL BLOCK DIAGRAM RGND_IOVDD_IO10-BITSDVIDEODATA20-BITED/HDVIDEODATAS_HSYNCP_

17、HSYNC P_VSYNC P_BLANKS_VSYNC11-BITDAC 1DAC 111-BITDAC 2DAC 211-BITDAC 3DAC 311-BITDAC 4DAC 411-BITDAC 5DAC 511-BITDAC 6DAC 6MULTIPLEXERREFERENCEAND CABLEDETECT16x/4x OVERSAMPLINGDAC PLLVIDEO TIMING GENERATORPOWERMANAGEMENTCONTROLCLKIN (2) PVDDPGND EXT_LF (2) VREFCOMP (2)RSET (2)ED/HD INPUTDEINTERLEA

18、VEPROGRAMMABLEHDTV FILTERSSHARPNESS ANDADAPTIVE FILTERCONTROLYCbCrHDTVTESTPATTERNGENERATORYCbCrTORGB MATRIXG/BRGBASYNCBYPASSRGBDGND (2)VDD (2)SCL/MOSISDA/SCLKALSB/SPI_SSSFL/MISOMPU PORTSUBCARRIER FREQUENCYLOCK (SFL)YUVTOYCrCb/RGBPROGRAMMABLECHROMINANCEFILTERADDBURSTRGB/YCrCbTOYUVMATRIX4:2:2 TO 4:4:4

19、HD DDRDEINTERLEAVESIN/COS DDSBLOCK16FILTER16FILTER4FILTERAGNDVAAADDSYNCVBI DATA SERVICEINSERTIONPROGRAMMABLELUMINANCEFILTER06399-001ADV7342/ADV7343 Figure 1. Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights. Protected by U.S. Patent Numbers 4,631,603, 4

20、,577,216, 4,819,098 and other intellectual property rights. 132AVR354 harman/kardonharman/kardon ADV7342/ADV7343 Rev. 0 | Page 18 of 88 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64GND_IO63CLKIN_B62S761S660S559S458S357DGND56VDD55S254S153S052TEST551TEST450S_HSYNC49S_VSYNC47RSET146VREF45COMP142DAC 34

21、3DAC 244DAC 148SFL/MISO41VAA40AGND39DAC 437DAC 636RSET235COMP234PVDD33EXT_LF138DAC 52TEST03TEST14Y07Y36Y25Y11VDD_IO8Y49Y510VDD12Y613Y714TEST215TEST316C011DGND17C118C219ALSB/SPI_SS20SDA/SCLK21SCL/MOSI2223P_HSYNC24P_VSYNC25P_BLANK26C4C327C528C629C730CLKIN_A3132PGNDPIN 1ADV7342/ADV7343TOP VIEW(Not to S

22、cale)EXT_LF206399-021 Figure 21. Pin Configuration Table 13. Pin Function Descriptions Pin No. Mnemonic Input/ Output Description 13, 12, 9 to 4 Y7 to Y0 I 8-Bit Pixel Port. Y0 is the LSB. Refer to Table 31 for input modes. 29 to 25, 18 to 16 C7 to C0 I 8-Bit Pixel Port. C0 is the LSB. Refer to Tabl

23、e 31 for input modes. 62 to 58, 55 to 53 S7 to S0 I 8-Bit Pixel Port. S0 is the LSB. Refer to Table 31 for input modes. 52, 51, 15, 14, 3, 2 TEST5 to TEST0 I Unused. These pins should be connected to DGND. 30 CLKIN_A I Pixel Clock Input for HD Only (74.25 MHz), ED1 Only (27 MHz or 54 MHz) or SD Only

24、 (27 MHz). 63 CLKIN_B I Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a 74.25 MHz reference clock for HD operation. 50 S_HSYNC I/O SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD horizontal synchronizatio

25、n signal. See the External Horizontal and Vertical Synchronization Control section. 49 S_VSYNC I/O SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control section.

26、 22 P_HSYNC I ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical Synchronization Control section. 23 P_VSYNC I ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization Control section. 24 P_BLANK I ED/HD Blanking Signal. See the E

27、xternal Horizontal and Vertical Synchronization Control section. 48 SFL/MISO I/O Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data Output. The SFL input is used to drive the color subcarrier DDS system, timing reset, or subcarrier reset. 47 RSET1 I This pin is used to control the a

28、mplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive operation (for example, into a 37.5 load), a 510 resistor must be connected from RSET1 to AGND. For low drive operation (for example, into a 300 load), a 4.12 k resistor must be connected from RSET1 to AGND. 133AVR354 harman/kardonharm

29、an/kardon ADV7342/ADV7343 Rev. 0 | Page 19 of 88 Pin No. Mnemonic Input/ Output Description 36 RSET2 I This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 k resistor must be connected from RSET2 to AGND. 45, 35 COMP1, COMP2 O Compensation Pins. Connect a 2.2 nF

30、capacitor from both COMP pins to VAA. 44, 43, 42 DAC 1, DAC 2, DAC 3 O DAC Outputs. Full and low drive capable DACs. 39, 38, 37 DAC 4, DAC 5, DAC 6 O DAC Outputs. Low drive only capable DACs. 21 SCL/MOSI I Multifunctional Pin: I2C Clock Input/SPI Data Input. 20 SDA/SCLK I/O Multifunctional Pin: I2C

31、Data Input/Output. Also, SPI clock input. 19 ALSB/SPI_SS I Multifunctional Pin: This signal sets up the LSB2 of the MPU I2C address. Also, SPI slave select. 46 VREF Optional External Voltage Reference Input for DACs or Voltage Reference Output. 41 VAA P Analog Power Supply (3.3 V). 10, 56 VDD P Digi

32、tal Power Supply (1.8 V). For dual-supply configurations, VDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering. 1 VDD_IO P Input/Output Digital Power Supply (3.3 V). 34 PVDD P PLL Power Supply (1.8 V). For dual-supply configurations, PVDD can be connected to othe

33、r 1.8 V supplies through a ferrite bead or suitable filtering. 33 EXT_LF1 I External Loop Filter for On-Chip PLL 1. 31 EXT_LF2 I External Loop Filter for On-Chip PLL 2. 32 PGND G PLL Ground Pin. 40 AGND G Analog Ground Pin. 11, 57 DGND G Digital Ground Pin. 64 GND_IO G Input/Output Supply Ground Pin

34、. 1 ED = enhanced definition = 525p and 625p. 2 LSB = least significant bit. In the ADV7342, setting the LSB to 0 sets the I2C address to 0 xD4. Setting it to 1 sets the I2C address to 0 xD6. In the ADV7343, setting the LSB to 0 sets the I2C address to 0 x54. Setting it to 1 sets the I2C address to

35、0 x56. 134AVR354 harman/kardonharman/kardon 135AVR354 harman/kardonharman/kardon IC51 XM IC136AVR354 harman/kardonharman/kardon 137AVR354 harman/kardonharman/kardon 138AVR354 harman/kardonharman/kardon 139AVR354 harman/kardonharman/kardon 140AVR354 harman/kardonharman/kardon 141AVR354 harman/kardonh

36、arman/kardon 142AVR354 harman/kardonharman/kardon 143AVR354 harman/kardonharman/kardon 144AVR354 harman/kardonharman/kardon 145AVR354 harman/kardonharman/kardon 146AVR354 harman/kardonharman/kardon 147AVR354 harman/kardonharman/kardon 148AVR354 harman/kardonharman/kardon ST2325V POWERED MULTI-CHANNE

37、LRS-232 DRIVERS AND RECEIVERS February 2001ISUPPLYVOLTAGERANGE: 4.5TO5.5VISUPPLYCURRENT NOLOAD(TYP):5mAITRANSMITTEROUTPUT VOLTAGESWING(TYP):7.8VICONTROLLEDOUTPUTSLEWRATEIRECEIVERINPUTVOLTAGERANGE: 30VIDATARATE(TYP):220KbpsIOPERATINGTEMPERATURERANGE:-40TO85oC,0TO70oCICOMPATIBLEWITH MAX232ANDMAX202DES

38、CRIPTIONThe ST232 is a 2 driver, 2 receiver devicefollowing EIA/TIA-232 and V.28 communicationstandard.It is particularly suitable for applicationswhere 12V is not available. The ST232 uses asingle 5V power supply and only four externalcapacitors (0.1F). Typical applications are in:PortableComputers

39、,LowPowerModems,Interfaces Translation, Battery Powered RS-232System,Multi-Drop RS-232 Networks.D(Micro Package)N(Plastic Package)W(Micro Package Large)T(TSSOPPackage)ORDER CODESTypeTemperatureRangePackageCommentsST232CN0 to 70oCDIP-1625 parts per tube / 40 tubeper boxST232BN-40 to 85oCDIP-1625 part

40、s per tube / 40 tubeper boxST232CD0 to 70oCSO-16 (Tube)50 parts per tube / 20 tubeper boxST232BD-40 to 85oCSO-16 (Tube)50 parts per tube / 20 tubeper boxST232CDR0 to 70oCSO-16 (Tape& Reel)2500 parts per reelST232BDR-40 to 85oCSO-16 (Tape& Reel)2500 parts per reelST232CW0 to 70oCSO-16 Large (Tube)49

41、parts per tube / 25 tubeper boxST232BW-40 to 85oCSO-16 Large (Tube)49 parts per tube / 25 tubeper boxST232CWR0 to 70oCSO-16 Large (Tape & Reel)1000 parts per reelST232BWR-40 to 85oCSO-16 Large (Tape & Reel)1000 parts per reelST232CT0 to 70oCTSSOP16 (Tube)only for samplesST232BT-40 to 85oCTSSOP16 (Tu

42、be)only for samplesST232CTR0 to 70oCTSSOP16 (Tape & Reel)2500 parts per reelST232BTR-40 to 85oCTSSOP16 (Tape & Reel)2500 parts per reel1/11149AVR354 harman/kardonharman/kardon PIN CONFIGURATIONPIN DESCRIPTIONPIN NoSYMBOLNAME AND FUNCTION1C1+Positive Terminal for the first Charge Pump Capacitor2V+Dou

43、bled Voltage Terminal3C1-Negative Terminal for the first Charge Pump Capacitor4C2+Positive Terminal for the second Charge Pump Capacitor5C2-Negative Terminal for the second Charge Pump Capacitor6V-Inverted Voltage Terminal7T2OUTSecond Transmitter Output Voltage8R2INSecond Receiver Input Voltage9R2OU

44、TSecond Receiver Output Voltage10T2INSecond Transmitter Input Voltage11T1INFirst Transmitter Input Voltage12R1OUTFirst Receiver Output Voltage13R1INFirst Receiver Input Voltage14T1OUTFirst Transmitter Output Voltage15GNDGround16VCCSupply VoltageABSOLUTE MAXIMUM RATINGS(Note 1)SymbolParameterValueUni

45、tVCCSupply Voltage-0.3 to 6VTINTransmitter Input Voltage Range-0.3 to (VCC+ 0.3)VRINReceiver Input Voltage Range30VTOUTTransmitter Output Voltage Range(V+ + 0.3) to (V- - 0.3)VROUTReceiver Output Voltage Range-0.3 to (VCC+ 0.3)VTSCTOUTShort Circuit Duration on TOUTinfiniteTstgStorage Temperature Ran

46、ge-65 to +150oCAbsoluteMaximumRatingsarethosevaluesbeyond whichdamage tothedevicemayoccur. Functionaloperationunderthese condition isnot implied.Note1:Noexternal supply can beappliedtoV+terminalandV- terminal.ST2322/11150AVR354 harman/kardonharman/kardon 1/26January 2005M24C64M24C3264Kbit and 32Kbit

47、 Serial IC Bus EEPROMFEATURES SUMMARYTwo-Wire I2C Serial InterfaceSupports 400kHz ProtocolSingle Supply Voltage:4.5 to 5.5V for M24Cxx2.5 to 5.5V for M24Cxx-W1.8 to 5.5V for M24Cxx-RWrite Control InputBYTE and PAGE WRITE (up to 32 Bytes)RANDOM and SEQUENTIAL READ ModesSelf-Timed Programming CycleAut

48、omatic Address IncrementingEnhanced ESD/Latch-Up ProtectionMore than 1 Million Erase/Write CyclesMore than 40-Year Data RetentionTable 1. Product ListFigure 1. PackagesReferencePart NumberM24C64M24C64M24C64-WM24C64-RM24C32M24C32M24C32-WM24C32-RPDIP8 (BN)81SO8 (MN)150 mil width81TSSOP8 (DW)169 mil wi

49、dthUFDFPN8 (MB)2x3mm (MLP)151AVR354 harman/kardonharman/kardon M24C64, M24C324/26SUMMARY DESCRIPTIONThese I2C-compatible electrically erasable pro-grammable memory (EEPROM) devices are orga-nized as 8192 x 8 bits (M24C64) and 4096 x 8 bits(M24C32).Figure 2. Logic DiagramI2C uses a two-wire serial in

50、terface, comprising abi-directional data line and a clock line. The devic-es carry a built-in 4-bit Device Type Identifier code(1010) in accordance with the I2C bus definition.The device behaves as a slave in the I2C protocol,with all memory operations synchronized by theserial clock. Read and Write