Hitachi-HTDK170E-mc-sm 维修电路原理图.pdf

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1、CAUTION:Before servicing this chassis, it is important that the service technician read the “Safety Precautions” and “Product Safety Notices” in this service manual.ATTENTION:Avant deffectuer lentretien du chassis, le technicien doit lire les Prcautions de scurit et les Notices de scurit du produit

2、prsents dans le prsent manuel.VORSICHT:Vor ffnen des Gehuses hat der Service-Ingenieur die Sicherheitshinweise“ und Hinweise zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.SERVICE MANUALMANUEL DENTRETIENWARTUNGSHANDBUCHData contained within this Service manual is subject to alteration fo

3、r improvement.Les donnes fournies dans le prsent manuel dentretien peuvent faire lobjet de modifications en vue de perfectionner le produit.Die in diesem Wartungshandbuch enthaltenen Spezifikationen knnen sich zwecks Verbesserungen ndern.SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT

4、DVD DIGITAL THEATRE SYSTEMJuly 2003No. 0153HTDK170EHTDK170EUKRadioFans.CN 收音机爱 好者资料库21. GENERAL DESCRIPTION1.1 ES60X8The ES6008/ES6018 Vibratto DVD processor is a single-chip MPEG video decoding chipthat integrates audio/video stream data processing, TV encoder, four video DACs withMacrovision. copy

5、 protection, DVD system navigation, system control and housekeepingfunctions.The Vibratto DVD processor is built on the ESS proprietary dual CPU ProgrammableMultimedia Processor (PMP) core consists of 32-bit RISC and 64-bit DSP processors and offersthe best DVD feature set. These features can be lis

6、ted as follows:General Features: Single-chip DVD processor based on ESS proprietary dual CPU PMP core. Integrated NTSC/PAL encoder. Four integrated 10-bit video DACs. DVD-Video, VCD 1.1, 2.0, and SVCD Interface for ATAPI devices and A/V DVD loaders. Interface for Compact Flash, Memory Stick and Smar

7、tMedia cards. Direct interface of 8- or 16-bit SDRAM up to 128-Mb capacity. Direct interface for up to four banks of 8-/16-bit EPROM or Flash EPROM for up to 16-MBcapacity.Video Related Features: Macrovision 7.1 for NTSC/PAL interlaced video. Simultaneous composite video and S-video outputs, or comp

8、osite and YUV outputs, orcomposite and RGB outputs. 8-bit CCIR 601 YUV 4:2:2 output. On-Screen Display (OSD) controller with 3-bit blending provides display with 256 colors in 8degrees of transparency. Subpicture Unit (SPU) decoder supports karaoke lyric, subtitles, and EIA-608 compliant Line21 Capt

9、ioning.Audio Related Features: Dolby Digital (AC-3) and Dolby Pro Logic.RadioFans.CN 收音机爱 好者资料库3 High-Definition Compatible Digital. (HDCD) decoding. Dolby Digital Class A and HDCD certified. CD-DA. MP3.1.2 MEMORY1.2.1 System SRAM InterfaceThe system SRAM interface controls access to optional extern

10、al SRAM, which can beused for RISC code, stack, and data. The SRAM bus supports four independent address spaces,each having programmable bus width and wait states. The interface can support not only SRAM,ROM/EPROM and memory-mapped I/O ports for standalone applications are also supported.1.2.2DRAM M

11、emory InterfaceThe Vibratto provides a glueless 16-bit interface to DRAM memory devices used as videomemory for a DVD player. The maximum amount of memory supported is 16 MB of SynchronousDRAM (SDRAM). The memory interface is configurable in depth to support 128-Mb addressing.The memory interface co

12、ntrols access to both external SDRAM or EDO memories, which can bethe sole unified external read/write memory acting as program and data memory as well asvarious decoding and display buffers.1.3 DRIVE INTERFACESThe Vibratto supports the AT Attachment Packet Interface (ATAPI), Integrated DriveElectro

13、nics (IDE), and other parallel and serial port interfaces used by many types of DVDloaders. These interfaces meet the specifications of many DVD loader manufacturers. An ATAPIdrive is connected via the standard 34 pin dual row PC style IDE header1.4 FRONT PANELThe front panel is based around an Futa

14、ba VFD and a common NEC front panelcontroller chip, (uPD16311). The ES6008/ES6018 controls the uPD16311 using several controlsignals, (clock, data, chip select). The infrared remote control signal is passed directly to theES60X8 and 8051 for decoding.1.5 REAR PANELOutputs and Inputs at the AV1000 re

15、ar panel:- Left, Right and Subwoofer (active) audio outputs.- Left, Right and CVBS input.- Composite, S-Video, and SCART outputs.- Input SCART- 5x15W 8ohms (L,R,SL,SR,C) + 1x25W 4ohms Subwoofer outputs.- AM / FM Tuner Antenna input- 220-240 V 50Hz AC Power inputThe six-video signals used to provide

16、CVBS, S-Video, and RGB are generated by the ES60X8sinternal video DAC. The video signals are buffered by external circuitry.Six channel audio output by the ES6018 in the form of three I2S (or similar) data streams. TheS/PDIF serial stream is also generated by the ES60X8 output by the rear panel. A s

17、ix channelaudio DAC (AK4356) are used for six channel audio output with ES6018, and similarly oneAK4362A Audio DAC is used for two channel audio output with ES6008 or ES6018.42. SYSTEM BLOCK DIAGRAM and ES6008/18 PIN DESCRIPTION2.1 ES6008/18 PIN DESCRIPTION5 6789102.1 SYSTEM BLOCK DIAGRAMSystem bloc

18、k diagram is shown in the following figure:3. AUDIO OUTPUTThe ES6008 supports two-channel analog audio output while ES6018 supports six-channelanalog audio output. In a system configuration with six analog outputs, the front left and rightchannels can be configured to provide the stereo (2 channel)

19、outputs and Dolby Surround, or theleft and right front channels for a 5.1 channel surround system.The ES6008 also provides digital output in S/PDIF format. The board supports both optical andcoaxial S/PDIF outputs.AV1000 Has also 5.1 channel Class-D amplifier outputs to 8 ohms satelites and 4 ohmssu

20、bwoofer.4 AUDIO DACSThe ES6008/18 supports several variations of an I2S type bus, varying the order of the data bits(leading or no leading zero bit, left or right alignment within frame, and MSB or LSB first) ispossible using the ES6008/18 internal configuration registers. The I2S format uses four s

21、tereodata lines and three clock lines. The I2S data and clock lines can be connected directly to one ormore audio DAC to generate analog audio output.The two-channel DAC is an AKM AK4382A. The DACs support up to 192kHz sampling rate.The outputs of the DACs are differential, not single ended so a buf

22、fering circuit is required. Thebuffer circuits use National LM833 op-amps to perform the low-pass filtering and the buffering.115 VIDEO INTERFACE5.1 Video Display OutputThe video output section controls the transfer of video frames stored in memory to the internal TVencoder of the Vibratto. The outp

23、ut section consists of a programmable CRT controller capable ofoperating either in Master or Slave mode.The video output section features internal line buffers which allow the outgoing luminance andchrominance data to match the internal clock rates with external pixel clock rates, easilyfacilitating

24、 YUV4: 2:2 to YUV4: 2:0 component and sample conversion. A polyphase filterachieves arbitrary horizontal decimation and interpolation.Video BusThe video bus has 8 YUV data pins that transfer luminance and chrominance (YUV) pixels inCCIR601 pixel format (4:2:2). In this format, there are half as many

25、 chrominance (U or V) pixelsper line as luminance (Y) pixels; there are as many chrominance lines as luminance.Video Post-ProcessingThe Vibratto video post-processing circuitry provides support for the color conversion, scaling,and filtering functions through a combination of special hardware and so

26、ftware. Horizontal up-sampling and filtering is done with a programmable, 7-tap polyphase filter bank for accuratenon-integer interpolations. Vertical scaling is achieved by repeating and dropping lines inaccordance with the applicable scaling ratio.Video TimingThe video bus can be clocked either by

27、 double pixel clock and clock qualifier or by a single pixelclock. The double clock typically is used for TV displays, the single for computer displays.Video Interface RegistersVID_SCN_HSTARTThe write-only Video Screen Horizontal Start Address register contains the 13-bit horizontal pixelstarting ad

28、dress of the active video display.VID_SCN_HENDThe write-only Video Screen Horizontal End Address register contains the 13-bit horizontal pixelending address of the active video display.VID_SCN_VSTARTThe write-only Video Screen Vertical Start Address register contains the 13-bit vertical scan linesta

29、rting address of the active video display.VID_SCN_VENDThe write-only Video Screen Vertical End Address register contains the 13-bit vertical scan lineending address of the active video display.VID_SCN_VERTIRQThe write-only Video Screen Vertical Line Interrupt register is selectable by software and c

30、ontainsthe line in which a vertical interrupt will occur. Line 0 is the top of the screen, as defined by theleading edge of the VSYNC pin. Typically, an interrupt is set either just before or just after theactive video display.VID_SCN_HBLANK_STARTThe write-only Video Screen Horizontal Blanking Inter

31、val Start Address register contains the 13-bit starting address of the horizontal blanking interval for the active video display.12VID_SCN_HBLANK_STOPThe write-only Video Screen Horizontal Blanking Interval End Address register contains the 13-bitending address of the horizontal blanking stop interv

32、al for the active video display.VID_SCN_VBLANK_STARTThe Video Screen Vertical Blanking Interval Start Address register contains the 13-bit startingaddress of the vertical blanking interval for the active video display.VID_SCN_VBLANK_STOPThe write-only Video Screen Vertical Blanking Interval Stop Add

33、ress register contains the 13-bitending address of the vertical blanking stop interval for the active video display.VID_SCN_HSYNCWIDTHThe write-only Video Screen Horizontal Sync Width Pulse register contains the 13-bit value of thehorizontal sync pulse width for the active video display. This regist

34、er is needed only if syncdirection is outputVID_SCN_HSYNCPERIODThe write-only Video Screen Horizontal Sync Period register contains the 13-bit value for theperiod of the horizontal sync pulse used by the active video display. It is needed only if syncdirection is output.VID_SCN_VSYNCPERIODThe write-

35、only Video Screen Video Sync Period register contains the 13-bit value for the period ofthe vertical sync pulse used by the active video display. This register is needed only if syncdirection is output.VID_SCN_VSYNCPIXELThe write-only Video Screen Vertical Sync Pixel register defines which pixel VSY

36、NC will changeon for the active video display. The number of pixels delayed from HSYNC that VSYNC willchange on either the rising or falling edge of VSYNC. This register is needed only if sync directionis outputVID_SCN_VSYNCWIDTHThe write-only Video Screen Vertical Sync Pulse Width register defines

37、the width of the 6-bitvertical sync pulse. It is needed only if sync direction is outputVID_SCN_VERTCOUNTThe read-only Video Screen Verital Counter register contains the current line of the verticalcounter, and starts its counting at VSYNC line 0. This register is typically used for testing only.VID

38、_SCN_HORIZCOUNTThe read-only Video Screen Horizontal Counter register contains the current pixel of thehorizontal counter, and starts its counting at HSYNC pixel 0. This register is typically used fortesting only.VID_SCN_COUNTER_CTLThe write-only Video Screen Counter Control register contains counte

39、r control bits for the invertedblank sync, inverted horizontal sync, and inverted vertical sync functions. This register initializesto 0 x00 after reset.VID_SCN_OUTPUTCNTLThe Video Screen Output Control register contains the control logic used to control the clampingand filtering characteristics of

40、the signal being output to the video display.13VID_SCN_ITERFACECNTLThe Video Screen Interface Control register contains the control logic used to determine thesignal output characteristics to the video display.VID_SCN_RESETSThe Video Screen Reset register contains the control logic for reset events,

41、 including the resetpan and scan, horizontal filtering and DMA enabling functions. This register is set to 1 on reset.VID_SCN_STATUSThe Video Screen Status register contains the status bits for the video section.VID_SCN_OSD_HSTARTThe OSD Video Screen Horizontal Start Address register contains the ho

42、rizontal starting addressvalue for the OSD, as referenced from the active display window.VID_SCN_OSD_HENDThe OSD Video Screen Horizontal End Address register contains the 13-bit horizontal endingaddress value for the OSD, as referenced from the active video display.VID_SCN_OSD_VSTARTThe OSD Video Sc

43、reen Vertical Start Address register contains the 13-bit vertical startingaddress value for the OSD, as referenced from the active video display.VID_SCN_OSD_VENDThe OSD Video Screen Vertical End Address register contains the 13-bit vertical ending addressvalue for the OSD, as referenced from the act

44、ive video display.VID_SCN_OSD_MISCThe OSD Video Screen Miscellaneous register contains the control logic and status bits for theOSD controller.VID_SCN_OSD_PALETTEThese 16 registers contain the OSD palette.6 SDRAM MEMORYThe memory bus interface generates all the control signals to interface with exte

45、rnal memory.The Vibratto supports different configurations using the memory configuration bits SDCFG1:0(bits 12:11), the SD8BIT bit (bit 14), and SD64M bit (bit 15) in the BUSCON_DRAM_CONTROLregister. Configurations can be implemented in many ways. The following table lists the typicalSDRAM configur

46、ations used by the Vibratto.14Typical SDRAM Configurations:The memory interface controls access to both external SDRAM or EDO memories, which can bethe sole unified external read/write memory acting as program and data memory as well asvarious decoding and display buffers. At high clock speeds, the

47、Vibratto memory bus interfacehas sufficient bandwidth to support the decoding and displaying of CCIR601 resolution images atfull frame rate.7 FLASH MEMORYThe decoder board supports AMD class Flash memories. Currently 4 configurations aresupported: FLASH_512K_8b FLASH_1024K_8b FLASH_512Kx2_8b FLASH_5

48、12Kx2_16bThe Vibratto permits both 8- and 16-bit common memory I/O accesses with a removable storagecard via the host interface.8 SERIAL EEPROM MEMORYAn I2C serial EEPROM is used to store user configuration (i.e. language preferences,speaker setup, etc.) and software configuration. Industry standard

49、 EEPROM range in size from1kbit to 256kbit and share the same IC footprint and pinout. The default device is 2kbit, 256kx 8,SOIC8 SGS Thomson ST24C02M1 or equivalent.159 ATA/IDE LOADER INTERFACEThe host interface can directly support ATAPI devices such as DVD drives or I/Ocontrollers. PIO modes 0 th

50、rough 4 are supported. The ATA/IDE interface can directly control twodevices through the use of the HCS1FX# and HCS3FX# signals. The ATA/IDE interface of theVibratto uses a command execution protocol that allows the operation of audio-CD and DVDloaders to coexist on the same type of interface cable