Pioneer-CZ1-pwr-sch 维修电路原理图.pdf

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1、Q.,.2 _ zszm : Qsq. 60.61.70.JOt.m.105.16bAPI, (OB. PI OPES : -D(.3.3.4.5,6.7.8 = (3 09.tOJl.fi : . (0EZ HON MfiXK ; /C/P0 /V9i?/W ; , . . P ; PICO FARAD -4- ; EiHcro/?oLYr/c NOfif MARK ; OHM K ; fcito O H M 1 - ,/ . RadioFans.CN 收音机爱 好者资料库RadioFans.CN 收音机爱 好者资料库Adjustment of power supply voltage (+

2、85 V +0.5 V) * Before turning on switch for power supply assembly (A) , Turn VR1 and VR4 fully clockwise and the VR2 and VR3 fully counter clockwise. A). Point of measurement, B) Point of adjustment, C) Specifications, D) Notes, E) Check, F) Check, G) Check, H) Approximately DC 70 V, I) Approximatel

3、y DC 85 V, J) Adjusting both should give a reading within +0.5 V of the voltage1s absolute value. K) Approximately DC 85 V, L) Adjusting both should give a reading within +0.5 V of the voltagefs absolute value, M) Rear panel, N) Power supply assembly (A) 4. OUTLINE OF CIRCUITS Today, the performance

4、 characteristics of amplifiers have reached a new high because of the rapid develop-ments iff NFB (negative feed back technology) . Because part of the NFB amplifiers1 s output goes back to the input stage, compensation must be made for the fact that the output and input wave forms are different. Co

5、nsequently, a source of TIM (Transient intermo-dulational distortion or dynamic distortion) exists. TIM can be eliminated by not using NFB, but many char-acteristics improve with NFB although S/N & distortion do not. With FET1 s and transistors being used as amp-lification elements, unless something

6、 is done to com-pensate for this due to their non linearity character-istics , NFB will be superior to non NFB devices. The. C-Zl is a non NFB amplifier (see note) which uses a superlinear circuit based on the concept of absorbing the non linear characteristics of FET1s and transistors with a revers

7、e non linearity mode. Because the improvements of characteristics that accompany NFB are not present, quality parts have been carefully selected and wiring material and positioning have been given thorough consideration. Note: The term non NFB used here refers to the fact that a voltage feedback loo

8、p is not used. Although FET and transistors are a type of element effecting current feedback on their own, current feedback does not exist. However, the current feedback resulting from the ele-ments internal resistance plus that developed by the emitter has no relation to TIM distortion and has no i

9、nfluence on sound quality characteristics. Super linear circuit The super linear circuit by using a reverse mode non linearity completely absorbs that non linearity of the semi conductor amplifying elements resulting in super-ior linearity characteristics. This theory is explained in figure 4-1. The

10、 current from the Q4 collector, IC1 and Q5 collector current IC3 become the same as the current IC2 from the Q3 collector. (That is to say that Rl = R2 = R3) If the voltage Vi is input to the base of Ql, the Q2 emitter voltage Va is as shown in the formula below. Va = Vi + Vbel - Vbe2 (1) If Ql and

11、Q2 are the same, Vbel and Vbe 2 become equal and the term Vbe becomes equal to zero (IC1 = IC2). Va = Vi (2) IC2 is as shown in the following equation. IC2 = Va/Re = Vi/Re = IC3 (3) The output voltage Vo is as shown in the following. Vo = IC3 x Rl = (Vi/Re) x Rl = (Rl/Re) x Vi (4) That is to say, th

12、e output voltage becomes (Rl/Re) times the input voltage. The voltage Vbe (non linearity element) disappears. In the actual circuit, the collector losses of Ql and Q2 are made equal, a double push pull type power source is included, the super linear circuit is encased in an aluminum case bonded with

13、 epoxy resin to make a module. The heat characteristics and effectiveness of the shielding is improved to increase reliability. The flat amp used in the super linear circuit module (AXX-002) is as shown in figure 4-2. The first stage in the module is a push-pull source follower buffer amp-lifier att

14、ached to the FET and transistor cascade. The second stage and above consists of the complimentary super linear circuit. The output stage is outside of the module and consists of a pure class A SEPP (single ended push-pull) circuit. Current equalizer For the super linear circuit, it was shown above t

15、hat its gain was decided by the value of the load resistance (Rl) assuming that Re remains fixed. If an impedence having RIAA load characteristics is used to enhance the above features, it will be possible to include an equalizer in the circuitry. The equalizer section included for C-Zl is as shown

16、in figure 4-3. It appears to be a CR type equalizer but the difference is that while a CR type equalizer will decrease the previously amplified current, the current gain equalizer will increase the creep margin in the high ranges that the amplifier itself tends to sup-press . It is necessary to divi

17、de RIAA characteristics into increasing low levels and decreasing high levels in order to gain stability in the rectifying current and to decrease distortion. Double locked servo regulator For non NFB amplifiers, the stability of output DC voltage is extremely important. The plan for the double lock

18、ed servo regulator used in the C-Zl is as shown in figure 4-4. In this method, the voltage supply is mon-itored at a point of mid potential and this results in a current being fed back to the stabilizer control circuit to further control the voltage supply. This is different from the normal DC servo

19、 method in that there is no servo loop included in the signal circuit and that the special characteristics of the non NFB am-plifier can be attained by doing everything in a direct fashion. A) Figure 4-1 Basic super linear circuit, B) Super linear circuit module, C) Current mirror, D) Regulator, E)

20、Regulator, F) Current mirror, G) DC detection, H) Figure 4-2 The flat amp using the super linear circuit module Output buffer amplifier The input stage with a source follower push pull circuit based on FET1s and transistor cascade is a fixed current load. The output stage is a pure class A SEPP as t

21、he DC voltage at the output midpoint is checked and the fixed current source is controlled thus keeping the output midpoint at zero potential. A) Current equalizer load (Raises lower values), B) Equalizer filter (Lowers higher values) C) Super linear circuit module, D) Super linear circuit module, E

22、) Bias circuit, F) Bias circuit, G) Figure 4-3 Schematic for the current equalizer, H) Super linear circuit, I) DC detection circuit, J) Power transformer, K) Rectifier circuit, L) Stabilized fixed voltage supply, M) Stab-ilized fixed voltage supply, N) Figure 4-4 Basic plan for double locked servo

23、regulator, 0) DC detection circuit, P) Figure 4-5 Schematic for the buffer ampli-fier , Q) Equalizer amplifier, R) Flat amplifier, S) Buffer amplifier, T) Figure 4-6 Layout of relays Other (The signal system) * Changing of cartridge load The input resistance and capacity for the phono circuit can be

24、 changed in three different stages, al-lowing adapting to the cartridge load characteristics. * Phono sub sonic filter If the function switch is put on PHONO SUBSONIC, the Cr filter (fc = 15 Hz, -6 dB/oct) part of the equalizer circuit is connected cutting out very low frequencies. * Volume control

25、A high quality 4 step switch is used improving S/N by controlling output. * Tone control Tone can be controlled by using a fixed loss of -3 dB Cr tape from BASS (50 Hz) to TREBLE (20 kHz) in 1.5 dB steps with a variation of +3 dB. When the TONE is off, the signal passes through a -3 dB attenuator. R

26、elay control logic circuit In the operation part of the C-Zl, feather touch tactile switches are employed, with the signal circuit relays being controlled by the logic circuits. Figure 4-6 shows the position of the relays while operating. Figure 4-7 shows the control circuits for the relays. The fig

27、ure shows Ql composed of a CMOS digital IC which has four pairs of built in clocked D latches. Q2 is composed of CMOS digital IC1 s which have two pairs of built in J-K flip flops. Q3 and Q4 are composed of digital IC1s (Not circuits) having seven NPN Darlington transistors and with just a small inp

28、ut, large values of current can be switched. (400 mA max) . For the function changing circuit, (TUNER, AUX, PHONO, PHONO SUBSONIC) a D latch is utilized which permits selecting the desired operation. The D latch fixes the value of the output signal to that of the clock pulse signal which enters (eit

29、her L or H) . Afterwards, even if the input should change, the output will not change. When the function button is pushed, it is detected that D1-D4 St C9 change from L to H and clocked pulse input into D latch. Because the D latch in the circuit of the button pushed has an H level input, the output

30、 is set at H level. Because the others have a low level input, the output. is set at L level. The D latch being a H level output circuit and in order to make the next stage1s Not gate output L level (NPN transistor is on) the circuit relays operate; the indicator lamps are illuminated. For the TONE

31、and TAPE MONITOR circuits, pushing the relevent button will input into the flip flop terminal (CK) at which time the flip flop will reverse. When the output of the flip flop is H level, the NOT gate output (Q) in the next stage will be L level (NPN transistor is on) , the relays will operate and the

32、 indicator lights will be illuminated. A) D30-37 Signals and root indicators, B) Figure 4-7 Relay control logic circuit * Output muting There is muting capacity (ground type) used for pre-venting transient noises when turning the C-Zl on and off. When the power is switched on (See figure 4-7) Q12 re

33、ceives load voltage from D40 and D41 and is switched off, CI is charged and Q91 s base voltage is raised. After about 22 seconds, Q8 and Q9 are switched on and the output muting relay RL 8 (at brake) operates, and muting (output circuit ground) is terminated. With the charging of C2 in about 20 seco

34、nds, (about 2 seconds before muting is cancelled, Q10, Qll and Q7 are switched on and the relays in the signal circuit operate and the signal root indicator LED is il-luminated. When power is turned off, Q12 is switched on by the residual power because the reverse bias quickly dis-appears , Q7-Q11 g

35、o off and all relays are released (except for RL6 and RL7) and the muting condition is resumed. * Memory for switch position Because the D latch and flip flop IC1 s are of the CMOS type, a small amount of current (in micro amps.) is sufficient to preserve their contents. The backup current for these

36、 IC1s is furnished by a 2.5 F condenser (4 x 10 F capacitors) and even if the AC current is cut off for 3 days or more, the switch position information is preserved. *Reset/Preset circuit If the back up time is exceeded on the above men-tioned condenser, the button switch positions will resume their

37、 starting position when the current is again turned on. In order to recharge the backup con-densers (C12-C15) when the power is turned on, the Q5 emitter voltage is temporarily lowered, passing through R42 and D26, the Q6 voltage is reduced and Q6 is temp-orarily switched on. Because of this, the Q6

38、 collector voltage rises, the reset pulse passes through Cll and is supplied to the D latch and flip flops. Output Q becomes L level and the Tone and TAPE MONITOR are put in off position.The reset pulse is input into the clock terminal of the D latch and also passes Dil of the turner circuit and inputs into the data terminal. As a result, only this circuit1 s D latch is set at H level and becomes the TUNER function.