Arcam-DV29-dvd-sm维修电路原理图.pdf

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1、ServiceManualDV29 DVD PlayerIssue 1.0ARCAMARCAMBringing music & movies to lifeBringing music & movies to lifeRadioFans.CN 收音机爱 好者资料库 Circuit Description Power Supply L959AY ! CCT diagram ! Component layout diagram ! Parts list Main Board L971AY ! CCT diagram ! Component layout diagram ! Parts list D

2、isplay Board L972AY ! CCT diagram ! Component layout diagram ! Parts list Transformers ! L924TX ! L925TX ! L931TX Mechanical Assembly ! Mechanical and packing part list DV29 Contents List RadioFans.CN 收音机爱 好者资料库 Overview The DV29 is effectively a no compromise version both electronically and mechani

3、cally of the DV79. The player is based around acclaimed Zoran Vaddis V chipset coupled to high specification Wolfson D to A converters for all six audio output channels, also featured in this design is a HDMI transmitter with digital Video and a Audio output capable of Digital Surround. The DV29 and

4、 the DV79 use the same main board and power supply stage but with many of the components either upgrade or replaced with different topologies, many of the critical audio/video components with 0.1% tolerance within the DV29 and we also have an extra toroid power supply for the Audio stages. Both the

5、HDMI chip and Video encoder are of a higher quality than those found inside the DV79. Power supply board. Non-switching Mains power arrives at IEC inlet socket SKT1 and is filtered by EMC choke LI and Y caps C3 and C4, mains switch SW2a/b switches both Negative and Live phases before the power reach

6、es the mains select switch at location SW1 the switch allows the primary windings of the transformer TX1 to be wired in either Parallel or Series configuration. The Bridge rectifying Diode package at location D1 forms the basis of the conventional power stage and supplies a VN35V6 (-35.6v) to the Sw

7、itch mode stage, transistor TR1 is biased by 2v7 Zener diode DZ1 and allows for the series Zener diodes DZ2, DZ3, DZ3 to supply the VN13V5 and VN19V rails. We will also see a simple A.C present circuit this is used for delayed output relay operation and fast relay closure under interrupted supply co

8、nditions thus preventing op-amp offsets from reaching the Audio output sockets. Switch mode The switch mode supply is formed around the Driver/Control chip IC1 UC3843 (used in regulating mode). The chip is referenced the 36.5V supply line and the Digital ground DGND, the supply for the chip is forme

9、d by the 12v Zener at location DZ6 and can be seen on Pin 7 as VCC. The power supply allows for the switch-mode to be tied the to Audio sampling frequency for any given compatible format see Fig 1. Fig 1 PSU clock control and IC305 line status Fs Frequency select PSUFS1 Pin 11 IC305a PSUFS0 Pin 12 I

10、C305a PSUCLK Output Pin 5 of IC305a 44.1 kHz 0 0 44.1 kHz 48 kHz 0 0 48 kHz 88.2 kHz 0 1 44.1kHz 96 kHz 0 1 48 kHz 176.4 kHz 1 0 44.1 kHz 192 kHz 1 0 48 kHz Others 1 1 OFF The PSU sync signal is driven into the power supply via Resistor R9 if no Sync is present the unit is set to free run at xxxx du

11、e to the RT/RC network attached to Pin 4. IC1 is running in regulated mode and monitors the voltage output on the +5V and +3V3 D.C lines, the two voltages are summed by TR8 and Driven into the VFB and Comp inputs of IC1, the Voltage is then regulated by changing the time base of the PWM output at pi

12、n 6 (longer the time base the lower the voltage), the PWM switching frequency is driven into the switch-mode transformer by the high speed Nmos device at position M1, R5 is used to sense the Current across the gate of the Nmosfet and in the event of a short circuit will safely shut the power supply

13、down. We derive the 12v Mech supply from the output of M1 using the Ultra-fast Diode at location D8 to rectify the PWM line. The D.C outputs from the switch mode have extensive switch mode noise removing filters these are seen as 100n caps down to ground and Wire wound inductors in series with the s

14、upply rail. Power supply main board All the power supply rails are supplied to the main board via the 32 way FFC conector at location CON1001. The Digital supplies from the switch mode stage of the power supply arrive as 3V3D, +5VD and +12VD we also see the Display board power supplies arrive as 19V

15、, -9V and 13.5V all of the supplies have a second stage of implemented on the board to remove all traces of ultra-sonic noise. The 3V3D rail is the main 3V3 rail used to power the digital circuitry; +5VD is used for all 5v Digital/Video supplies the +12VD is used for Scart switching and to power the

16、 HDMI circuit (not DV78). The 1V8 rail is derived from the 3V3 rail and is regulated by the adjustable regulator at location REG1003. FMJ Dv29 Circuit description. The DV29 uses a separate isolated Toroid transformer and Rectification stages based around Bridge rectifiers DBR1000 and DBR1001 and bul

17、k smoothing caps C1048 and C1049 to supply the Analogue stages the smoothed D.C output from this stage is fed L1013 (+) and L1015 (-). Regulator REG1001 is fed from the +15V3 rail and forms the Audio DAC supply. The Display board requires several supply voltages these are simply passed through the m

18、ain board, being filtered on the way to prevent transmission of noise through to the surrounding electronics. The display takes the +5V, -19V, -13V5 and -9V the 13V5 and 9V form a floating 4.5V supply biased relative to the 19V grid voltage. Display Board The main component of the Display board is I

19、C1 this is a Vacuum Florescent Display driver with keyboard san and a serial data in/out interface. The Chip receives display drive serial data from the Vaddis V chip on the main board via Con1 on pins 12, 13 and 14 these will be seen a DIN, STS and CLK this data is used to drive the VFD a DOUT line

20、 interfaces with the VADDIS V and supplies Keyboard Scan information. The keyboard scan is a 6 x 4 matrix with the Key Source appearing at S3, S4, S5, S6 and the Keyscan data returns appearing a K2, K3 and K4. Please see: above for power supply information. The Infra red pick-up at location RXI rece

21、ives RC5 data and send the data to the Vaddis V on the main board via transistors TR2 and TR3, LED 2 is used to mix the rear panel RC5, this is covered in-depth within the Coms and Video output section of this guide. Main Board electronics Zoran Vaddis V. The main processor/control chip on the main

22、board is the Zoran Vaddis V at location IC202, this is the latest incarnation of the very popular Vaddis range of processors and allows for a much lower component count when compared to our earlier players as many of the playback functions have moved onto the Vaddis V silicon. Below you will see the

23、 major functions of the Vaddis V o 20 Bit digital video output for external Video DACs and HDMI output stage. o Decoded Analogue Video output (internal DAC) used on the DV78 only. o Digital Audio output 3 data lines 6 channels for internal L + R DACs and L + R + C + LS + RS for DV79 and DV29 also us

24、ed for HDMI for the DV79 and DV29. o SPDIF output. o Internal display interface. o Internal ATAPI interface. o Internal IR interface. o Serial in/out for RS232 DV79/DV29 A more detailed explanation of the Vaddis V and peripheral components follows. Vaddis Power The Vaddis V is powered by two separat

25、e supplies the Vaddis requires a 1.8v supply for the core, this is regulated from the 3.3v rail by REG1003, the 3.3v rail is used to supply power to the I/P O/P ports of the chip. ATAPI interface CON203 is an ATAPI interface on a 40 way IDE connector. This is decoupled from the Drive via an array of

26、 decoupling resistors as required by the ATAPI spec. Display Board interface The display board interface is on the 16 way FFC flexi foil connector at location CON202. Power for the display also travels on the connector. There are 4 wires to interface with the VFD driver chip these are seen as. o XFP

27、DIN - Data to the display board o FPDOUT - Data from the display board o XFPCLK - Clock o XFPSEL - Chip select The above control lines are level shifted to 5v logic from 3.3v levels by IC200 (74HCT125) these are the levels required by the VFD drive chip. The IR output from the Display board arrives

28、as IRRCV this is an open collector signal, which can be wire-Ord with the re-panel remote input. Digital Audio The Digital audio leaves the chip 3 sets of data lines labelled as. o ADAT0 - Left and Right channel data o ADAT1 - Left and Right surround o ADAT2 - Centre and Sub Along with the ADAT line

29、 we will also see the ABCLK and ALRCK as required for IS2 data conversion. The Vaddis V also supplies a direct SPDIF output for interfacing with ancillary processing equipment. Digital Video The Digital Video output from the Vaddis V consists of the following signals: o VIDPO to 19 - 20 Bit wide dig

30、ital video data o CLK_27M - 27 Mhz Video clock o VSYNC - Vertical sync o HSYNC - Horizontal Sync The 20 bit wide bus VIDP0 to 19 provides video data as follows. Interlaced video mode: VIDP0 to 7 provide multiplexed 8 bit Y, Cb and Cr data with VIDPO being the Isb. Progressive scan video mode: VIDP0

31、to 9 provide 10 bit multiplexed Cb, Cr data with VIDP0 being the Isb. VIDP10 to 19 provide 10 bit Y data with VIDP10 being the Isb. Flash/ SDRAM IC203 is a 64Mbit (32 bit x 2Meg) SDRAM. It runs at 135MHz IC205 is a 16Mbit (16 bit x 1Meg) intel type flash IC for program storage (Player software). The

32、 flash interfaces to the Vaddis V using the SDRAM bus it may appear that the bus connects to the flash in a random manner, however this is simply because the Vaddis bus is multiplexed that way. The Flash will be accessed at power up and the contents are copied to the SDRAM the program will then be r

33、un from the SDRAM. Series resistors are employed to isolate the flash bus from the main SDRAM bus. EEPROM IC204 is a 8kBit (1K x 8) Serial EEPROM. This is used for storage of non-volatile storage of player settings, region settings and bookmark data. Clocks CLK27MV is the 27Mhz clock for video. It i

34、s used to generate the 135Mhz clock for the Vaddis microprocessor and DSP. The MCLKV is the audio master clock for the Vaddis. We run the Vaddis in PLL bypass mode and generate or own master clock (see main clock section of manual) for higher accuracy and improved performance across Audio and Video.

35、 RESET IC201 is a reset generator chip that monitors the +3.3V rail and ensures a reset signal PWR_ON_RESET* is generated on power up, or if the mains power dips below an operational level. This signal is used to reset the Vaddis V and Flash micro only. The Vaddis V line labelled as RESET* resets th

36、e remaining circuitry of the player apart from the HDMI chip, this has its own reset line labelled as HDMI_RESET this is necessary if we require to reset the HDMI chip only (for example when the HDMI sink is connected and then disconnected). Serial Port The VADDIS V can interface with the external w

37、orld via the RS232 connector at location CON900 and the RS232 Transceiver at location IC900, the serial data lines are shown as SERIAL RX and SERIAL TX these lines allow for direct control over the unit via RS232. Fig 3. GPIO control signals from the Vaddis V Single Name I/P-O/P Function PSUFSO-1 Ou

38、tput Control PSU Clock divider ENABLE_AV Output SCART control High in normal operation and low in standby 16/9 Output Scart 16/9 anamorphic control line 9190INT* Input Interrupt signal from SII9190 HDMI transmitter GAIN_SCALING Output High for HDCD gain scaling ML_8740_0-2 Output SPI load signal for

39、 Audio DACs 0,1 and 2 (see note 1) MC Output SPI clock signal for DAC control MD Output SPI data signal for DAC control FSELE0-1 Output Frequency select generator MUTE* Output Active low audio mute signal DDC_SDA,DDC,SCL I/O 12C bus for DDC channel on HDMI interface PROG_INT* Output High for Progsca

40、n mode, Low for interlaced mode. Controls Sil9130 data mux HDMI_RESET* Output Reset signal for HDMI transmitter RESET* Output System reset Clocks and SPDIF stage. IC300 is a SM8707E clock generator IC. This IC is sensitive to noise on its power supply, which causes clock jitter for this reason we ha

41、ve a independent Low dropout low noise +3v3 power supply for the chip based around the regulator at location REG300. X300 is a 27Mhz crystal that IC300 uses to generate all the video and audio clocks required by the system the crystal sits on the XTI and XTO pins of the chip, the 27Mhz output at Pin

42、 4 (MO2) is used to drive the Vaddis chip directly bypassing the internal PLL. The frequency of the audio master is dependent on the on the current audio sample rate (I.e the sample rate required by the format CD=44.1Khz and DVD=48khz etc) and this is set by the system micro via the FSLO and FSEL1 t

43、his selects either the 22.5792Mhz or 24.576Mhz clock from frequency from IC300 this may then be divided by 2 by the clock divide chip at location IC306 depending on the status of FSEL1. Therefore 4 clock frequencies may be obtained to support all required audio samples rates. Nand gate IC303 is used

44、 to gate FSEL1 with ENABLE_AV (which is low in standby mode) as such when in standby mode the audio clock is disabled. Clock Buffer IC301 us used to buffer the audio master clock. The circuit is arranged so that each device that requires the audio master clock has its own driver these are seen as. o

45、 MCLK_DAC0 - Pin 18 o MCLK_DAC1 Pin 16 o MCLK_DAC2 Pin 14 o MCLK_VADDIS Pin 3 o MCLK_HDMI Pin 9 We also run the Mute Line from the Vaddis V IC301 this can be seen on Pin 12 and drives transistor TR401, the transistor pulls the relays RLY400, RLY500, RLY600 to ground and un-mutes the audio outputs. I

46、S2 Audio Data IC302 and IC309 are buffers for the 12S signals these ensure that the signals travelling to the DACs are point to point. IC302 deals with the ALRCK and ABCLK and IC309 the ADAT0,1,2 all signal are split into three separate lines for the three stereo DACS. PSU Clock Divider IC304 and IC

47、305 form a clock divide by 1, 2 or 4 to ensure the PSU clock is always either 44.1kHz or 48Khz (See fig 1 within the power supply description section). This circuit will also switch the PSUCLK off when switching between sample rates (the PSU will free run when the PSUCLK is not present). SPDIF Outpu

48、t The SPDIF output consists of IC308 implemented as a inline buffer and parallel output buffer. Gate A buffers the signal so that the SPDIF line from the VADDIS sees fewer loads and form a feed to the Optical output transmitter, gates B,C and D drive the SPDIF in parallel so that we can drive a 75oh

49、m load adequately. The resistors at the output of IC308 are arrange so that the output will be 500mV pk-pk when the output is terminated with a 75 ohm load at the same time the output impedance of the circuit is 75ohms as required by the Sony Philips Digital Interface specification, the transformer

50、at location TX301 electrically isolates the SPDIS output. Left and Right channel D to A stages The Wolfson WM8740 stereo DAC requires +5V(A) and a +3V3 supply along with the Digital Audio data lines already described in this guide. The Left channel output only will be described in this section as al