Yamaha Ysd917-M Digital Interface Receiver 电路图.pdf

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1、 YSD917 CATALOG No: LSI-4SD917A3 2003.3 YSD917 DIR5 Digital Audio Interface Receiver 5 Outline YSD917 is an LSI that receives and demodulates signals with the digital audio interface format that conform to EIAJ CP1201 and IEC958 standards (hereafter referred to as “DAIF signal”). This LSI can be use

2、d for to various application such as AV amplifiers because it is capable of accepting DAIF signal which sampling frequency ranges from 32 kHz to 96 kHz and the demodulated serial data output is capable of being selected from various formats. Features Fundamental Functions Sampling frequency : Two ra

3、nges are available including; 32 kHz to 48 kHz (hereafter referred to as “normal rate”) and 64 kHz to 96 kHz (hereafter referred to as “double rate”) Can select and provide various clocks to peripheral devices such as DAC and ADC as a master clock. Can supply clock to ADC and DAC in any case includi

4、ng when DAIF signal is not present. The device checks the DAIF signal at all times including when it supplies clock to ADC. Thus, it is capable of reading status information as necessary. Has a terminal that outputs a signal indicating the double rate operation. Every channel status and user data ca

5、n be read through the microcomputer interface. Has an output terminal for interrupt that informs external devices of the changes of the status information. Can be adaptable to various serial data output formats by setting a register. The relationship between the word clock and data is maintained at

6、all times including the moment of transfer from PLL unlock to lock or lock to unlock so that the effect of the transfer to peripheral devices is suppressed. Two or more devices can be used synchronously when in the slave mode. Other features Microcomputer interface with four wire serial system. Inte

7、rnal operating frequency of 25 MHz Power down mode Single power supply voltage of 5.0 V Si-gate CMOS process 28 pin SOP package (YSD917-M) RadioFans.CN 收音机爱 好者资料库 YSD917 2 Block Diagram Digital audio interface decoder and lock error judgement Microcomputer interface PLL Reference clock generation Ch

8、annel status User data Frame buffer Interrupt cause detection Clock system selection Output clock generation Serial Conversion Control signals DATA BUS Output selection DDIN PCO SDMCK INT XI XO SDO ERR/BS DBL/V SYNC/U FS128/C SI SCK /CS SO MCK /IC SDBCK SDWCK M/S /LOCK AVDD PCO AVSS M/S 1 2 3 4 MCK1

9、1 TEST 6 DDIN 5 /IC 7 VSS 8 XO 9 XI10 VDD12 SDO13 SDBCK14 SCK SI SO /CS 28 27 26 25 SYNC/U 18 INT 23 VDD 24 /LOCK 22 ERR/BS 21 DBL/V 20 FS128/C 19 VSS 17 SDMCK 16 SDWCK 15 Pin Assignment RadioFans.CN 收音机爱 好者资料库 YSD917 3 Terminal Function List No. Name I/OFunction 1 AVDD - Analog power supply for PLL

10、 (+5V) 2 PCO A PLL filter connection terminal 3 AVSS - Analog ground 4 M/S Is+ Master/slave mode selection 5 DDIN Is Digital audio interface data input 6 TEST Is+ Test terminal (To be open.) 7 /IC Is Initial clear input 8 VSS - Ground 9 XO O 24.576MHz crystal oscillator connection terminal (output)

11、10 XI I 24.576MHz crystal oscillator connection terminal (input) 11 MCK O 12.288MHz clock output 12 VDD - +5 V power supply 13 SDO O Serial data output 14 SDBCK Is/O Serial data bit clock input/output 64 fs 15 SDWCK I/O Serial data word clock input/output fs 16 SDMCK O Serial data master clock outpu

12、t 256 fs or 128 fs 17 VSS - Ground 18 SYNC/U O Serial data synchronization timing output / User data output 19 FS128/C O Serial data master clock 128 fs output / Channel status output 20 DBL/V O Double rate output / Validity flag output 21 ERR/BS O Data error detection output / Block start output 22

13、 /LOCK O PLL lock detection output 23 INT O Interrupt output 24 VDD - +5 V power supply 25 /CS I Microcomputer interface chip select input 26 SO Ot Microcomputer interface data output 27 SI I Microcomputer interface data input 28 SCK Is Microcomputer interface bit clock input Note Is : Schmidt trigg

14、er input terminal I+ : Input terminal with pull-up resistor O : Digital output terminal Ot : Three-state digital output terminal A : Analog terminal For SYNC/U, FS128/C, DBL/V and ERR/BS, their functions are selected by setting a register. RadioFans.CN 收音机爱 好者资料库 YSD917 4 Terminal Function 1. System

15、 clock: XI, XO, MCK SDMCK The crystal oscillator (24.576 MHz) is connected to the terminals XI and XO to form an oscillation circuit. Use the crystal oscillator of fundamental mode. When using an external clock, input it to XI terminal. This LSI supplies a master clock to the peripheral devices such

16、 as DAC, ADC and DSP. MCK outputs the clock of 12.288 MHz (i.e. 256fs when fs=48 kHz) that is obtained by dividing the clock of XI. For SDMCK, the operation is selected depending on the state of the PLL lock and the setting of a control register. When PLL is not locked (/LOCK=H) - (1) SDMCK outputs

17、12.288 MHz. When PLL is locked (/LOCK = L) and register CKMOD = 1 - (2) SDMCK outputs 12.288 MHz. When PLL is locked (/LOCK = L) and register CKMOD = 0 SDMCK is selected as follows according to the setting of the register LOCKMOD1-0. LOCKMOD1 LOCKMOD0 Normal rate Double rate 0 0 256fs 256fs 0 1 256f

18、s 128fs 1 - 256fs 12.288MHz (3) The mode like the above (1) ,(2)and (3) in which the clock of 12.288 MHz that is obtained by dividing the clock of XI is outputted from SDMCK, is referred to as “free-run mode”. In the slave mode, SDMCK is fixed to “L”. 2. Initial Clear: /IC Initializes the internal r

19、egisters and internal circuit. When the power supply is turned on, this terminal must be set to “L” once. The clocks of MCK, SDMCK, SDBCK, SDWCK, FS128 and SYNC are outputted at all times including when /IC = “L”. 3. Digital Audio Interface Input: DDIN Digital Audio Interface Format signal (DAIF sig

20、nal) is inputted through this terminal. 4. Analog circuit for PLL: PCO The capacitor for PLL is connected here. Connect a capacitor of 4700pF between the terminals PCO and AVSS. PCO 4700pF YSD917 5 5. Serial data interface: SDBCK, SDWCK, FS128, SYNC, SDO Supplies clocks to the peripheral devices suc

21、h as DAC, ADC and DSP. The period of SDBCK, SDWCK and FS128 is obtained as follows by dividing the clock of SDMCK. SDBCK 64fs SDWCK fs FS128 128fs In the slave mode, SDBCK and SDWCK are input terminals and FS128 and SYNC are fixed to “L”. SDO is the demodulated data output of DAIF signal. The data i

22、s always 24 bit wide including auxiliary bits. The timing of serial data interface signal can be selected from the following formats by setting a control register. SDBCK SDWCK MLML MLML M8 7LM8 7L M6 5LM6 5L M4 3LM4L3 MLML M : MSB DATA L : LSB DATA 1 Frame L chR ch SDO SDOFMT1-0 = 00 SDOBIT1-0 = XX

23、SDOFMT1-0 = 10 SDOBIT1-0 = XX SDOFMT1-0 = 01 SDOBIT1-0 = 00 SDOFMT1-0 = 01 SDOBIT1-0 = 01 SDOFMT1-0 = 01 SDOBIT1-0 = 10 SDOFMT1-0 = 01 SDOBIT1-0 = 11 SDOBP = 1 SDOBP = 0 SDOWP = 0 SDOWP = 1 Register YSD917 6 6. Output terminals for channel status and others: BS, V, U, C The signals obtained from DAI

24、F signal including block start, validity flag, user data and channel status are outputted through BS, V, U and C terminals respectively. 7. Status information monitor terminals: /LOCK, ERR, DBL, INT /LOCK outputs “L” when PLL is locked to DDIN input. ERR terminal outputs “H” when PLL is not locked t

25、o DDIN input or if a parity error is detected. DBL outputs “H” when PLL is locked at double rate (fs = 64 to 96 kHz) and when this device is not in free- run mode. It outputs “L” when PLL is locked at normal rate (fs = 32 to 48 kHz) or when this device is in free- run mode. INT outputs “H” when the

26、cause of an interrupt is detected. 8. Serial microcomputer interface: /CS, SCK, SI, SO This is a four wire serial interface for reading or writing the control registers. SO becomes an output terminal only when all of the following conditions are met. /CS = L When reading the valid addresses Timing o

27、f 8 bits data output If any of the above condition is not met, SO outputs High-Z. Thus SO, SI and SCK can be used jointly with other devices that has the similar interface. The microcomputer interface functions at all times including power down mode. 9. Other terminals: M/S, TEST M/S selects the mas

28、ter or slave mode when two or more of this LSI are used. When this terminal is open or connected with VDD, this device operates in master mode, or in slave mode when connected with VSS. TEST is a terminal for testing the LSI. Keep it open when using this device. A0A1A2A3A4A5A6R/W D0D1D2D3D4D5D6D7Don

29、t Care High-Z A0A1A2A3A4A5A6R/WDont CareDont Care High-Z D0D1D2D3D4D5D6D7 High-Z SO SI SO SCK SI /CS write R/W = L Read R/W = H Dont Care Dont Care Address of register Address of register Read data Write data YSD917 7 Electrical Characteristics 1. Absolute maximum ratings Item Symbol Conditions Min.

30、 Max. Unit Supply voltage VDD AVDD Vss-0.5 Vss+7.0 V Input voltage VI -0.5 VDD+0.5 V Storage temperature Tstg -50 125 C 2. Recommended operating conditions Item SymbolConditionsMin. Typ. Max. Unit Supply voltage VDD AVDD 4.75 5.0 5.25 V Operating temperature XI clock frequency Top fxin 0 25 24.576 7

31、0 C MHz 3. DC characteristics Condition: Under recommended operating conditions Item SymbolConditions Min. Typ. Max. Unit H level input voltage (1) VIH1 *1 0.8VDD V H level input voltage (2) VIH2 *2 2.2 V L level input voltage (1) VIL1 *1 0.2VDDV L level input voltage (2) VIL2 *2 0.8 V H level outpu

32、t voltage VOH IOH = -80A VDD-1.0 V L level output voltage VOL IOL = 1.6 mA 0.4 V Input leakage current ILI Terminal without pull up resistor -10 10 A Pull up resistor RU 25 100 k Power consumption PD Locked at 96kHz. 120 150 mW *1 : Applies to input terminals of XI, DDIN, /IC and M/S. *2 : Applies t

33、o input terminals other than the above. YSD917 8 Example of System Configuration YSD917 (DIR5) ADCDSPDAC XI XO DAIF (SPDIF) DDIN SDO SDMCK SDBCK SDWCK Analog HOST PROCESSOR /CS SCK SI SO /LOCK ERR DBL INT 24.576MHz YSD917 9 External Dimensions of Package YSD917 AGENCY All rights reserved Address inq

34、uiries to: Semiconductor Sales & Marketing Department Head Office203, Matsunokijima, Toyooka-mura Iwata-gun, Shizuoka-ken, 438-0192, Japan Tel. +81-539-62-4918Fax. +81-539-62-5054 Tokyo Office2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568, Japan Tel. +81-3-5488-5431Fax. +81-3-5488-5088 Osaka Office3-

35、12-12, Minami Senba, Chuo-ku, Osaka City, Osaka, 542-0081, Japan Tel. +81-6-6252-6221Fax. +81-6-6252-6229 Printed in Japan 2003 IMPORTANT NOTICE 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been caref

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