Alinco_DR-138_serv.pdf

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1、 * Specifications * Circuit Description * Parts list * Schematic Diagram * Block Diagram * PC Board View * Mechanical Parts ALINCO, INC. DR-138 Service ManualService Manual DR138 SPECIFICATIONS General Frequency Range RX136174MHz TX136174MHz Number of channels200 Operation modeFM16KF3E (Wide) 11KF3E

2、 (Narrow) PLL Stepping2.5, 5, 6.25, 8.33, 10, 12.5, 20, 25, 30, 50KHz Antenna Impedance50 Working temperature20+60 Power Supply13.8V DC15% (11.715.8V) Grounding MethodNegative ground Current DrainLess than 300mA on standby Less than 600mA on receive Less than 10A on transmit Frequency Stability2.5pp

3、m Dimensions (W x H x D) (Dimensions including protrusions) 145 x 47 x 190 mm Weight (Including microphone)Approx. 1.2kg TRANSMITTER Power Output High60W Mid25W LowAbout 10W ModulationReactance modulation Maximum frequency deviationWide : 5kHzNarrow : 2.5kHz Spurious emission60dB Adjacent channel po

4、werWide : 70dBNarrow : 60dB Noise and hum ratioWide : 40dBNarrow : 36dB Microphone Impedance1K RECEIVER Receiver circuitryDouble conversion superheterodyne Intermediate Frequency (1st / 2nd)38.85MHz / 450kHz Sensitivity (12dB SINAD)Wide : 0.25V or lessNarrow : 0.35V or less Squelch Sensitivity0.126V

5、 or less Adjacent channel selectivityWide : 70dBNarrow : 60dB Intermodulation rejection ratio60dB Spurious and image rejection ratio70dB Audio Output (8,10% distortion) 2W or higher (10% distortion) Audio Output Impedance8 2 DR138 3 ANTSW IFsystem (PLL) CF201(wide) ANT 1st LocalOSC BUFFERAMP U501(4/

6、4) U200 IF AMP Q204 MCF XF200, XF201 MIXER Q205 BPF RF AMP Q206 BPF D210,D211 U505 D/A TV CPU D207, D208 L206, L207 D205,D206 L204, L205 CF200(Narrow) D/ACONVERTER U505 W/NO X 2MULTIPLY Q211 TCXO X200 ANTSW MCF 38.850MHz IF SYSTEM 450KHz CF ANT AF AMP SP TCXO19.200MHz POWER AMP RF AMP PLL VCO MIC MI

7、C AMP RX TX 1st MIX RF AMP 1/2 X2M ULTIPLY 38.4M Hz Q211 CIRCUIT DESCRIPTION Frequency configuration The receiver utilizes double conversion. The first IF is 38.850 MHz and the second IF is 450kHz. The first local oscillator signal is supplied from the PLL circuit. The PLL circuit in the transmitter

8、 generates the necessary frequencies. Fig. 1 shows the frequencies. Fig. 1 Frequency configuration Receiver The receiver is double conversion super heterodyne, designed to operate in the frequency range of 136 to 173.9975MHz. The frequency configuration is shown in Fig. 1. Front - end RF amplifier A

9、n incoming signal from the antenna is applied to an RF amplifier (Q206) after passing through a transmit/receive switch circuit (D210 are off) and a band pass filter (L206, L207 and varactor diodes : D207, D208). After the signal is amplified (Q206), the signal is filtered through a band pass filter

10、 (L204, L205 and varactor diodes: D205, D206) to eliminate unwanted signals before it is passed to the first mixer. The voltage of these diodes are controlled by tracking the CPU (U2) center frequency of the band pass filter. (See Fig. 2.) Fig. 2 Receiver section configuration DR138 4 CIRCUIT DESCRI

11、PTION First Mixer The signal from the RF amplifier is heterodyned with the first local oscillator signal from the PLL frequency synthesizer circuit at the first mixer (Q205) to create a 38.850MHz first intermediate frequency (1st IF) signal. The first IF signal is then fed through one pair of monoli

12、thic crystal filter (MCF : XF200 and XF201) to further remove spurious signals. IF amplifier The first IF signal is amplified by Q204, and then goes to U200 (FM processing IC). The signal is heterodyned again with a second local oscillator signal within U200 to create a 450kHz second IF signal. The

13、second IF signal is then fed through a 450kHz ceramic filter (Wide : CF201, Narrow : CF200) to further eliminate unwanted signals before it is amplified and FM detected in U200. Wide/Narrow Switching Circuit The Wide port and Narrow port (pin 75) of the CPU is used to switch between ceramic filters.

14、 When the Wide port is high, the ceramic filter SW diodes (D200, D201) cause CF201 to turn on to receive a Wide signal. When the Narrow port is low, the ceramic filter SW diodes (D200, D201) cause CF200 to turn on to receive a Narrow signal. (See Fig. 3.) Fig. 3Wide/Narrow Switching Circuit AF Signa

15、l System The detection signal from IF IC (U200) goes to D/A converter (U505) for adjusting the gain and is output to AF filter (U502) for characterizing the signal. It is also amplified by entering compander amplifier (U500). The AF signal output from U500 and the TONE signal are summed up and the r

16、esulting signal goes to the D/A converter (U505). The AFO output level is adjusted by the D/A converter. The signal output from the D/A converter is input to the audio power amplifier (U506). The AF signal from U505 was inputted into (U506).The AF signal from (U506) switches between the internal spe

17、aker and speaker jack (J502) output. (See Fig. 4.) Fig. 4 AF signal system U501, U502 AF Filter U505 D/A CONV. U200 IF IC U505 D/A CONV. AF PA U506 SP U500 COMPANDE IF_IN U200 IF SYSTEM MIX_O D201 D200 CF200 (NARROW) CF201 (WIDE) R205 R206 SW SW Q203 Q201 WIDE/NARROW SW U2 75pin . R207 R208 DR138 5

18、COMPARATOR PHASECHARGE PUMP U205:PLLIC REFOSC I/N I/M PLLDATA LPF Q210 TXVCO Q218 BUFFAMP Q209 19.200MHz Q201,Q219 T/R SW . RXVCO Q217 RFamplifiers AMP P45(CPU) D219,D222 D217,D220 5KHz/6.25KHz 5KHz/6.25KHz CIRCUIT DESCRIPTION Squelch Circuit The detection output from the FM IF IC (U200) passes thro

19、ugh a noise amplifier (U202 B/2) to detect noise. A voltage is applied to the CPU (U2). The CPU controls squelch according to the voltage (SQIN) level. The signal from the RSSI pin of U200 is used for S-meter. The electric field strength of the receive signal can be known before the SQIN voltage is

20、input to the CPU, and the scan stop speed is improved. Fig. 5 Squelch Circuit PLL frequency synthesizer The PLL circuit generates the first local oscillator signal for reception and the RF signal for transmission. PLL The frequency step of the PLL circuit is 5 or 6.25kHz. A 19.200MHz reference oscil

21、lator signal is divided at U205 by a fixed counter to produce the 5 or 6.25kHz reference frequency. The voltage controlled oscillator (VCO) output signal is buffer amplified by Q210, then divided in U205 by a dualmodule programmable counter. The divided signal is compared in phase with the 5 or 6.25

22、kHz reference signal in the phase comparator in U205. The output signal from the phase comparator is filtered through a low-pass filter and passed to the VCO to control the oscillator frequency. (See Fig. 6.) VCO The operating frequency is generated by Q218 in transmit mode and Q217 in receive mode.

23、 The oscillator frequency is controlled by applying the VCO control voltage, obtained from the phase comparator, to the varactor diodes (D219 and D222 in transmit mode and D217 and D220 in receive mode). The TX/RX pin is set high in receive mode causing Q202 and Q219 to turn Q218 off, and turn Q217

24、on. The TX/RX pin is set low in transmit mode. The outputs from Q217 and Q218 are amplified by Q209 and sent to the RF amplifiers. (See Fig. 6.) Fig. 6 PLL circuit UNLOCK Circuit During reception, the RXC signal goes high, the TXC signal goes low, and Q108 turns on. Q101 turns on and a voltage is ap

25、plied to (8R). During transmission, the RXC signal goes low, the TXC signal goes U200 SYSTEM CPU U2NOISE AMP U202 IF SQ RSSI SQIN RSSI DR138 6 D/A U505 M62364F CONVERTER U504 COMPANDER AMP Q5 2SC1623 U500 U504 MIC/IDC U504 SPLA TTER FILTER U505 VCO Q218 2SK1875 NJM2902 MC33111 NJM2902 NJM2902 D/A M6

26、2364F CONVERTER BUFFER Q209 2SC4226 Q207 Q207 2SC4226 U505 D/A M62364F CONVERTER PLL U205 LMX1511TM RFAMP Q210 2SC4226 RFAMP Q220 2SC3357 DRIV ESTAGE Q212 2SK3078A DRIV EAMP Q214 RD07 FINALAMP Q216 RFM70U12D ANT MIC BUFFER CIRCUIT DESCRIPTION high and Q104 turns on. Q102 turns on and a voltage is ap

27、plied to (8T). The CPU in the control unit monitors the PLL (U205) LD signal directly. When the PLL is unlocked during transmission, the PLL LD signal goes low. The CPU detects this signal and makes the TXC signal low. When the TXC signal goes low, no voltage is applied to 8T, and no signal is trans

28、mitted. (See Fig. 7.) Fig. 7 Unlock circuit Transmitter Outline The transmitter circuit produces and amplifies the desired frequency directly. It FM-modulates the carrier signal by means of a varicap diode. Power Amplifier Circuit The transmit output signal from the VCO passes through the transmissi

29、on/reception selection diode (D203) and amplified by Q220, Q212 and Q214. The amplified signal goes to the final amplifier (Q216) through a low-pass filter. The low-pass filter removes unwanted high-frequency harmonic components, and the resulting signal is transmitted through the antenna terminal.

30、(See Fig. 8.) Fig. 8 Transmitter system APC Circuit The automatic transmission power control (APC) circuit detects part of a final amplifier output with a diode (D230, D231) and applies a voltage to U204. U204 compares the APC control voltage (PC) generated by the D/A converter (U505) with the detec

31、tion output voltage. U204 generates the voltage to control Q214 and Q216 and stabilizes transmission output. The APC circuit is configured to protect over current of Q214 and Q216 due to fluctuations of the load SW Q101 SW Q102 SW Q108 SW Q104 U2U205 CPU PLL LD RXC 8C PLL lock :LDH TXC 8R8T . DR138

32、7 CIRCUIT DESCRIPTION at the antenna end and to stabilize transmission output at voltage and temperature variations. (See Fig. 9.) Fig. 9 APC Circuit Control Circuit The CPU carries out the following tasks (See Fig. 10.): 1) Controls the WIDE, NARROW, TX/RX outputs. 2) Controls the display unit. 3)

33、Controls the PLL (U205). 4) Controls the D/A converter (U505) and adjusts the volume, modulation and transmission power. Fig. 10 Control circuit Memory Circuit The transceiver has an 128k-bit EEPROM (U6). The EEPROM contains adjustment data. The CPU (U2) controls the EEPROM through two serial data l

34、ines. (See Fig. 11.) Fig. 11 APC Circuit Display Circuit The CPU (U2) controls the display LCD and LEDs. When power is on, the CPU will use the P07 line to control the LCD illumination backlight LEDs. The brightness function is controlled by the switch Q6 and Q7. The LCD driver (U3) and CPU (U2) com

35、municate through the P85, P86, lines. (See Fig. 12.) CK D/A DT LD LE U505 converter U205 PLL U2 CPU U6 EEPROM U2 CPU RF AMP Q220 DRIVE STAGE Q212 DRIVE AMP Q214 FINAL AMP Q216 ANT ANT SWLPF POWER DET D230,D231 APC CONTROL VR200 U204 14pin U505 PC D210,D211 D203 DR138 8 D/A U505 U2 CPU VCO X200 TCXO

36、U205 PLL 2T/5T/DTMF DCS/CTCSS TCXO MOD VCOMOD U504 FILTER LPF AFWNLPF CPU U503 U2 FILTER BUFFER AMP U501A U2008 DTMF-DET AMP P02 P01 DTMF/2T/5T DCS/CTCSS COMPARATOR CPU U2 LCD U3 LCD COM0COM3 SEG0SEG39driver P85 P86 Q6,Q7 SW 8C D5 P07 CIRCUIT DESCRIPTION Fig. 12 Display circuit Encode CTCSS, DCS dat

37、a of the P31 Line is output from pin 42 of the CPU. The signal passes through a low-pass CR filter and goes to the D/A converter (U505). High-speed data (2T/5T/DTMF) is output from pin 58 of the CPU. The signal passes through a low-pass CR filter, providing TX and SP output audio frequency, and has

38、processed IDC after amplified by a U504(B/4). The signal then passes through a low-pass filter (separation filter) U504 (C/4 and D/4), and filter the parts which are higher than 3kHz frequency, and the signal attained goes into the D/A converter (U505). The D/A converter (U505) adjusts the balance b

39、etween the MOD and CTCSS/DCS levels. Signal of CTCSS/DCS port is summed with MOD and the resulting signal goes to the VCO. This signal is applied to a varicap diode in the VCO for direct FM modulation. (See Fig. 13.) Fig. 13 Encode circuit Decode DCS/CTCSS/DTMF/2T/5T The signal from (AFWN) entering

40、into AF signal and higher audio frequencies output by pin 1 of U501: A are cut by low-pass filter U503 and amplified. then led to pin 51 of CPU. The input signal is compared with the programmed tone frequency code in the CPU. The squelch will open when they match. The signal (DTMF-DET) goes to P02 (

41、pin 52) of CPU (U2). The DTMF/2T/5T input signal from the DTMF-DET goes to compared U2008. The compared signal goes to the CPU for processing and be decoded within the CPU (U2). (See Fig. 14.) Fig. 14 Decode circuit DR138 9 U2 5M CPU Q100 SW Q103 SW U1 AVR Q101 SW Q108 SW Q106 SW VAMVFM Q102 SW Q104

42、 SW Q107 SW Q105 SW 8R 8T U100 AVR U101 AVR 5C 8C P20 P27 P24 P25 FB POWER SW POWER CIRCUIT DESCRIPTION D/A Converter The D/A converter (U505) is used to adjust MO modulation, AF volume, TV voltage, FC reference voltage, and PC POWER CONTROL voltage level. Adjustment values are sent from the CPU as

43、serial data. The D/A converter has a resolution of 256 and the following relationship is valid. Power Supply Circuit When the POWER switch on the display unit is pressed, the power port on the display unit which is connected to CPU port 45 (POWER), goes low, then CPU port 23 (P20) goes high, Q103 tu

44、rns on, SBE SW (Q100) turns on and power (SBE) is supplied to the radio. During receiving, the CPU port 19 (P24) output H level. Q101 and Q108 turn on. and reception circuit is supplied by 8V power supply (8R). When the receiving is at FM, the CUP port 16 (P27) output L level. Q106 turns on and supp

45、lies 8V power supply to FM reception circuit (VFM). During transmitting, CPU port 18 (P25) output H level. Q102 and Q104 turn on. Transmitting circuit output 8V power supply (8T). (See Fig. 15.) Fig. 15 Power supply circuit DR138 10 P PARTS LIST DISPLAY UNIT Ref. NoParts No.Description of itemSize (

46、LxW)(mm)QtySpecification C1-C2SMT CAPACITOR0603210410% 50V C3SMT CAPACITOR0603110210% 50V C4SMT CAPACITOR0603110410% 50V C5SMT CAPACITOR0603110210% 50V C6SMT CAPACITOR0603110410% 50V C7-C20SMT CAPACITOR06031410210% 50V C21SMT CAPACITOR0603110310% 50V C22SMT CAPACITOR0603110410% 50V C23SMT CAPACITOR0

47、603110310% 50V C24SMT CAPACITOR0603110210% 50V C25-C27SMT CAPACITOR0603310310% 50V C28SMT CAPACITOR0603110210% 50V C29SMT CAPACITOR0603110410% 50V C30SMT CAPACITOR0603110310% 50V C31SMT CAPACITOR06031NO USE C32SMT CAPACITOR0603110510% 50V C33-C34SMT CAPACITOR0603247310% 50V C35-C36SMT CAPACITOR06032

48、27310% 50V C37SMT CAPACITOR0603122510% 50V C38SMT CAPACITOR0603110310% 50V C39SMT CAPACITOR0603110210% 50V C40SMT CAPACITOR0603122P5% 50V C41SMT CAPACITOR0603110210% 50V C42SMT CAPACITOR0603120P5% 50V C43-C44SMT CAPACITOR0603210310% 50V C45SMT CAPACITOR0603110210% 50V C46SMT RESISTOR0603168K5% DR138

49、 PARTS LIST Ref. NoParts No.Description of itemSize (LxW)(mm)QtySpecification C48SMT CAPACITOR06031100P5% 50V C49SMT CAPACITOR0603122510% 50V C50SMT CAPACITOR0603110410% 50V C51SMT CAPACITOR060318P0.1P 50V C52SMT CAPACITOR0603110310% 50V C53SMT CAPACITOR0603110210% 50V C54-C55SMT CAPACITOR0603210210% 50V C1000-C1016SMT CAPACITOR060317NO USE E1ELECTRO48122uF25V E2ELECTRO48147uF/10V E3SMT TANTALUM CAPACITORA type122uF20% 10V E4ELECTRO48122uF/10V E5SMT TANTALUM CAPACITORA type122uF20% 10V E1000-E1003SMT TANTALUM CAPACITORA type3NO USE