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1、HF MARINE TRANSCEIVER iM710 SERVICE MANUAL GMDSS Others GEN-23 EUR-21 INTRODUCTION This service manual describes the latest service information for the IC-M710 HF MARINE TRANSCEIVER. DANGER NEVER connect the transceiver to an AC outlet or to a DC power supply that uses more than 16 V. This will ruin
2、 the transceiver. DO NOT expose the transceiver to rain, snow or any liquids. DO NOT reverse the polarities of the power supply when con- necting the transceiver. DO NOT apply an RF signal of more than 20 dBm (100 mW) to the antenna connector. This could damage the transceiv- ers front end. ORDERING
3、 PARTS Be sure to include the following four points when ordering replacement parts: 1. 10-digit order numbers 2. Component part number and name 3. Equipment model name and unit name 4. Quantity required 1160000130 S.ICTD62783AFIC-M710 MAIN UNIT5 pieces 8810008560 ScrewPH M38 SUS ZKIC-M710 Top cover
4、10 pieces Addresses are provided on the inside back cover for your convenience. REPAIR NOTES 1. Make sure a problem is internal before disassembling the transceiver. 2. DO NOT open the transceiver until the transceiver is disconnected from its power source. 3. DO NOT force any of the variable compon
5、ents.Turn them slowly and smoothly. 4. DO NOT short any circuits or electronic parts. An insu- lated tuning tool MUST be used for all adjustments. 5. DO NOT keep power ON for a long time when the trans- ceiver is defective. 6. DO NOT transmit power into a signal generator or a sweep generator. 7. AL
6、WAYS connect a 50 dB to 60 dB attenuator between the transceiver and a deviation meter or spectrum ana- lyzer when using such test equipment. 8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver. To upgrade quality, any electrical or mechanical parts a
7、nd internal circuits are subject to change without notice or obligation. MODELSYMBOL Others Others GMDSS GEN-21 GEN-22 EUR-22 Version IC-M710 GEN EUR TABLE OF CONTENTS SECTION 1SPECIFICATIONS SECTION 2INSIDE VIEWS SECTION 3CIRCUIT DESCRIPTION 3 - 1RECEIVER CIRCUITS . . . . . . . . . . . . . . . . .
8、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1 3 - 2TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 - 3 3 - 3PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . .
9、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 5 3 - 4DC-DC CONVERTER CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 6 3 - 5CPU PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . .
10、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 7 SECTION 4ADJUSTMENT PROCEDURES 4 - 1PREPARATION BEFORE SERVICING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1 4 - 2PLL ADJUSTMENT . . . . . . . . . . . . . . . . . . .
11、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2 4 - 3POWER VOLTAGE ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2 4 - 4TRANSMITTER ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . .
12、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 4 4 - 5RECEIVER ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 8 SECTION 5PARTS LIST SECTION 6MECHANICAL PARTS AND DISASSEMBLY SECTION 7SEMI-CONDUCTOR IN
13、FORMATION SECTION 8BOARD LAYOUTS 8 - 1LOGIC UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1 8 - 2SENSOR1/2 BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14、. . . . . . . . . . . . . . . . 8 - 1 8 - 3MIC BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1 8 - 4VR1 BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15、. . . . . . . . . . . . . . . . . . . . . 8 - 1 8 - 5VR2 BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1 8 - 6MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16、. . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 3 8 - 7PLL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 5 8 - 8PLL-A UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 7 8 - 9PA150W BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 9 8 - 10 FILTER BOARD . . . . . . . . . . . . . . . . . . . . . . . . . .
18、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 11 8 - 11 TERMINAL BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 12 8 - 12 REG BOARD . . . . . . . . . . . . . . . . . . . . . . . . .
19、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 - 13 8 - 13 ALARM BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 - 13 SECTION 9BLOCK DIAGRAM SECTION 10VOLTAGE DIAGRAMS 10 - 1 F
20、RONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1 10 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21、10 - 2 10 - 3 PLL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 5 10 - 4 PLL-A UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22、. . . . . . . . . 10 - 6 10 - 5 PA150W, TERMINAL, FILTER AND REG BOARDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 7 1 - 1 SECTION 1 SPECIFICATIONS GENERAL Frequency coverage : Receive 0.5000 kHz29.9999 MHz Transmit 1.60002.9999 MHz 4.00004.9999 MHz 6.00006.9999 M
23、Hz 8.00008.9999 MHz 12.000013.9999 MHz 16.000017.9999 MHz 18.000019.9999 MHz 22.000022.9999 MHz 25.000027.50000 MHz Mode : J3E (USB), H3E (AM), J2B (AFSK), F1B (FSK), R3E, A1A (CW) (Available modes differ according to versions) Number of channels : 1136 channels (max.) 160 (user programmable), 242 (
24、ITU SSB duplex), 72 (ITU simplex), 662 (ITU FSK duplex) Antenna impedance : 50 (nominal) Usable temperature range : 30C to +60C; 22F to +140F (Specifications are guaranteed with 20C to +40C; 4F to +104F) Frequency stability : 10 Hz (30C to +60C; 22F to +140F) (20 Hz above 15 MHz for GEN-21, GEN-22,
25、EUR-21.) Power supply requirement : 13.6 V DC 15% Negative ground GEN 13.6 V DC 15% Floating ground EUR Current drain (at 13.6 V DC) : Transmit (max. output power) 30 A Receive (max. audio output) 2.5 A GEN 3 A EUR Dimensions : 291.4(W)315(D)116.4(H) mm (projections not included) 111/2(H)1211/32(W)4
26、19/32(D) in Weight : 7.9 kg; 171332 lb Others : 8.1 kg; 172732 lb GMDSS TRANSMITTER Output power (at 13.6 V DC) : 150, 60, 20 W PEP (60, 20 W PEP only above 25 MHz) GEN 150, 60 W PEP (60 W PEP only above 25 MHz) EUR 125 W PEP (85 W PEP MF and 25 MHz bands) GMDSS Spurious emissions : 65 dB GEN 60 dB
27、EUR Carrier suppressions : 40 dB unwanted sideband suppression : 55 dB Microphone impedance : 600 RECEIVER Sensitivity : J3E, R3E, J2B, A1A, F1B 0.5 V (1.800029.9999 MHz) (for 12dB SINAD) 1.0 V (1.60001.7999 MHz) 6.3 V (0.50001.5999 MHz) H3E (for 10dB S/N) 3.2 V (1.800029.9999 MHz) 6.3 V (1.60001.79
28、99 MHz) 32 V (0.50001.5999 MHz) Spurious response rejection : 70 dB (1.600029.9999 MHz) Audio output power : 4.5 W (at 10% distortion with a 4 load) Audio impedance : 4 to 8 Clarity variable range : 150 Hz All stated specifications are subject to change without notice or obligation. SECTION 2INSIDE
29、VIEWS 2 - 1 PA150W, FILTER AND TERMINAL BOARDS TERMINAL board Fuse (F7001) Drive amplifiers (Q4001, Q4002: 2SC3133) Thermal switches S4001: OHD-3 110M S4002: OHD-3 50M Power amplifiers (Q4003, Q4004: 2SC2904) PA150W board REG board EUR-21, EUR-22 only FILTER board Power detector circuit MAIN, PLL AN
30、D LOGIC UNITS RF filter circuit Noise blanker circuit 2nd mixer circuit 1st IF amplifier (Q8: 3SK131) 1st IF filter (FI1: FL-120) PLL IC (IC3005: LC7153M) DDS IC (IC3001: SC-1246A) PLL/-A unit ALARM board except GEN-21 MAIN unit Squelch circuit Demodulator circuit (IC10: NJM1496V) BFO DDS IC (IC3002
31、: SC-1287) Reference oscillator (X3001: CR-282) GEN-21, GEN-22, EUR-21 only LOGIC unit 3-1 RECEIVER CIRCUITS 3-1-1 RF FILTER CIRCUIT (MAIN UNIT) Received signals from the antenna connector pass through the transmit/receive switching relay (FILTER board RL4317) and are then applied to the MAIN unit v
32、ia J2. The signals pass through the protection relay (RL2), 1.6 MHz cut off high-pass filter (L2L4, C4C8, C629) and are then applied to one of nine bandpass filters (including one low-pass filter for below 2.0 MHz). These filters are selected by the filter control signals (B0B8) as described in the
33、table below. The filtered signals pass through the 30 MHz cut-off low- pass filter (L71, L72, C130C134, C618), and are then applied to the 1st mixer circuit (Q6, Q7). RF FILTERS USED 3-1-2 1ST MIXER AND IF CIRCUITS (MAIN UNIT) The 1st mixer circuit converts the received signals into a fixed frequenc
34、y, 69.0115 MHz 1st IF signal using the PLL output frequency. By changing the PLL frequency, only the desired frequency is picked up at the pair of crystal filters (FI1a, FI1b) at the next stage. The IF amplifier (Q8) and resonator circuits are designed between the filter pair. The PLL output signal
35、(1LO) enters the MAIN unit via J3 and is amplified at the 1st LO ampli- fier (Q5) and then applied to the 1st mixer (Q6, Q7) 3-1-3 2ND MIXER AND IF CIRCUITS (MAIN UNIT) The 1st IF signal from the crystal filter (FI1b) is converted again into a 9.0115 MHz 2nd IF signal at the 2nd mixer circuit (D52,
36、L66, L67). The 60 MHz 2nd local signal (2LO) from the PLL unit enters the MAIN unit via J4 to be applied to the 2nd mixer. The 2nd IF signal is passed through the noise blanker gate (D15, D16) and amplified at the 2nd IF amplifier (Q16) and then applied to one of the 9 MHz IF filters as described be
37、low. The passed signal is amplified at the two stage 2nd IF amplifiers (Q32, Q33) and is applied to a demodulator circuit (D39 for H3E or IC10 for J3E and others). 2ND IF FILTERS USED 3-1-4 NOISE BLANKER CIRCUIT (MAIN UNIT) The noise blanker circuit cuts off the IF circuit line at the moment of rece
38、iving a pulse-type noise. A portion of the 2nd IF signal between resonator circuits (L83, L84 after stage of the 2nd mixer, D52) is amplified at the noise amplifiers (Q9, IC8, Q11). The signal is then detected at the noise detector (D17) to convert the noise components to DC voltages. The signals ar
39、e then applied to the noise blanker switch (Q13, Q14). At the moment the detected voltage exceeds the Q13s threshold level, Q14 outputs a blanking signal to close the noise blanker gate (D15, D16) by applying reverse-biased voltage. Q15 turns the noise blanker circuit ON and OFF. 3 - 1 SECTION 3 CIR
40、CUIT DESCRIPTION LPF or BPF 0.529.999 MHz 1st mixer Q6, Q7 1st LO: 69.511599.0115 MHz Fl1a/Fl1b Crystal filter Crystal filter 69.0115 MHz 2nd mixer D52 2nd LO: 60.0 MHz Fl2 or Fl3/Fl4 9.0115 MHz Other modes H3E Detector D39 Demodulator IC10 Audio output BFO J3E, J2B, R3E, FSK: FSK narrow, J2B narrow
41、: A1A: 9.013 MHz 9.0123 MHz 9.0116 MHz Frequency (MHz) 0.51.999 22.999 34.999 56.999 79.999 Frequency (MHz) 1013.999 1417.999 1823.999 2429.999 Control signal B5 B6 B7 B8 Control signal B0 B1 B2 B3 B4 Entrance coil L49 L8 L13 L18 L23 Entrance coil L28 L33 L38 L43 MODE J3E, R3E, FSK H3E FSK narrow, A
42、1A narrow Used filter FI2 FI3/FI4 Optional narrow filter* Control signal SEL8: low, H3E8: low SEL8: low, H3E8: high SEL8: high, H3E8: low RECEIVE FREQUENCY CONSTRUCTION *Built-in to the GMDSS versions 3 - 2 The detected voltage is also applied to the noise blanker AGC circuit (Q12, Q10) and is then
43、fed back to the noise amplifier (IC8) as a bias voltage. The noise AGC circuit prevents closure of the noise blanker gate for long periods by non-pulse-type noise. The time constant of the noise blanker AGC circuit is determined by R58 and C114. 3-1-5 DEMODULATOR CIRCUIT (MAN UNIT) This circuit mixe
44、s the 2nd IF and BFO signals to pick up the AF components (except H3E mode). The 2nd IF signal from the 2nd IF amplifier (Q33) is applied to the balanced mixer (IC10, pin 1). The 9.01169.0130 MHz BFO signal from the PLL unit is also applied to IC10 (pin 10). AF sig- nals are output from pin 12 and a
45、re then applied to the AF circuits. 3-1-6 H3E DETECTOR CIRCUIT (MAIN UNIT) The 2nd IF signal from the 2nd IF amplifier (Q33) is applied to the AM detector circuit (D39) to be demodulated into AF signals. The detected signals are amplified at the buffer amplifier (Q45), and are then applied to the AF
46、 circuits. 3-1-7 AGC CIRCUIT (MAIN UNIT) The AGC (Automatic Gain Control) circuit reduces IF ampli- fier gain to prevent the receiver circuit from distorting and to keep the audio output at a constant level. A portion of the IF signals from the 2nd IF amplifier (Q33) is detected at the AGC detector
47、circuit (D31) and is then applied to the AGC amplifier (Q41) to control the AGC time constant line. The reference voltage of the AGC line is con- trolled by the “RFG” line which comes from the CPU for the RF gain setting. When receiving a strong signal, the detected voltage increases and the voltage
48、 of the AGC line is decreased by the AGC amplifier (Q41) via the 5 V voltage line. The AGC line is used for the bias voltage of the IF amplifiers (Q8, Q16, Q32, Q33), so that these amplifiers reduce gain. When the strong signal disappears, the AGC line voltage is released by C245/R268 and C670/R813.
49、 The AGC switch (Q42, D38) turns the AGC circuit OFF when the AGC OFF function activates. The AGC-fast switch (Q131) sets the AGC line as fast-release during scanning, A1A mode selection and DSC operation. 3-1-8 S-METER CIRCUIT (MAIN UNIT) The S-meter indicates the AGC level on the display, since the AGC level varies with the received signal strength. The AGC bias voltage (AGC time constant line) from the AGC amplifier (Q41) is inverted and amplified at the meter amplifier (IC19b). The amplified signal is ap
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