FT817.pdf

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1、1 2003 VERTEX STANDARD CO., LTD. Printed in Japan. (E137790A) Technical Supplement FT-817 HF / VHF / UHF All Mode Transceiver Introduction This manual provides technical information necessary for servicing the Yaesu FT-817 HF 10.7 MHz (WFM) 2nd: 455 kHz Sensitivity:SSB/CWAMFM 100 kHz-500 kHz 500 kHz

2、-1.8 MHz32 V 1.8 MHz-28 MHz0.25 V2 V 28 MHz-30 MHz0.25 V2 V0.5 V 50 MHz-54 MHz0.2 V2 V0.32 V 144/430 MHz0.125 V0.2 V (IPO, ATT off, SSB/CW/AM = 10 dB S/N, FM = 12 dB SINAD) Squelch Sensitivity:SSB/CW/AMFM 1.8 MHz-28 MHz2.5 V 28 MHz-30 MHz2.5 V0.32 V 50 MHz-54 MHz1 V0.2 V 144/430 MHz0.5 V0.16 V (IPO,

3、 ATT off) Image Rejection:HF/50 MHz: 70 dB 144/430 MHz: 60 dB IF Rejection:60 dB Selectivity (6/60 dB): SSB/CW: 2.2 kHz/4.5 kHz AM: 6 kHz/20 kHz FM: 15 kHz/30 kHz FM-N: 9 kHz/25 kHz SSB (optional YF-122S installed): 2.3 kHz/4.7 kHz (66 dB) CW (optional YF-122C installed): 500 Hz/2.0 kHz AF Output: 1

4、.0 W (8 Ohms, 10% THD or less) AF Output Impedance:4-16 Ohms Specifications are subject to change without notice, and are guaranteed within amateur bands only. Frequency ranges vary according to transceiver version; check with your dealer. Downloaded by? Amateur Radio Directory? ? www.hamdirectory.i

5、nfo 3 Exploded View it then passes through a filter (R1308 and C1293). The signal next passes through a de-emphasis cir- cuit which consists of R1256 and C1286. The squelch circuit selectively amplifies the noise com- ponent of the demodulator output using the filter ampli- fier inside the FM IC and

6、 the active band-pass filter con- sisting of an externally attached resistor and capacitor. This circuit uses a signal detected by D1065 (DA221). SSB/CW Demodulator Circuit The 2nd IF signal is applied to the SSB demodulator Q1055 (SN16913) on the MAIN Unit, which produces audio by applying a carrie

7、r signal from the CAR-DDS IC (Q1031). Similarly, the CW signal is demodulated using a carrier signal which is offset by the Pitch frequency. The demodulated SSB and CW signals are each stripped of high-frequency components by an active low-pass fil- ter which consists of op-amp IC Q1093-1 (NJM2902V)

8、. Then, they enter the VR Unit via J1008. AM Demodulator Circuit The 2nd IF signal from the IF Unit is applied to diode D1060 (BAS316) for AM demodulation . The output from the detector passes through analog switch Q1049 (BU4066BF). Then, it enters the VR Unit via J1008. Audio Amplifier Circuit The

9、demodulated signal that is selected by one of analog switches IC Q1057 (according to the reception mode) passes through the audio amplifier IC Q1094 (NJM2902V), volume control VR4901, and IC Q1070 (TDA7233D) to drive the internal or external speaker with a maximum output of approximately 1.0 Watt. T

10、ransmit Signal Circuitry Microphone Amplifier Circuit The audio signal from microphone jack J1014 on the MAIN Unit is amplified by transistor Q1092 (2SC4154E) on the MAIN Unit, and then is applied to electronic vol- ume IC Q1071 (M62364EP), which is controlled via the User Menu (Item #46: SSB MIC).

11、The output (audio signal) from the electronic volume IC is amplified by Q1096 (NJM2902V) and fed to balanced modulator IC Q1087 (SN16913) through the low-pass fil- ter IC Q1096 (NJM2902V). During FM transmission, the audio signal is adjusted via the User Menu (Item# 29 : FM MIC) . The audio signal t

12、hat has passed through the pre-emphasis circuit (C2201 and R2228 on the MAIN Unit) may be mixed with a tone signal from CPU IC Q4004, and is then amplified and lim- ited by op-amp IC Q1095-4 (NJM2902V) of the IDC cir- cuit. The audio then passes through the splatter filter (sec- ondary active low-pa

13、ss filter) formed by op-amp IC Q1095-1 (NJM2902V), R1321, and R1322, plus C1344, and is then fed to the frequency-modulator circuit on the MAIN Unit through R1183 and R1477 for setting of the frequency deviation. SSB Modulator Circuit The carrier signal appropriate to the transmitting mode (LSB or U

14、SB) is applied from the CAR-DDS Unit to bal- anced modulator IC Q1087 (SN16913) on the MAIN Unit, and is modulated by microphone audio. The balanced modulator produces the upper and lower side bands and carrier signal. The carrier and audio sig- nal are suppressed and the carrier balance is adjusted

15、 by VR1001. As a result, the output signal obtained is a DSB signal with a carrier suppression of 30 dB or more (addi- tional carrier suppression is supplied by the SSB filter). The DSB modulated signal (1st IF signal: 455 kHz) then passes through ceramic filter CF1004 (CFJ455K14) or the optional me

16、chanical filter U1003 on the MAIN Unit, strip- ping residual carrier and the undesired sideband; the sig- nal then passes as an SSB signal through buffer-amplifier Q1040 (BB301C). 9 Circuit Description AM Modulator Circuit As in the SSB modulator circuit, a carrier signal from the CAR-DDS Unit and a

17、n audio signal from the microphone are applied to balanced modulator IC Q1087 (SN16913) on the MAIN Unit. The control signal from MODE SW IC Q1021 (BU4094BCFV) on the MAIN Unit causes a voltage labeled AM 5V to be sent from transistor Q1079 (2SC4154E). This voltage is applied to IC Q1087 via D1077 (

18、BAS316), caus- ing the balanced modulator to lose balance. The restored carrier signal and modulated signal are then fed to the Tx mixer via ceramic filter CF1004 (CFJ455K14) on the MAIN Unit. Frequency Modulation Circuit The FM circuit uses a voltage controlled crystal oscillator (VCXO) which consi

19、sts mainly of Q1033 (2SC4400), X1001 on the MAIN-Unit, varactor diode D1056 (HVC362), and T1018. The VCXO has a center frequency of 22.7785MHz. The FM signal is produced by applying a signal from the FM microphone amplifier circuit to varactor diode D1056 and varying the crystal oscillator load capa

20、city in propor- tion to the signal voltage. CW (A1) Signal Generator Circuit When the transmitting mode is CW (A1), the control sig- nal from D-A converter IC Q1077 (M62353GP) on the MAIN Unit creates a CW 5V voltage. The voltage is applied to balanced modulator IC Q1087 via D1071, pro- viding a car

21、rier from the balanced modulator for the in- put to the transmit signal circuit of the MAIN Unit. 1st IF Circuit/1st Mixer Circuit The 455 kHz 1st IF signal from the modulator circuit is band-limited by the MAIN Units ceramic (CF1004) or optional mechanical filter U1003 (XF5201 or XF5301) ac- cordin

22、g to the selected mode (CW, SSB, or AM). It is then buffer-amplified by FET Q1040 (BB301C) and fed to 1st mixer IC Q1038 (SN16913). The IF Units double balanced mixer IC Q1038 (DBM) is used as the 1st mixer. A local signal (67.875MHz) is pro- duced by tripling the Reference frequency at Q1047 (2SC41

23、54E), and this local signal is fed to the local port of the doubly-balanced mixer IC, where it is mixed with the 455 kHz 1st IF signal to produce a 68.33MHz 2nd IF signal. 2nd IF Circuit/2nd Mixer Circuit The 2nd IF signal passes through crystal filter XF1001 and then is fed to the 2nd mixer circuit

24、. The 2nd mixer consists of the MAIN Units D1049 (HSB88WS). The 2nd local signal (68.430-538.330MHz) from the PLL Unit is applied to the gates of each FET in the 2nd mixer. High-Frequency Transmit Preamplifier Circuit The transmit signal is passed through a low-pass filter (1.8- 29.7 MHz), a high-pa

25、ss filter (50-54 MHz), a band-pass filter (144-146 MHz), or a band-pass filter (430-440 MHz) and then is amplified by Q1001 (UPC2710), and passed onward to the PA Unit via J1002. Power Amplifier Circuit The transmit signal from the MAIN Unit arrives at con- nector J3001 on the PA Unit. The transmit

26、signal (1.8 MHz to 430 MHz) delivered to the PA Unit is amplified by pre-driver Q3001 (2SC3357), driver Q3002 (2SK5296) and final amplifiers Q5401/Q5402 (2SK2975). Low-Pass Filter (LPF) Circuit The transmission signal from the power amplifier circuit is passed through a low-pass filter which consist

27、 mainly of RL3001-RL3015, RL3017, and corresponding inductor and capacitor networks. The LPF is a 5th or 7th-order Chebyschev type filter, utilizing nine different sections for the various amateur bands at 1.8 430 MHz. The low-pass filtered transmission signal is fed to the FRONT ANT connector (J000

28、1) or REAR ANT connector (J0002) through the triplexer and directional coupler. The directional coupler samples a part of the transmis- sion power to detect forward power and reflected power. A DC voltage corresponding to the relative forward/re- flected power is produced by D3032/D3033 (both MA716,

29、 1.8 to 54 MHz), D3009/D3017 (both MA716, 144 to 148 MHz), or D3007/D3008 (both MA716, 430 to 450 MHz) , and is used for automatic level control (ALC). ALC Circuit The output from the directional coupler is routed from connector J3004 and applied to the ALC circuit via con- nector J1003 on the MAIN

30、Unit. The ALC circuit consists of an op-amplifier circuit for amplifying the forward and reflected voltage, a time-con- 10 Circuit Description stant ALC amplifier, and a transmit signal control circuit on the MAIN Unit. The forward voltage from connector J1003 on the MAIN Unit is added with a DC con

31、trol voltage and is then ap- plied to op-amp IC Q1097 (NJM2902V). The reflected voltage is added with a DC control voltage and is then applied to op-amp IC Q1098 (NJM2904V), In the event of high SWR conditions (SWR of 3:1 or more), transmitter output is reduced and a High SWR warn- ing appears, thus

32、 protecting the PA Unit from potential damage and alerting the operator to the high SWR situa- tion. The ALC amplifier amplifies the forward DC output via transistor Q1019 (2SC4154). This output then passes through a fast-attack, slow-delay RC time-constant circuit which consists of R1097 and C1113

33、for the input to the Tx signal control circuit on the MAIN Unit. The TX control circuit adjusts the IF amplifier gain via gate 2 of FET Q1007 (BB304C) of the 68.33 MHz IF ampli- fier circuit to prevent the power output from exceeding the preset level. PLL Frequency Synthesizer The PLL Frequency Synt

34、hesizer consists mainly of a mas- ter reference oscillator circuit, 2nd local oscillator circuit, plus the PLL IC, CAR-DDS, and REF-DDS units, which digitally synthesize carrier outputs, and a PLL circuit which contains a voltage controlled oscillator (VCO). Master Reference Oscillator Circuit The m

35、aster reference oscillator uses a crystal oscillator (oscillation frequency: 22.625MHz) composed of Q5001 (2SC4400-4), X5001, TC5001, C5001, R5005, and associated components. The reference oscillator signal passes through buffer amplifier Q5002 (2SC4400-4), C5004, C5007, R5003, R5004, R5007, and is

36、then fed to the MAIN Unit via J5002. CAR-DDS Circuit /REF-DDS Circuit DDS ICs Q1031 (AD9835BRU) and Q2016 (AD9850BAS) each contain a shift register, selector, phase accumulator, and ROM. The reference oscillation frequency (22.625MHz) that is delivered to each of the DDS Units is applied to each DDS

37、 IC after amplification by transistors Q1028/Q2020 (both 2SC4400-4). The DDS outputs contain digital amplitude data corre- sponding to serial frequency data from CPU IC Q4004 of the PANEL Unit. The DDS frequency range is 453.5 466.5 kHz (cf = 455.0 kHz) for the CAR-DDS, and 7.2-8.0 MHz for the REF D

38、DS. 2nd Local Oscillator Circuit The 2nd L.O. circuit is a Hartley-type overtone oscillator circuit (frequency: 67.875 MHz) composed of Q1047 (2SC4400) on the MAIN Unit. 1st Local Oscillator Circuit VCO output is buffer-amplified by Q2008 (2SC4400), Q2011, Q2014, and Q2016(all 2SC5374) and passes th

39、rough a low-pass filter. It is then fed to the Tx/Rx fre- quency mixer circuitry on the MAIN Unit. PLL Circuit The PLL circuit is a frequency mixing type composed of a VCO, mixer, PLL IC, and loop filter. The VCO consists of five circuits (VCO1, VCO2, VCO3, VCO4, and VCO5), with a frequency range of

40、 68.430- 538.330 MHz divided into five bands, allocated to the five VCO circuits. VCO1-VCO5 consist mainly of FETs Q2004, Q2005, and Q2006 (all 2SK210GR), transistors Q2009, Q2010 (both 2SC5374), diodes D2001-D2006 (all HVC362), D2007 (1SV282), D2008 (1SV281), and D2009 (1SV286), and coils T2001-T20

41、03, L2010, and L2011. The VCO switching signal from connector J2002 is used to drive switching transistors Q2001, Q2002, Q2003, Q2012, and Q2013 (all DTC124EU) to switch the source terminal of the oscillator FET. The 68.430-538.330 MHz VCO signal is fed to mixer D1047 (GN2011-Q). The REF-DDS signal

42、(7.2-8.0 MHz) is fed to PLL IC Q2022 (FQ7925) after it passes through a LPF composed of C2064, C2067, C2069, C2071, C2075, L2014, L2015, and L2016 , and buffer amplifier Q2019 (2SC4400-4) . The phase of the reference frequency and that of the sig- nal input to PLL IC are compared, and a signal whose

43、 pulse corresponds to the phase difference is produced. The VCO frequency is controlled by a first lag filter which consists of R2057, R2065, R2062, and C2090 and a second- ary lag filter composed of C2085, C2088, and R2053. 11 Circuit Description Control Circuitry Microprocessor Circuit The micropr

44、ocessor circuit, which is composed of CPU IC Q4004 (HD64F2345) and EEPROM IC Q4004 (ATC64N- 10S1), performs various types of processing, such as con- trol signals, serial I/O, A/D conversion, dial counter cir- cuit control, key input, and display functions. The EEPROM memorizes various parameters an

45、d settings (transmission frequency range, transmission output con- trol) and carrier points according to the transceiver ver- sion and the contents of memory channels. Reset Circuit The reset circuit consists mainly of PANEL Unit ICs Q4014 (PST3445), Q4015 (2SC4154E), Q4011 (2SA1602A), Q4016 (2SC415

46、4E), and Q4010 (2SA1602A), and associated ca- pacitors and resistors. This circuit controls the power- down input port, CPU reset input, keyer CPU, and re- lated circuits. Dial Counter Circuit The dial counter circuit consists of Main Dial and SEL (Se- lector) Knob. This circuit detects a two-phase

47、pulse hav- ing a phase difference of 90 degrees and delivers it to CPU IC Q4006 . Serial Data Communication Circuit The Serial Data Communication Circuit consists of ICs Q4008, Q4009, Q4010, etc. on the PANEL-Unit. These ICs distribute a set of serial data (Data/Clock/Strobe) gener- ated by CPU to v

48、arious devices, such as CAR-DDS, REF- DDS, E.VOL, D/A, or Shift-Register for controlling ana- log switching , band switching, VCO selection, etc. Serial data communication is clock synchronous for the above purposes, whereas the serial data is transferred to an asyn- chronous signal for the CAT syst

49、em for external computer control of the transceiver). Various types of data, such as operating frequency, mode, and display data, are processed by CPU IC Q4004 . The CAT (external computer control) signals are converted to RS232 interface standard levels by the optional CAT Interface Cable (CT-62). Key Matrix Circuit The key matrix circuit consists of PANEL Unit diodes D4001-D4003 and D4006 (all IMN10) and the panel key switches arranged on the matrix. When a key is pressed, this circuit reads the input data for processing by the CP