FT857.pdf

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1、1 Introduction This manual provides technical information necessary for servicing the FT-857 HF/VHF/UHF Ultra-Compact Transceiver. Servicing this equipment requires expertise in handling surface-mount chip components. Attempts by non-qualified per- sons to service this equipment may result in perman

2、ent damage not covered by the warranty, and may be illegal in some countries. Two PCB layout diagrams are provided for each double-sided circuit board in the Transceiver. Each side of is referred to by the type of the majority of components installed on that side (“leaded” or “chip-only”). In most c

3、ases one side has only chip components, and the other has either a mixture of both chip and leaded components (trimmers, coils, electrolytic capacitors, ICs, etc.), or leaded components only. While we believe the technical information in this manual to be correct, VERTEX STANDARD assumes no liabilit

4、y for damage that may occur as a result of typographical or other errors that may be present. Your cooperation in pointing out any inconsistencies in the technical information would be appreciated. 2003 VERTEX STANDARD CO., LTD.EH007M90A Technical Supplement Specifications . 2 Exploded View 10.7 MHz

5、 (WFM) 2nd: 455 kHz Sensitivity:SSB/CWAMFM 100 kHz-1.8 MHz32 V 1.8 MHz-28 MHz0.2 V2 V 28 MHz-30 MHz0.2 V2 V0.5 V 50 MHz-54 MHz0.125 V1 V0.2 V 144/430 MHz0.125 V0.2 V (SSB/CW/AM = 10 dB S/N, FM = 12 dB SINAD) Squelch Sensitivity:SSB/CW/AMFM 100 kHz-1.8 MHz 1.8 MHz-28 MHz2.5 V 28 MHz-30 MHz2.5 V0.32 V

6、 50 MHz-54 MHz1 V0.16 V 144/430 MHz0.5 V0.16 V Image Rejection:HF/50 MHz: 70 dB, 144/430 MHz: 60 dB IF Rejection:60 dB Selectivity (6/60 dB):SSB/CW: 2.2 kHz/4.5 kHz AM: 6 kHz/20 kHz FM: 15 kHz/30 kHz FM-N: 9 kHz/25 kHz SSB (optional YF-122S installed): 2.3 kHz/4.7 kHz (66 dB) CW (option YF-122C inst

7、alled): 500 Hz/2.0 kHz CW (option YF-122CN installed): 300 Hz/1.0 kHz AF Output:2.5 W (4 Ohms, 10% THD or less) AF Output Impedance:4-16 Ohms Specifications are subject to change without notice, and are guaranteed within the amateur bands only. 4 Note 5 Exploded View (2) a “through” circuit enabled

8、via diodes D1011 and D1012 (both DAP236U); or (3) RF amplifier Q1025 (2SC5374). Received 430 MHz signals, after passing through a high- pass filter composed of L3058, L3069, C3250, C3251, C3253, C3258, and C3298, are passed through low-pass filter composed of L3043, L3044, C3209, C3211, C3214, C3215

9、, C3246, and C3255, and through a directional cou- pler, to the UHF T/R switch circuit composed of diode switch D3019/D3022 (both UM9957F), D3023, and D3039 (both HSU277). Then the signals are fed to the 1st Mixer Q1128 via the RF-AMP Q1026 (2SK2685). Received 145 MHz signals, after passing through

10、a high- pass filter composed of L3055, L3056, L3067, C3248, C3249, C3252, and C3254, are passed through a low-pass filter composed of L3040, L3041, C3204, C3205, C3210, C3213, and C3216, and a directional coupler, to the VHF T/R switch circuit, composed of diode switch D3018/ D3021 (both UM9957F). T

11、hen the signals are fed to 1st Mixer Q1128 via the RF-AMP, Q1024 (BB304CDW). Received 76-108 MHz signals, after passing through a high-pass filter composed of L3055, L3056, L3067, C3248, C3249, C3252, and C3254, are passed through low-pass filter composed of L3040, L3041, C3204, C3205, C3210, C3213,

12、 and C3216, and a directional coupler, to the T/R switch circuit, composed of diode switch D3018/ D3021 (both UM9957F). Then it is fed to the Wide-FM IF IC Q1058 (CXA1611N) on the MAIN Unit. 1st Mixer Circuit/1st IF Circuit The 1st mixer on the MAIN Unit consists of quad MOS FET Q1128 (SPN5001), whe

13、re the receiving signal is mixed with the 1st local signal (68.430-538.330 MHz) from the PLL Unit. The resulting output signal (68.33 MHz) passes through monolithic crystal filter (MCF) XF1001 (MF68Q, BW: 6.0 kHz) to obtain the 1st IF signalwith a center frequency of 68.33 MHz. The IF signal passes

14、through the 1st IF amplifier Q1073 (BB305CEW) to the 2nd Mixer, Q1083 and Q1084 (both 2SK302Y). 2nd Mixer Circuit/2nd IF Circuit The 2nd Mixer consists of FETs Q1083 and Q1084 (both 2SK302Y) on the MAIN Unit, where the 1st IF signal is mixed with the 2nd local signal (67.875 MHz). The re- sulting ou

15、tput signal (455 kHz) is applied to the 2nd IF filter which is matched to the receiving mode: either CF1004, CF1005 or an optional mechanical filter. Noise Blanker Circuit A portion of the 2nd IF signal is amplified by Noise Blanker Amplifiers Q1075 and Q1079 (both BB305CEW) on the MAIN Unit, and th

16、en rectified by D1064 (1SS372). This output is applied to the Noise Blanker Controllers, Q1093 (2SC4154E) and Q1099 (2SA1602A), which a yield Blanking signal according to the timing of the incoming noise pulses. Then Blank- ing signal controls the Noise Blanker Gate D1066 (BAS316), to slice out the

17、impulse noise from the signal. AGC Circuit The AGC circuit consists of D1061 (1SS372), transistor Q1090 (2SC4154E), and associated parts on the MAIN Unit. Output from the AGC circuit is fed back to the IF AGC circuit that controls the gain of the IF amplifier FETs. FM IF Circuit/FM Demodulator Circu

18、it On FM, the 2nd IF signal passes through the buffer am- plifier Q1094 (2SC4154E) and 2nd IF filters (CF1002 and CF1003) to the FM IF IC Q1080 (TA31135FN) which contains a mixer, limiter amplifier, filter amplifier, squelch trigger, and demodulator. The demodulated audio signal at Q1080 passes thro

19、ugh a low-pass filter (R1339 and C1282) and a de-emphasis circuit (R1303 and C1345), then proceeds to the Audio Amplifier Circuit. The squelch circuit selectively amplifies the noise com- ponent of the demodulator output using the filter ampli- fier inside the FM IF IC and an active band-pass filter

20、 consisting of an externally attached resistor and capaci- tor. Signal detection is performed by D1057 (DA221). SSB/CW Demodulator Circuit The 2nd IF SSB/CW signal passes through buffer ampli- fiers Q1088 and Q1081 (both BB305CEW) to the SSB balanced demodulator Q1071 (SA602AD) which pro- duces audi

21、o by applying the carrier signal from the CAR- DDS IC Q1062 (AD9835BRU). The demodulated audio signal is stripped of high-frequency components by an active low-pass filter, op-amp IC Q1120 (NJM2902V), then is applied to the Audio Amplifier Circuit. AM Demodulator Circuit The 2nd IF AM signal passes

22、through buffer amplifiers Q1088 and Q1081 (both BB305CEW) to the AM demodu- lator D1055 (BAS316), yielding demodulated audio sig- nal which is applied to the Audio Amplifier Circuit. Audio Amplifier Circuit The demodulated audio signal is passed through AF pre- amplifier Q1119 (NJM2902V) and electro

23、nic volume con- trol IC Q1087 (M62364EP) to the AF Amplifier IC Q1105 (TDA2003H) which drives the internal or external speaker to a maximum output of approximately 2.5 Watts. 10 Circuit Description Transmit Signal Circuitry Microphone Amplifier Circuit The audio signal from microphone jack is amplif

24、ied by audio amplifier Q1109 (2SC4154E) on the MAIN Unit, and then is applied to electronic volume control IC Q1087 (M62364EP), the level of which is set via the User Menu. SSB Modulator Circuit The output (audio signal) from the electronic volume con- trol IC is passed through audio amplifier Q1118

25、 (NJM2902V) to the balanced modulator IC Q1071 (SA602AD) which produces a Double Sideband (DSB) signal by applying the carrier signal from the CAR-DDS IC Q1062 (AD9835BRU). The DSB modulated signal (455 kHz) is fed to ceramic filter CF1004 (or the optional mechanical filter) which strips residual ca

26、rrier and the undesired sideband, resulting in a Single Sideband (SSB) signal. AM Modulator Circuit As in the SSB modulator circuit, a carrier signal appro- priate to the transmitting mode (AM) from the CAR-DDS Unit and an audio signal from the microphone are applied to balanced modulator IC Q1071 (

27、SA602AD). The con- trol signal from Mode Switch IC Q1003 (BU4094BCFV) causes a voltage (“AM 5V”) to be sent from transistor Q1058 (2SC4154E). This voltage is applied to IC Q1071 via D1059 (BAS316), causing the balanced modulator to lose balance. The restored carrier signal and modulated signal are t

28、hen fed to the TX mixer via ceramic filter CF1004. FM Modulator Circuit The output (audio signal) from the electronic volume con- trol IC is passed through the pre-emphasis circuit which consists capacitor C1492 and resistors R1493 and R1477, and Instantaneous Deviation Control Q1119 (NJM2902V), to

29、the splatter filter which consists Q1119, capacitor C1430, and resistors R1358 and R1384. The fil- tered audio signal is applied to the FM modulator circuit, which produces the FM signal. The FM modulator circuit uses a voltage controlled crystal oscillator (VCXO) which consists Q1055 (2SC4400), D10

30、46 (1SV229), and X1002 (22.7767 MHz). 1st IF Circuit/1st Mixer Circuit The modulated SSB/AM signal is applied to the 2nd Mixer Q1082 (SA602AD), which produces the 68.33 MHz 2nd IF signal utilizing the 2nd local signal (68.875 MHz). The 2nd IF signal is fed through the 2nd IF filter XF1004 which stri

31、ps away unwanted mixer products, then passes through the 2nd IF amplifier Q1061 (BB304CDW) to the double balanced mixer D1034 (HSB88WS) which produces the transmit frequency by applying the local signal (68.430- 538.330 MHz) from the PLL Unit. The transmit signal is passed through a low-pass filter

32、(1.8-29.7 MHz), a high- pass filter (50-54 MHz), a band-pass filter (144-146 MHz), or a band-pass filter (430-450 MHz) which consists of various inductors and capacitors. The filtered transmit sig- nal is amplified by Q1017 (2SC3357), Q1011 (2SK2596), Q1006/Q1007 (2SK2973), and Q1001/ Q1002 (2SK2975

33、), and is applied to the Power Ampli- fier: Q3022/Q3023 (2SC5125: HF/50 MHz) or Q3024 (2SC3102: 144/430 MHz). ALC Circuit The output from the directional coupler is routed from connector J3001 and applied to the ALC circuit via con- nector J1001 on the MAIN Unit. The ALC circuit consists of an op-am

34、p circuit for ampli- fying the forward and reflected voltage, a time-constant ALC amplifier, and a transmit signal control circuit on the MAIN Unit. The forward voltage from connector J1001 on the MAIN Unit is added with a DC control volt- age and is then applied to op-amp IC Q1111 (NJM2902V). The r

35、eflected voltage is added with a DC control voltage and is then applied to op-amp IC Q1112 (NJM2904V). In the event of high SWR conditions (SWR 3:1 or more), transmitter output is reduced, thus protecting the PA Unit from potential damage; a “HI SWR” indication also ap- pears on the LCD, alerting th

36、e user to an antenna prob- lem. The ALC amplifier magnifies the forward wave output via transistor Q1009 (2SC4154). This output then passes through a fast-attack, slow-delay RC time-constant cir- cuit, which consists of R1051 and C1051, for input to the TX signal control circuit on the MAIN Unit. Th

37、e TX con- trol circuit adjusts the IF amplifier gain via gate 2 of FET Q1061 (BB304CDW) of the 2nd IF amplifier circuit, to prevent the TX output from exceeding the preset level. 11 Circuit Description PLL Frequency Synthesizer The PLL Frequency Synthesizer consists mainly of the master reference os

38、cillator circuit, 2nd local oscillator cir- cuit, PLL IC, and CAR-DDS and REF-DDS units, which digitally synthesize carrier outputs, plus a PLL circuit which contains a voltage controlled oscillator (VCO). Master Reference Oscillator Circuit The master reference oscillator uses a Crystal Oscillator

39、(oscillation frequency: 22.625 MHz) composed of Q5001 (2SC4400-4), X5001, TC5001, C5001, and R5005. The reference oscillator signal passes through a buffer ampli- fier Q5002 (2SC4400-4), and is then fed to the MAIN Unit via J5002. CAR-DDS Circuit REF-DDS Circuit DDS ICs Q1062 (AD9835BRU), and Q2016

40、(AD9850BAS) each contain a shift register, selector, phase accumulator, and ROM. The reference oscillation frequency (22.625 MHz) that is delivered to each of the DDS Units is applied to each DDS IC after amplification by transistors Q1043, Q1046, Q1048, and Q1059 (all 2SC4400-3). The DDS outputs co

41、ntain digital amplitude data corre- sponding to serial frequency data from CPU IC Q1049. The DDS frequency range is 453.5 466.5 kHz (center frequency = 455.0 kHz) for the CAR-DDS, and 7.2-8.0 MHz for the REF DDS. 1st Local Oscillator Circuit VCO output is buffer-amplified by Q2011 (2SC5374) and Q202

42、2 (UPC2713T), and passes through a low-pass filter. It is then fed to the TX/RX frequency mixer cir- cuitry of the MAIN Unit. 2nd Local Oscillator Circuit The 2nd LO circuit is a Hartley-type overtone oscillator circuit (frequency: 67.875 MHz) composed of Q1052 (2SC4400-3) on the MAIN Unit. PLL Circ

43、uit The PLL circuit is a frequency mixing type composed of a VCO, mixer, PLL IC, and loop filter. The VCO consists of five circuits (VCO1, VCO2, VCO3, VCO4 and VCO5), with a frequency range of 68.430-538.330 MHz divided into five bands, allocated to the five VCO circuits. VCO1- VCO5 consist mainly o

44、f FETs Q2004, Q2005, and Q2006 (all 2SK210GR); transistors Q2009 and Q2010 (both 2SC5374); diodes D2001-D2006 (all HVC362), D2007 (1SV282), D2008 (1SV281), and D2009 (1SV286); and coils T2001-T2003, L2010, and L2011. The VCO switching signal from the connector J2002 is used to drive switching transi

45、stors Q2001, Q2002, Q2003, Q2012, and Q2013 (all DTC124EU) to switch the source terminal of the oscillator FET. The 68.430-538.330 MHz VCO signal is buffer-ampli- fied by Q2023 (UPC1688G), and fed to PLL IC Q2021 (FQ7925). The REF-DDS signal (7.2-8.0 MHz) is fed to PLL IC Q2021 after it passes throu

46、gh a low-pass filter composed of C2064, C2067, C2069, C2071, C2075, L2014, L2015, and L2016, and is fed to PLL IC Q2021 (FQ7925). The phase of the reference frequency and that of the signal input to the PLL IC are compared, and a signal whose pulse corresponds to the phase difference is produced. 12

47、 Alignment Introduction and Precautions The following procedures cover adjustments that are not normally required once the transceiver has left the facto- ry. However, if damage occurs and some parts subsequent- ly be replaced, realignment may be required. If a sudden problem occurs during normal op

48、eration, it is likely due to component failure; realignment should not be done until after the faulty component has been replaced. We recommend that servicing be performed by authorized Vertex Standard service technicians, experienced with the circuitry and fully equipped for repair and alignment. I

49、f a fault is suspected, contact the selling dealer for instruc- tions regarding repair. Authorized Vertex Standard ser- vice technicians have the latest configuration information, and realign all circuits and make complete performance checks to ensure compliance with factory specifications after repairs. Those who do undertake any of the following alignments are cautioned to proceed at their own risk. Problems caused by unauthorized attempts at realignment are not covered by the warranty policy. Also, Vertex Standard must re- serve the rig