FT817ND.pdf

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1、2005 VERTEX STANDARD CO., LTD. (E137790B) Technical Supplement FT-817/FT-817ND HF / VHF / UHF All Mode Transceiver Introduction This manual provides technical information necessary for servicing the Yaesu FT-817/FT-817ND HF 10.7 MHz (WFM) 2nd: 455 kHz Sensitivity:SSB/CWAMFM 100 kHz-500 kHz 500 kHz-1

2、.8 MHz32 V 1.8 MHz-28 MHz0.25 V2 V 28 MHz-30 MHz0.25 V2 V0.5 V 50 MHz-54 MHz0.2 V2 V0.32 V 144/430 MHz0.125 V0.2 V (IPO, ATT off, SSB/CW/AM = 10 dB S/N, FM = 12 dB SINAD) Squelch Sensitivity:SSB/CW/AMFM 1.8 MHz-28 MHz2.5 V 28 MHz-30 MHz2.5 V0.32 V 50 MHz-54 MHz1 V0.2 V 144/430 MHz0.5 V0.16 V (IPO, A

3、TT off) Image Rejection: HF/50 MHz: 70 dB 144/430 MHz: 60 dB IF Rejection:60 dB Selectivity (6/60 dB): SSB/CW: 2.2 kHz/4.5 kHz AM: 6 kHz/20 kHz FM: 15 kHz/30 kHz FM-N: 9 kHz/25 kHz SSB (optional YF-122S installed): 2.3 kHz/4.7 kHz (66 dB) CW (optional YF-122C installed): 500 Hz/2.0 kHz CW (optional

4、YF-122CN installed): 300 Hz/1.0 kHz AF Output: 1.0 W (8 Ohms, 10% THD or less) AF Output Impedance:4-16 Ohms Specifications are subject to change without notice, and are guaranteed within amateur bands only. Frequency ranges vary according to transceiver version; check with your dealer. 3 Exploded V

5、iew it then passes through a filter (R1308 and C1293). The signal next passes through a de-emphasis cir- cuit which consists of R1256 and C1286. The squelch circuit selectively amplifies the noise com- ponent of the demodulator output using the filter ampli- fier inside the FM IC and the active band

6、-pass filter con- sisting of an externally attached resistor and capacitor. This circuit uses a signal detected by D1065 (DA221). SSB/CW Demodulator Circuit The 2nd IF signal is applied to the SSB demodulator Q1055 (SN16913P) on the MAIN Unit, which produces audio by applying a carrier signal from t

7、he CAR-DDS IC Q1031 (AD9835). Similarly, the CW signal is demodulated us- ing a carrier signal which is offset by the Pitch frequency. The demodulated SSB and CW signals are each stripped of high-frequency components by an active low-pass fil- ter which consists of op-amp IC Q1093-1 (NJM2902V). Then

8、, they enter the VR Unit via J1008. AM Demodulator Circuit The 2nd IF signal from the IF Unit is applied to diode D1060 (BAS316) for AM demodulation. The output from the detector passes through analog switch Q1049 (BU4066BF). Then, it enters the VR Unit via J1008. Audio Amplifier Circuit The demodul

9、ated signal that is selected by one of analog switches IC Q1057 (BU4066BCF: according to the recep- tion mode) passes through the audio amplifier IC Q1094 (NJM2902V), volume control VR4901, and IC Q1070 (TDA7233D) to drive the internal or external speaker with a maximum output of approximately 1.0 W

10、att. Transmit Signal Circuitry Microphone Amplifier Circuit The audio signal from microphone jack J1014 on the MAIN Unit is amplified by transistor Q1092 (2SC4154E) on the MAIN Unit, and then is applied to electronic vol- ume IC Q1071 (M62364FP), which is controlled via the User Menu (Item #46: SSB

11、MIC). The output (audio signal) from the electronic volume IC is amplified by Q1096 (NJM2902V) and fed to balanced modulator IC Q1087 (SN16913P) through the low-pass filter IC Q1096 (NJM2902V). During FM transmission, the audio signal is adjusted via the User Menu (Item# 29 : FM MIC). The audio sign

12、al that has passed through the pre-emphasis circuit (C2201 and R2228 on the MAIN Unit) may be mixed with a tone sig- nal from CPU IC Q4004 (HD6432345A20FA), and is then amplified and limited by op-amp IC Q1095-4 (NJM2902V) of the IDC circuit. The audio then passes through the splat- ter filter (seco

13、ndary active low-pass filter) formed by op- amp IC Q1095-1 (NJM2902V), R1321, and R1322, plus C1344, and is then fed to the frequency-modulator circuit on the MAIN Unit through R1183 and R1477 for setting of the frequency deviation. SSB Modulator Circuit The carrier signal appropriate to the transmi

14、tting mode (LSB or USB) is applied from the CAR-DDS Unit to bal- anced modulator IC Q1087 (SN16913P) on the MAIN Unit, and is modulated by microphone audio. The balanced modulator produces the upper and lower side bands and carrier signal. The carrier and audio sig- nal are suppressed and the carrie

15、r balance is adjusted by VR1001. As a result, the output signal obtained is a DSB signal with a carrier suppression of 30 dB or more (addi- tional carrier suppression is supplied by the SSB filter). The DSB modulated signal (1st IF signal: 455 kHz) then passes through ceramic filter CF1004 (CFJ455K1

16、4) or the optional mechanical filter U1003 on the MAIN Unit, strip- ping residual carrier and the undesired sideband; the sig- nal then passes as an SSB signal through buffer-amplifier Q1040 (BB301C). 11 Circuit Description AM Modulator Circuit As in the SSB modulator circuit, a carrier signal from

17、the CAR-DDS Unit and an audio signal from the microphone are applied to balanced modulator IC Q1087 (SN16913P) on the MAIN Unit. The control signal from MODE SW IC Q1021 (BU4094BCFV: Lot 1 - 76, CD4094BPWR: Lot 77 -) on the MAIN Unit causes a voltage labeled AM 5V to be sent from transistor Q1079 (2

18、SC4154E). This voltage is applied to IC Q1087 (SN16913P) via D1077 (BAS316), causing the balanced modulator to lose balance. The re- stored carrier signal and modulated signal are then fed to the Tx mixer via ceramic filter CF1004 (CFJ455K14) on the MAIN Unit. Frequency Modulation Circuit The FM cir

19、cuit uses a voltage controlled crystal oscillator (VCXO) which consists mainly of Q1033 (2SC4400), X1001 on the MAIN-Unit, varactor diode D1056 (1SV229), and T1018. The VCXO has a center frequency of 22.7785MHz. The FM signal is produced by applying a signal from the FM microphone amplifier circuit

20、to varactor diode D1056 and varying the crystal oscillator load capacity in propor- tion to the signal voltage. CW (A1) Signal Generator Circuit When the transmitting mode is CW (A1), the control sig- nal from D-A converter IC Q1077 (M62353GP) on the MAIN Unit creates a CW 5V voltage. The voltage is

21、 ap- plied to balanced modulator IC Q1087 (SN16913P) via D1071, providing a carrier from the balanced modulator for the input to the transmit signal circuit of the MAIN Unit. 1st IF Circuit/1st Mixer Circuit The 455 kHz 1st IF signal from the modulator circuit is band-limited by the MAIN Units ceram

22、ic (CF1004) or optional mechanical filter U1003 (XF5201 or XF5301) ac- cording to the selected mode (CW, SSB, or AM). It is then buffer-amplified by FET Q1040 (BB301CAW) and fed to 1st mixer IC Q1038 (SN16913P). The IF Units double balanced mixer IC Q1038 (SN16913P) is used as the 1st mixer. A local

23、 signal (67.875MHz) is produced by tripling the Reference fre- quency at Q1047 (2SC4400), and this local signal is fed to the local port of the doubly-balanced mixer IC, where it is mixed with the 455 kHz 1st IF signal to produce a 68.33MHz 2nd IF signal. 2nd IF Circuit/2nd Mixer Circuit The 2nd IF

24、signal passes through crystal filter XF1001 and then is fed to the 2nd mixer circuit. The 2nd mixer consists of the MAIN Units D1049 (HSB88WS). The 2nd local signal (68.430-538.330MHz) from the PLL Unit is applied to the gates of each FET in the 2nd mixer. High-Frequency Transmit Preamplifier Circui

25、t The transmit signal is passed through a low-pass filter (1.8-29.7 MHz), a high-pass filter (50-54 MHz), a band- pass filter (144-146 MHz), or a band-pass filter (430-440 MHz) and then is amplified by Q1001 (UPC2710), and passed onward to the PA Unit via J1002. Power Amplifier Circuit The transmit

26、signal from the MAIN Unit arrives at con- nector J3001 on the PA Unit. The transmit signal (1.8 MHz to 430 MHz) delivered to the PA Unit is amplified by pre-driver Q3001 (2SC3357), driver Q3002 (2SK2596) and final amplifiers Q5401/ Q5402 (2SK2975: Lot 1 - 74, RD07MVS1: Lot 75 -). Low-Pass Filter (LP

27、F) Circuit The transmission signal from the power amplifier circuit is passed through a low-pass filter which consist mainly of RL3001-RL3015, RL3017, and corresponding inductor and capacitor networks. The LPF is a 5th or 7th-order Chebyschev type filter, utilizing nine different sections for the va

28、rious amateur bands at 1.8 430 MHz. The low-pass filtered transmission signal is fed to the FRONT ANT connector (J0001) or REAR ANT connector (J0002) through the triplexer and directional coupler. The directional coupler samples a part of the transmis- sion power to detect forward power and reflecte

29、d power. A DC voltage corresponding to the relative forward/re- flected power is produced by D3032/D3033 (both MA716, 1.8 to 54 MHz), D3009/D3017 (both MA716, 144 to 148 MHz), or D3007/D3008 (both MA716, 430 to 450 MHz) , and is used for automatic level control (ALC). ALC Circuit The output from the

30、 directional coupler is routed from connector J3004 and applied to the ALC circuit via con- nector J1003 on the MAIN Unit. The ALC circuit consists of an op-amplifier circuit for amplifying the forward and reflected voltage, a time-con- 12 Circuit Description stant ALC amplifier, and a transmit sign

31、al control circuit on the MAIN Unit. The forward voltage from connector J1003 on the MAIN Unit is added with a DC control voltage and is then ap- plied to op-amp IC Q1097 (NJM2902V). The reflected voltage is added with a DC control voltage and is then applied to op-amp IC Q1098 (NJM2904V), In the ev

32、ent of high SWR conditions (SWR of 3:1 or more), transmitter output is reduced and a High SWR warning appears, thus protecting the PA Unit from potential dam- age and alerting the operator to the high SWR situation. The ALC amplifier amplifies the forward DC output via transistor Q1019 (2SC4154). Th

33、is output then passes through a fast-attack, slow-delay RC time-constant cir- cuit which consists of R1097 and C1113 for the input to the Tx signal control circuit on the MAIN Unit. The TX control circuit adjusts the IF amplifier gain via gate 2 of FET Q1007 (BB304CDW) of the 68.33 MHz IF amplifier

34、circuit to prevent the power output from exceed- ing the preset level. PLL Frequency Synthesizer The PLL Frequency Synthesizer consists mainly of a mas- ter reference oscillator circuit, 2nd local oscillator circuit, plus the PLL IC, CAR-DDS, and REF-DDS units, which digitally synthesize carrier out

35、puts, and a PLL circuit which contains a voltage controlled oscillator (VCO). Master Reference Oscillator Circuit The master reference oscillator uses a crystal oscillator (oscillation frequency: 22.625MHz) composed of Q5001 (2SC4400), X5001, TC5001, C5001, R5005, and associated components. The refe

36、rence oscillator signal passes through buffer amplifier Q5002 (2SC4400), C5004, C5007, R5003, R5004, R5007, and is then fed to the MAIN Unit via J5002. CAR-DDS Circuit /REF-DDS Circuit DDS ICs Q1031 (AD9835BRU) and Q2016 (AD9850BRS) each contain a shift register, selector, phase accumulator, and ROM

37、. The reference oscillation frequency (22.625MHz) that is delivered to each of the DDS Units is applied to each DDS IC after amplification by transistors Q1028/Q2020 (both 2SC4400). The DDS outputs contain digital amplitude data corre- sponding to serial frequency data from CPU IC Q4004 (HD6432345)

38、of the PANEL Unit. The DDS frequency range is 453.5 466.5 kHz (cf = 455.0 kHz) for the CAR- DDS, and 7.2-8.0 MHz for the REF DDS. 2nd Local Oscillator Circuit The 2nd L.O. circuit is a Hartley-type overtone oscillator circuit (frequency: 67.875 MHz) composed of Q1047 (2SC4400) on the MAIN Unit. 1st

39、Local Oscillator Circuit VCO output is buffer-amplified by Q2008 (2SC4400), Q2011, Q2014, and Q2016 (all 2SC5374) and passes through a low-pass filter. It is then fed to the Tx/Rx fre- quency mixer circuitry on the MAIN Unit. PLL Circuit The PLL circuit is a frequency mixing type composed of a VCO,

40、mixer, PLL IC, and loop filter. The VCO consists of five circuits (VCO1, VCO2, VCO3, VCO4, and VCO5), with a frequency range of 68.430- 538.330 MHz divided into five bands, allocated to the five VCO circuits. VCO1-VCO5 consist mainly of FETs Q2004, Q2005, and Q2006 (all 2SK210GR), transistors Q2009,

41、 Q2010 (both 2SC5374), diodes D2001-D2006 (all HVC362), D2007 (1SV282), D2008 (1SV281), and D2009 (1SV286), and coils T2001-T2003, L2010, and L2011. The VCO switching signal from connector J2002 is used to drive switching transistors Q2001, Q2002, Q2003, Q2012, and Q2013 (all DTC124EU) to switch the

42、 source terminal of the oscillator FET. The 68.430-538.330 MHz VCO signal is fed to mixer D1047 (GN2011-Q). The REF-DDS signal (7.2-8.0 MHz) is fed to PLL IC Q2022 (UPC2713T: Lot 1 - 74, UPC2710: Lot 75 -) after it passes through a LPF composed of C2064, C2067, C2069, C2071, C2075, L2014, L2015, and

43、 L2016 , and buffer amplifier Q2019 (2SC4400). The phase of the reference frequency and that of the sig- nal input to PLL IC are compared, and a signal whose pulse corresponds to the phase difference is produced. The VCO frequency is controlled by a first lag filter which consists of R2057, R2065, R

44、2062, and C2090 and a second- ary lag filter composed of C2085, C2088, and R2053. 13 Circuit Description Control Circuitry Microprocessor Circuit The microprocessor circuit, which is composed of CPU IC Q4004 (HD6432345) and EEPROM IC Q4006 (AT24C64AN), performs various types of processing, such as c

45、ontrol signals, serial I/O, A/D conversion, dial counter circuit control, key input, and display functions. The EEPROM memorizes various parameters and settings (transmission frequency range, transmission output con- trol) and carrier points according to the transceiver ver- sion and the contents of

46、 memory channels. Reset Circuit The reset circuit consists mainly of PANEL Unit ICs Q4014 (PST3445), Q4015, Q4016 (both 2SC4154), and Q4010, Q4011 (both 2SA1602A), and associated capacitors and resistors. This circuit controls the power-down input port, CPU reset input, keyer CPU, and related circui

47、ts. Dial Counter Circuit The dial counter circuit consists of Main Dial and SEL (Se- lector) Knob. This circuit detects a two-phase pulse hav- ing a phase difference of 90 degrees and delivers it to CPU IC Q4006. Serial Data Communication Circuit The Serial Data Communication Circuit consists of ICs

48、 Q4008 (TC7SU04FU), Q4009 (TC74HC139AF) and tran- sistor Q4010 (2SA1602A), etc. on the PANEL-Unit. These ICs distribute a set of serial data (Data/Clock/Strobe) gen- erated by CPU to various devices, such as CAR-DDS, REF- DDS, E.VOL, D/A, or Shift-Register for controlling ana- log switching , band s

49、witching, VCO selection, etc. Serial data communication is clock synchronous for the above purposes, whereas the serial data is transferred to an asyn- chronous signal for the CAT system for external computer control of the transceiver). Various types of data, such as operating frequency, mode, and display data, are processed by CPU IC Q4004 (HD6432345). The CAT (external computer control) signals are converted to RS232 interface standard levels by the optional CAT Interface Cable (CT-62). Key Matrix Circuit The key matrix circuit consists of PANEL Unit diodes D4001-D4003 and D40