PHILIPS. PM3267. Test. Service Manual. CDC-311.电路图.pdf

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1、100 MHz Dual-Channel Oscilloscope _ I-It7 F , , M , FLIAF)PE13, PM 32671 PM 3267U i:mm Service Manual 9499 445 021 11 84031 6/04 lPHlLlPSl Scientific often a problem with long signal wires. In the TRIGGER INPUT STAGE, these current signals are converted into voltage form, and fed to the TRIGGER SELE

2、CTION CIRCUIT. The EXT trigger signal from the EXT input socket, and the LINE signal from the LINE TRIGGER PICK-OFF are fed to the TRIGGER SELECTION CIRCUIT via the EXT-LINE TRIGGER INPUT circuit. In this stage, the EXT and LINE trigger signals are converted to symmetrical current signals and adapte

3、d to the A, B and COMP signals. The EXT-LINE TRIGGER INPUT stage is controlled by the EXT pushbutton and LINE (pushbuttons B and EXT depressed simultaneously). In addition, the A and B trigger signals are fed to the TRIGGER SELECTION CIRCUIT of the DTB. 2. 1 . 2 . 1. - Main time-base The trigger sig

4、nals are selected by the MTB trigger source switches A, B, EXT, COMP, LINE, which control the TRIGGER SELECTION CIRCUIT. Common-mode interference is reduced by using a symmetrical configuration for the TRIGGER SELECTION This stage converts the symmetrical current signal to an asymmetrical voltage si

5、gnal, which is fed to the switches DC, LF, HF. Several signals are produced by the INTERFACE, e.g. X DEFL, TRIG VIEW and AUTO/TV. The X-DEFL signal is an asymmetrical signal that is fed to the X DEFLECTION AMPLIFIER. The symmetrical TRIG VIEW signal is routed to the VERTICAL CHANNEL SWITCH; the asym

6、metrical AUTO/TV signal is routed to the AUTO and TV CIRCUIT. The FINAL TRIGGER AMPLIFIER comprises the SLOPE circuit under the control of the SLOPE switch The output of the FINAL TRIGGER AMPLIFIER is fed to the CURRENT-VOLTAGE CONVERTER. In the AUTO CIRCUIT, the TOP DETECTOR detects the amplitude o

7、f the AUTO SIGNAL. When in the AUTO Mode, the LEVEL range is determined by this detected amplitude. The MULTIPLEXER is an electronic switch which, depending on the selected mode, selects the different ranges for the LEVEL control. Each mode has its own specific LEVEL range, for example: - CIRCUIT ou

8、tput signal. This output current signal is fed to the TRIGGER AMPLIFIER INPUT STAGE. INTERFACE via the TRIGGER COUPLING stage. The coupling is controlled by the MTB trigger coupling -_ L - incorporated in the LEVEL control. It permits positive and negative triggering. - .- TV : fixed level TRIG : f

9、8 divisions X DEFL : 0 divisions (LEVEL inoperative) AUTO : determined by TOP DETECTOR - If the instrument is provided with the TTL/ECL option, the TV pushbutton will function as the TTL or ECL mode switch. The TV trigger signal is fed to the TV CIRCUIT. When the TV pushbutton is selected, the TV CI

10、RCUIT is inserted between the INTERFACE and the CURRENT- VOLTAGE CONVERTER of the MTB. - - I In the TV mode, the FINAL TRIGGER AMPLIFIER is switched off and also the LEVEL control is inoperative, a fixed trigger level being set. For FRAME and LINE synchronisation, a frame or line filter is selected

11、with the MTB TIME/DIV switch. Via The SWEEP-GATING LOGIC determines the start of the MAIN TIME-BASE GENERATOR sweep. The SWEEP-GATING LOGIC is controlled by signals derived from the TRIGGER MODE SELECTION, the HOLD-OFF CIRCUIT and the CURRENT-VOLTAGE CONVERTER. The TRIGGER MODE SELECTION is controll

12、ed by the MTB trigger mode selection pushbuttons AUTO, TRIG, SINGLE. In the AUTO mode, the MAIN TIME-BASE GENERATOR runs automatically when no trigger pulses are available. In the TRIG mode, the MAIN TIME-BASE GENERATOR must be normally triggered by trigger signals derived fromthe CUR RENT-VOLTAGE C

13、ONVERTER. If the SINGLE pushbutton is selected, the SWEEP-GATING LOGIC will start the MAIN TIME-BASE GENERATOR for one sweep. - The MAIN GATE OUT signal (optional) is taken from the SWEEP-GATING LOGIC This MAIN GATE OUT signal output is at logic H during the MTB sweep and L for other conditions. The

14、 NOT TRIG LED lights up when the MTB is not triggered. the CURRENT-VOLTAGE CONVERTER, the trigger signal is routed to the SWEEP-GATING LOGIC. _ -_ - 2.1.2.2. 2-5 The MAIN TIME-BASE GENERATOR produces a sawtooth voltage, the repetition time being controlled by the TIME/DIV switch. To enable the capac

15、itors that determine the repetition rate sufficient time to discharge, the HOLD-OFF CIRCUIT is employed. This time is adjustable with the HOLD-OFF control. After the HOLD-OFF time, the HOLD-OFF CIRCUIT sends a signal to the SWEEP-GATING LOGIC, which in turn starts the next time-base sweep. The repet

16、ition rate of the MTB sawtooth voltage is continuously variable with the continuous control CAL. The output sawtooth voltage from the MTB is fed to the HORIZONTAL CHANNEL SWITCH circuit. Delayed time-base Channel A and B trigger signals are fed to the DTB TRIGGER SELECTION CIRCUIT via the TRIGGER IN

17、PUT STAG E . Trigger selection is controlled by the DTB trigger source selection pushbuttons A, B. The symmetrical output current signal from the TRIGGER SELECTION CIRCUIT is converted to an asymmetri- cal voltage signal in the TRIGGER AMPLIFIER INPUT STAGE. This signal is then fed via the TRIGGER C

18、OUPLING circuit to the FINAL TRIGGER AMPLIFIER. Trigger coupling is selected by thn DC, LF, HF pushbuttons. The FINAL TRIGGER AMPLIFIER comprises the LEVEL/SLOPE controls and their associated circuits. The asymmetrical input voltage signal is converted to an asymmetrical current signal, which is fed

19、 to the CURRENT- VOLTAGE CONVE RTE R . The output of the CURRENT-VOLTAGE CONVERTER and the output of the COMPARATOR are fed to the SW EEP-GAT I NG LOG IC. The COMPARATOR circuit compares the amplitude of the MTB sawtooth voltage with a d.c. voltage selected by the DELAY TIME control. If the amplitud

20、e of the MTB sawtooth is equal to the d.c. voltage, the COMPARATOR produces a signal that is then fed to the SWEEP-GATING LOGIC. If the MTB pushbutton of the delayed time-base trigger source switches is depressed, the SWEEP-GATING LOGIC starts the DELAYED TIME-BASE GENERATOR immediately after the DE

21、LAY TIME selected. If the A or B pushbutton is depressed, the SWEEP-GATING LOGIC detects the end of the delay time but waits for a trigger signal (A or B) from the CURRENT-VOLTAGE CONVERTER, after which the TIME-BASE GENERATOR starts. The DELAYED GATE OUT is taken from the SWEEP-GATING LOGIC when th

22、is option is available. The output is at logic H during the DTB sweep and L for other conditions. The DTB sawtooth voltage is produced in the DELAYED TIME-BASE GENERATOR under the control of the TIME/DIV switch and its continuous CAL control. If the UNCAL LED lights up, it indicates that the continu

23、ous controls of one or both time-bases are not in the CAL position. 2.1.2.3. Horizontal channel selection and final horizontal amplifier In the X DELFECTION AMPLIFIER the X DEFL signal derived from the MTB INTERFACE is amplified and fed to the HORIZONTAL CHANNEL SWITCH circuit. The HORIZONTAL CHANNE

24、L SWITCH selects the X DEFL, MTB and/or DTB signals under the control of the HORIZONTAL CHANNEL SELECTION LOGIC, which in turn is controlled by the horizontal display mode switches X DEFL, DTB, ALT TB, MTB. If the X DEFL pushbutton is selected, the signal chosen by the MTB trigger source selection s

25、witches A, B, EXT, LINE, will determine the horizontal deflection. Horizontal deflection is performed by the sawtooth output of the DELAYED TIME-BASE GENERATOR if the DTB pushbutton is selected. Similarly, the MTB pushbutton selects the MAIN TIME-BASE GENERATOR sawtooth for horizontal deflection. If

26、 the ALT TB pushbutton is selected, the HORIZONTAL CHANNEL SWITCH alternates from the MTB saw- tooth to the DTB sawtooth voltage at the end of everty time-base sweep. 2-6 The selected signal is routed to the FINAL HORIZONTAL AMPLIFIER via the HORIZONTAL PRE- AMPLIFIER. This pre-amplifier comprises t

27、he X POS potentiometer for horizontal shift of the trace, and its associated circuit. It also includes the X MAGNIFIER for x10 magnification of the horizontal deflection. If the X MAGN push-pull switch, incorporated in the X POS control, is pulled for x10 magnification the MAGN LED lights-up. - - Th

28、e signal is converted into symmetrical current form in the HORIZONTAL PRE-AMPLIFIER and fed to the FINAL HORIZONTAL AMPLIFIER to drive the horizontal deflection plates of the c.r.t. - 2.1.3. CRT Display Section The Z-LOGIC and Z PRE-AMPLIFIER stages are part of the TIME-BASE UNIT 2. The Z-AMPLIFIER,

29、 CALIBRATION GENERATOR and TRACE ROTATION CIRCUIT are located on the UNIT 6. FINAL AMPLIFIER UNIT 5. The supply voltages for the c.r.t. are derived from the POWER SUPPLYf - The Z-LOGIC receives the following inputs to drive the Z PRE-AMPLIFIER and Z-AMPLIFIER: - - The external Z-MOD signal applied t

30、o the BNC connector on the rear panel. This 2-MOD signal must be - Two signals produced in the MTB and DTB to unblank the trace during the sweeps. - The chopper blanking signal from the VERTICAL CHANNEL SELECTION LOGIC to blank the trace TTL-compatible. An L level in gives trace blanking. + during s

31、witching between channels A and B in the chopped mode. The output signal from the Z-LOGIC that determines trace blanking or unblanking is routed to the Z PRE- - AMPLIFIER. Here the trace intensity is determined by the front-panel INTENS potentiometer setting. In the Z AMPLIFIER, after amplification

32、the Z-signal is split into two paths, an 1.f. + d.c. and an h.f. path, because of the potential difference that exists between the Z AMPLIFIER output and the c.r.t. cathode - (-1500 V). The h.f. signals are fed via a high voltage capacitor directly to grid GI of the c.r.t. oscillator frequency, whic

33、h is then passed via another high voltage capacitor and demodulated in the DEMO- DULATOR stage to retrieve the original signal. However, the d.c. and 1.f. signals are blocked by this capacitor. These signals therefore are used to modulate an - The original h.f. and d.c. + 1.f. signals are recombined

34、 on the grid GI - The c.r.t. supply voltages are derived from the 1500 V GENERATOR. The CRT CIRCUIT comprises the FOCUS control circuit for the electron beam, and the preset potentiometers for GEOMETRY and ASTIGMATISM. I The post-acceleration anode potential of 8,5 kV is produced in the HV MULTIPLIE

35、R and derived from the -1500 V cathode supply. - A preset front-panel control TRACE ROTATION enables the trace to be aligned in parallel with the graticule lines. This preset controls the TRACE ROTATION CIRCUIT that drives the trace rotation coil situated on the c.r.t. I 2.1.4. Power Supply - The in

36、strument may be powered either by an a.c. supply voltage or by a 24 V battery supply voltage. By means of the MAINS VOLTAGE ADAPTOR the instrument can be set to the local mains voltage. This circuit incorporates a fuse for the a.c. supply. - This a.c. supply voltage is fed via the double-insulated m

37、ains transformer to the full-wave RECTIFIER. A LINE trigger signal at mains frequency is fed via the LINE TRIGGER PICK-OFF circuit to the EXT-LINE TRIGGER INPUT. From the RECTIFIER the unregulated d.c. supply is fed to the CONVERTER DRIVER. When a 24 V battery supply is used, this is fed via the DC

38、PROTECTION + FUSE stage to the CONVERTER DRIVER. This protection stage safeguards the instrument against reversed polarity of the battery supply source. - .- 2-7 Attenuation positions x5 x2.5 X I c FET switches conductive D503/9,11,12 D503,5,6,8 D503/1,3,4 THE CONVERTER DRIVER stage drives the CONVE

39、RTER transformer. The rectified +14V output-voltage is fed back as control via the REGULATOR + PROTECTION circuit. In this way, the voltages on the secondary windings of the CONVERTER transformer are stabilised. After rec- tification and smoothing, the stabilised supply voltages are fed to the vario

40、us electronic circuits in the instru- ment. 2.2. CIRCUIT DESCRIPTION OF THE VERTICAL SECTION l- l- As the channel A and B attenuators are almost identical, only the channel A is described. 2.2.1. Input Signal Coupling (see Fig. 8 . 3 . ) Input signals applied to input socket A (X2) can be either a.c

41、.-coupled, d.c.-coupled or internally disconnected, depending on the coupling mode switch position of S17 (AC-0-DC). In the AC position (S17A points 2 and 3) a blocking capacitor C501 paralleled by series circuit R502 and C502 are inserted in the signal path which prevents the d.c. component being a

42、pplied to the attenuator. In this mode, the lower frequency limit is 2 Hz and some pulse droop may occur when low-frequency square-wave signals are displayed. When DC is selected (S17A points 1 and 2 and S17B points 4 and 5) the complete input signal (a.c. + d.c. components) is fed to the attenuator

43、 input R503, R504, R506. Thus the full bandwidth of the oscilloscope is available. If the 0 pushbutton is depressed, the input signal is isolated from the attenuator and the attenuator input is earthed, as a reference for calibration or trace centering, etc. 2 . 2 . 2 . Attenuator and Impedance Conv

44、erter (see Fig. 2.2. and 8.3) The attenuator consists of a triple high-impedance voltage divider, an impedance converter and a low-impedance voltage divider. High-impedance and lo w-impedance attenuator The overall attenuation is determined by the combinations of the selected sections of the high- a

45、nd low-impe- dance attenuator. The voltage dividers of the high-impedance attenuator are controlled by reed relays. Read relay K503 and K504 are activated in the AMPL/DIV (S9) positions 2 mV/DIV . 100 mV/DIV (x 1 stage). In the 0.2 V/DIV . 1 V/DIV positions of S9, reed relays K506 and K507 are activ

46、ated. The input signal is x10 attenuated by voltage divider R514 and R516. When positions 2 V/DIV . 10 V/DIV are selected, reed relays K501 and K502 are activated, and the input signal is XI 00 attenuated by voltage divider R509 and R511. The AMPL/DIV switch S9 controls the FET switches via resistor

47、s R557, R559 and R562. These resistors have high-ohmic values to eliminate parasitic capacitance effects on the FET gates, thus preventing any loss of band- width. The trimmers C504 and C512 are adjustable to obtain constant input capacitance in all attenuator settings. The high-impedance attenuator

48、 sections are made independent of frequency (i.e. the capacitive attenu- ation for a.c. signals is adjusted to conform with the resistive attenuation for d.c. signals) by means of trimmers C503, C508 and C511. 2-8 V501 V506 ATT I =- V507 IMP I - I Impedance converter (see Fig, 2.2. and 8.3.) The inp

49、ut signal is fed via FET V501 (in source-follower cor?figuration), transistors V503, V504 and V508 to the low-impedance attenuator. The special type FET V501, with very fast rise-time response, reduces the source impedance which prevents bandwidth loss. The FET consists of a double gate. One gate is not used and connected to the drain via R521. The input signal is applied to the other gate. The diodes inside this FET protect the input source follower of the