Fluke B0127-FlukeAddtionalOperationManual 电路.pdf

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1、Dialog BOi27 9010A Micro-System Troubleshooter Avoiding Potential Problems When Getting Started Introduction This document is intended to be used in conjunction with the 9010A Operators Manual when getting started on troubleshooting your own system. It is not intended to be a substitute for the manu

2、al. This document covers common precautions to be observed and the error messages you may encounter when plugging the 9010A interface into your unit- under-test (UUT) for the first time. More detailed information is contained in your Operators Manual. Should applications assistance be necessary, ple

3、ase contact your Fluke Sales Engineer. 收音机爱好者资料库 Ra d i o Fa n s .CN Table of Contents I. INITIAL CONSIDERATIONS A.Starting Off With a Known Good UUT B. Multiple Processor Systems C, Systems With Watchdog Timers D. Multiple-Page Memories E.I/O Ports Connected To Active Stimulus F. Enableable Lines G

4、. Warning II. INITIAL SETUP A. B. C. D. E. F. G. H. f : III. LEARN A. B. IV. VIEW A . B. c. D. Fail On Power Up Pod Self-Test Fail Pod Time Out UUT Power Fail Bad Power Supply Active Forcing Line Active Interrupts Control Error Address-Bit Tied Data-Bit Tied Learn Fail Fatal Abort Finding Nothing Fi

5、nding Many Small I/O Sections Does Not Find All I/O Locations False ROM V. PREPROGRAMMED TESTS A. Control Error B. Address Error C. Data Error D. Read/Write Error E. RAM-Bits Tied F. RAM Decode Error G. RAM Pattern Error H. ROM Error I. Initial Considerations Before starting, there are a few importa

6、nt points to consider with regard to the 9010A and its interaction with your system. While most users will find that they can begin troubleshooting with no extraordinary efforts, some special purpose designs and applications may require special handling. The user needs to be aware of these situation

7、s and how to handle them. A. B. C. Starting Off With a Known Good Unit- Under-Test (UUT) When documentation is unavailable or it is desired that the LEARN feature be used, it is important that a known good UUT is tested. In the event a faulty UUT is used, false information is likely to be learned. T

8、his occurs since the LEARN algorithm acts upon the information returned from a series of read and write operations. If misinformation is fed into the algorithm, erroneous values are returned. Multiple Processor Systems It is common in todays technology to design a system with multiple processors. In

9、 the typical case where the processors talk to each other through a communication port, the 9010A is easily used by plugging into each processor socket one-by-one and testing up to the communication port. In the less typical case, where processors share memory, additional precautions must be taken.

10、In these cases it is possible that one processor may interfere with the task being performed by the other. While handshake lines generally insure that two processors are not on the bus at the same time, one processor may corrupt data in memory, and prevent the other processor from successfully perfo

11、rming a test such as a RAM test. In these rare cases, it is necessary for the user to somehow prevent the two processors from accessing the same memory locations. This may be done by tying a line on the UUT or possibly by WRITING data to a particular location to disable one of the microprocessors. S

12、ystems With Watchdog Timers Systems designed with wdtchciog timers must be individually checked to see what this timer (reset line) is tied to. If the timer is only tied to the processor, it can be 收音机爱好者资料库 Ra d i o Fa n s .CN ignorrd in the SET UP mode. If the timer is tied to devices other than t

13、he processor then it must physically be disabled by tying the lme either high or low. D. Multiple Page Memories Sometimes, one page of memory is not sufficient for system operation. In such cases the designer incorporates multiple pages of memory. The processor switches between these banks or pages

14、in order to properly address them. The LEARN operation is not designed to find these multiple pages of memory. However, the YOlOA can easily test multiple pages of memory. A common technique is to use an l/O port to switch between banks of memory. Using the 9010A WRITE key, the desired bank can be s

15、elected for testing. It is then necessary to select either the ROM TEST or the RAM TEST as appropriate. This sequence of selecting a memory bank through a WRITE and then testing the bank of memory through RAM TEST or ROM TEST can easily be put together b the user in a 9010A program. E.I/O Ports Conn

16、ected To Active Stimulus Due to the series of reads and Lvrites performed by LEARN, Ii0 ports are stimulated when LEARN occurs across those addresses. If this I/O port is connected to a stimulus device, the device ail1 be activated. If this port is connected to a memory device such as a disk drive,

17、then rhe disk c11l very possibly be written on. F. Euableable Lines Sumctimes, enableable lines (such as KEAl)Y and HOLD on the 8080 Microprocessor) interfere with the LEARN procesh. This may occur if, for example, the board IS out of the system, and the board ntxds to be m the system to have READY

18、driven to the actiae state If this is the case, a POD Tl.1EOU? message will appear on the 9010A If this condition occurs, the READY and HOLD lines may be disabled through the SET-Cl- procedure. The SET- (1 menu items on the 8080 are ENABLE READY? and ENABLE HOLD? Answer NO to each of these one at a

19、time and see tvhich one(sl altou the pod and board to function. II. G.Warning Plug the pod into the 901 OA only u hen power is off. Plug the pod into the UUT only when the 9010A is powered on. Failure to do this may cause damage to the pod or the 9010A. Initial Setup After taking into account any of

20、 the:se initial considerations, a brief setup procedure is recommended in order to verify the integrity ot the 9010A and configure the UUT and the 9010A in such a way as to make them complimentaq This is accomplished first by powering up the 9010A which performs a self test on itself, Next, a self t

21、est of the pod is performed bj, locking the pod into the self test socket and pressing BUS TEST on the 9010A. Finally, plug the pod into the UUT and again select BUS TEST. A. B. c. Fail On Power Up When the 9010A is turned on, a if WC is performed verifying its integrity. If the message indicates a

22、failure exists in the 9010A, refer to the service manual or contact your local Fluke Service Center. Pod Self Test Fail If, when performing a pod selt test, the message refers to a pod sell resr tailbre. the pod has failed. Refer to the pod manual or contact your local Fluke Service Center. Pod Time

23、 Out The pod timeout message can CCUI butt) during a pod self test or during operation with a UUT. This message indicates that power at the microprocessor piug IS OK, but the pod IS not communicating Mith the 9010A mainframe. Check first Iu m&c sure that rhe microprocessor plug is plugged in firmly

24、wirh no pin bent under or missing (either into the se&test sucker ur the 171_“I“ During a pod self test, this message means the pod has failed and needs to be bcr iced Occurence of this mrsbage during UL-l operation may signify one of several svmptoms. Again, check to make sure the &roprocessor plug

25、 is plugged in ilrInly. Make sure the microprocessor socket has no pins bent under. Next, disable the forcing lines in the SET-.Ul mode. If the UUI requlrcs an 8080 pod, the iorcing lmes would be READY and H0L.D. SET-tip 收音机爱好者资料库 Ra d i o Fa n s .CN FLUKE Y allows you to disable these lines before

26、they enter the processor. (Thus, preventing these line:, from stopping the pod processor.) Answer NO to the SET-UP questions, ENABLE READY and ENABLE HOLD. If this doesnt clear the problem, theUUT clock should be checked for functionality. This can be easily done with the troubleshooting probe. Assu

27、ming the clock is working, the problem may be caused by a UUT clock that is slower than that expected by the 9OlOA. In this case the pod (which is running off the UUT clock) does not respond in a timely manner to commands from the 9010A. Provision is made in SET-UP to change the pod timeout. Select

28、YES, then enter a greater timeout number with 60,000 being the maximum timeout available. 1). UUT Power Fail This message can occur both during pod self test or durmg operation with a UUT. It means that the power supply at the UUT microprocessor socket is out of tolerance and the pod is not communic

29、ating with the 9010A mainframe. Check first to be sure the pod cable is plugged firmly into the 9010A. During self test, be sure the microprocessor plug is tightly held in by the pod self test %IF socket. It is possible the thumbwheel was not properly tightened and has come loose. It this message ap

30、pears during UU? operation, it means that the power supply is out of tolerance at the UUT processor socket and the pod is not communicating uith the 9OlOA. The UUT should be checked for broken power traces, and bad connections. Then, follow the procedure for 1013 TIh1EOUT above. If the pod cable is

31、properly plugged into the 9010A and the pod UUT cable is securely plugged into the LCI, then the “UUT POWER FAIL” message mdicates that the UUT microprocessor clock circuit is not working due to a bad UUT power supply. Note that the UUT power fail message cannot be disabled in SET-UP. E. Had Power S

32、upply Ihe 9010A constantlv monitors the UUTs povver to within a 10%) window. If the power supplied to the processor does not fall within this window, the 9010A will halt and display rhi message. First the UUT should be checked to determine whether a problem exists or whether this is the way the UUT

33、has been designed. (The UUT may be designed to run with a low Vcc.) If this is the UUT design, the 9010A can be made to stop monitoring UUT power through the SET-UP mode. One of the menu selections asks if you want to trap on a bad power supply. Selection of NO will now stop the 9010A from monitorin

34、g the UUTs processor power. Note that SET-UP cannot be used to disable the UUT power fail message. F. Active Forcing Line Often times UUTs are designed with watchdog timers or some other form of reset circuitry which continually try to force the processor into a certain state. If this circuitry affe

35、cts only the processor, it can be disabled through the set up commands as described in section IF. If this circuitry affects other devices on the UUT such as the ROM or RAM, then the circuit must be disabled by tying it either high or low. In tying forcing lines high or low, only one at a time shoul

36、d be manipulated. If, after tying the first line, the UUT and 9010A work together, do not tie any other lines. These lines often are used to add wait states and if disabled, the UUT may not function properly. G. Active Interrupts When an interrupt occurs, the 9OlOA tells you that this has happened.

37、It is possible that the UUT has interrupts pending all the time. In order for the 9010A to successfullv interact with the UUT, these interrupts must be ignored. A menu selection in the set up mode allows the 9010A to disregard all pending interrupts. The selection is SET - TRAP ACTIVE INTERRUPT? Sel

38、ection of NO will now allow the 9010A and UUT to function compatibly. H. Control Error The control error message indicates a faulty UUT control line. One or more of the control lines are not properly drivable. included in the message are the faulty bits. This information can then be correlated with

39、the decal on the pod case describing which bit is which control line. From here the UUT must be inspected to determine 收音机爱好者资料库 Ra d i o Fa n s .CN the cause of the drivability problem. I. Address Bit Tied Address bits may be tied high, low, or together. The full text of the message will describe t

40、he particular situation and which lines are affected. Those lines must then be traced on the UUT until the situation causing those lines to be faulty is found. J. Data Bit Tied Data bits may be tied high, low, or together. The full text of the message will describe the particular situation and which

41、 lines are affected. Those lines must then be traced on the UUT until the situation causing those lines to be faulty is found. III. Learn At this point, the 9010A should be plugged into a known good UUT and the BUS TEST should have come back with a message OK. LEARN can now be properly executed to p

42、rovide documentation for the UUT. A. Learn Fail When an error occurs during LEARN, the 9010A logs that fact. The operator may attempt to troubleshoot the error or continue with the LEARN. If LEARN is continued, the display LEARN FAIL comes up as a reminder of the failure during the learn process. Th

43、is message does not mean that the attempted LEARN was faulty, only that a driveability error of some kind occurred. However, if a failure occurs during the LEARN operation, LEARN parameters may be incorrect. B. Fatal Abort LEARN has a finite amount of memory space in which to store its descriptors.

44、(It can store up to 100 descriptors.) In the verb rare case when the allocated memory space is deplcted, LEARN stops vith the message I:ATAL ABORT. The user mav be able to accomplish a successful LEARfi b! selectively LEARNing sections of address space, or the information may be entered manually usi

45、ng the VIEW function. IV. View Once LEARN is complete, the VIEW keys can he used to look at the information which was acquired during the LEARN process. Remember V. that LEARN often acquires many lines of information. If the MORE annunciator is flashing, select the MORE key for the next line of info

46、rmation. A. B. C. D. Finding Nothing Sometimes UUTs are designed with energy-saving switches to turn off power to memory devices on the board when not in use. In some cases, the power switch may be controlled by an I/O port requiring a certain value to be written out using the WRITE key. Finding Man

47、y Small Sections of I/O When LEARN is interfered with, strange results can occur. If the UUT has a watchdog timer that is connected to the RAM and not disabled, LEARN will set many small sections of I/O. In this case, UUT documentation should be checked for timers and reset circuitry. Does Not Find

48、All I/O Locations LEARN is limited in its abilitv to find all I/O locations. Only those locaiions with at least one bit readjwriteable will be found. Therefore, read only I/O, and write only I/O will be missed. If UUT documentation exists, these locations may be tested manually. False ROM Occasional

49、ly, a PIA or PI0 will power up in a strange mode on a UUT. When this occurs, LEARN will see those locations as read-only locations and report them as ROM. The VIEW function can be used to deliminatc any extraneous descriptors (CLEAR). Preprogrammed Tests Upon completion of LEARN, the ncccssarb address parameters are stored in the 90lOhs memory for the preprogrammed tests. Any test selection and ENTER will perform that test over the address ranges stored. If an error occurs, the 9010A will halt and inform the user of the UU? error. For more extensive information, bee section 4H of the 9010A