8035XA Ops Manual_REVF 电路图.pdf

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1、Giga-tronics Incorporated v 4650 Norris Canyon Road v San Ramon, California 94583 925.328.4650 or 800.726.4442 v 925.328.4700 (Fax) v 800.444.2878 (Customer Service) v 925.328.4702 (CS Fax) .Certified ProductISO 9001. Certified Process Registrar: BSI, Certification No. FM 34226 v Registered 04 June

2、1996 v Amended 01 March 2000 Manual Part Number: Revision: Print Date: Series 8035XA Peak Power Sensors Operation 80351A = 100 x larger, 80352A = 1000 x larger Zero Set: 1.0 mW, Peak; 0.05 mW, CW Zero Drift: 1.0 mW, Peak 0.05 mW, CW in 1 hour at constant temperature, 24 hour warmup Noise Uncertainty

3、: 1.0 mW, Peak; 0.05 mW, CW at constant temperature, measured over a 1 minute interval, 24 hour warmup Sample Delay Timing Delay Range:-20 ns to 104 ms Delay Resolution:0.5 ns Delay Jitter:2.0 ns Trigger Level Set Range: Internal:-30 to +20 dBm Resolution:0.01 dB External:0.0V to 4.0V Resolution to

4、0.01V Trigger Jitter: 2.0 ns Settling Time:(50% to within 3%) 500 s) as shown in Figure 2-12. Figure 2-12: Pulse Profile and Sample Delay Test Setup Use the Sample Delay output as an oscilloscope trigger source. This waveform rises at the trigger point and falls at the sample point; thus, it provide

5、s both a stable scope trigger source and a precise indicator of the trigger point and sample point. The time length of the sample delay pulse is the sum of the sample delay which is displayed on the Series 8540 power meter front panel, and the sample delay offset which is available through the menu.

6、 Series 8035XA Peak Power Sensors 2-12Manual 21568, Rev. F, March 2008 2.3.7Sample Delay Offset In addition to compensating for delay line triggering variations or external triggering cables, sample delay offset can be used to set a 0.0 ns time reference point after the trigger point (see Figure 2-1

7、3). Figure 2-13: Sample Delay total = sample delay + sample delay offset total = 20,000s + 0.120s = 200 120s total = 200,000s + (-0.010s) = 199.990s t t t or total t The use of a digital oscilloscope can permit better viewing of data. There are two small markers injected onto this waveform. The firs

8、t is a small triggering marker which is added slightly after the trigger point. The second marker on the waveform is the sample marker. The sample marker is located slightly behind the actual sample point. There may be small markers at the end of the sample transfer and when the trigger signal occur

9、s. Because the visibility of these markers varies greatly with signal level and horizontal sweep rate, the use of the SAMPLE DELAY output is recommended. In Figure 2-14, triggering occurs at the frame start of a pulsed TDMA communications signal. The trigger level is set such that triggering can onl

10、y occur on the highest amplitude pulse; this provides stable triggering. A sample delay offset is used to set a 0.0 ns reference point at the start of the third data burst pulse. Figure 2-14: Using SD to Offset a 0 ns Time Reference Detector Out Connection Sample Delay Offset Sample Delay Sample Del

11、ay Internal Trigger Level Sample Delay Connection Operation Manual 21568, Rev. F, March 2008 2.3.8Measuring Pulse Droop Pulse characteristics such as droop, ripple, and overshoot can be measured quickly using referenced measurements. This involves the use of the front panel REL key for the Series 85

12、40 power meter users, or the CALC#:REF:COLL function for 58542 power meters. 1.Connect the 8035XA Peak Power Sensor to the power meter and the CALIBRATOR output. 2.Press CAL/ZERO to calibrate the sensor to the meter. 3.Upon successful completion of power sweep calibration, connect the sensor to a pu

13、lsed signal source. The power level must be above the trigger level. 4.Connect the 8035XA Detector Out and Sample Delay leads to a digital oscilloscope. 5.Set the sample delay (DLYA) to the t1 position just after the rising edge as shown in Figure 2-15. 6.Press REL. The display should now read appro

14、ximately 0.00 dBm or 100%. 7.Set the sample delay to the t2 position just before the falling edge of the pulse. The display is now reading the pulse-top amplitude variation. Figure 2-15: SD Setting for Measuring Pulse Droop Detector Out Trigger Level t1 t2 Series 8035XA Peak Power Sensors 2-14Manual

15、 21568, Rev. F, March 2008 2.3.9Measuring 3 dB Pulse Width Pulse width and other pulse timing parameters can be measured using the REL key and the sample delay offset control (see Figure 2-16). 1.Preset the delay offset to 0 nS. 2.Set the sample delay equal to about half the pulse width. 3.Press REL

16、 to set the 0.0 dB reference level (100% for Watts display). 4.Set the sample delay to a position on the rising edge of the pulse. Increment or decrement the sample delay value until the power level display reads approximately -3.00 dBr. 5.Remember or write down the sample delay value. 6.Press MENU,

17、 and use the up/down arrow keys to display SETUP MENU. Press ENTER. Select PEAK SNSR SETUP, then select the current triggering method (INT or EXT). When DLY Offset appears, set the offset value to the same time value from Step 4. This sets the 3 dB down time point to a 0.0 ns reference position. 7.P

18、ress ENTER to return to the measurement display. 8.Set the sample delay to a position on the falling edge of the pulse. Increment or decrement the sample delay value until the display again reads approximately -3.00 dBr. The sample delay currently displayed is the signals 3 dB pulse width. Figure 2-

19、16: Using SD to Measure a 3 dB Pulse Width 100% Reference Level 3 dB down (50%) 3 dB down (50%) Sample Delay Offset Total Delay Trigger Level Sample Delay = Pulse Widtht t= Operation Manual 21568, Rev. F, March 2008 2.3.10Measuring Rise-Time Rise time measurements can be performed using a technique

20、similar to the pulse width measurement. This example uses a linear Watts display readout rather than the more common logarithmic dBm readout for convenient identification of the 10% and 90% levels. 1.Preset the delay offset to 0 ns. 2.Press dBm/mW to obtain a linear, Watt, display readout. 3.Set the

21、 sample delay equal to about half the pulse width. 4.Press REL to set the 100% reference level. 5.Set the sample delay to a position on the rising edge of the pulse. Increment or decrement the sample delay value until the power level display reads approximately 10%. 6.Remember or write down the samp

22、le delay value. 7.Press MENU. Select SETUP MENU then PEAK SNSR SETUP. Proceed to the SAMPLE DELAY OFFSET selection. Set the offset value to the same value from Step 6. 8.Return to the measurement display and increment the sample delay until the display reads approximately 90%. The sample delay curre

23、ntly displayed is the 10% to 90% rise time. 2.4GPIB Commands These commands supplement the commands given in the Series 8540C Universal Power Meter Operation and Maintenance Manual. 2.4.1Setting Trigger Modes These commands set the trigger method for the 8035XA sensor. The sensor can be set to trigg

24、er on the rising RF envelope of the power signal. This is the internal trigger mode. An external TTL trigger can be used, or the sensor can “free run” and allow a CW measurement mode with no trigger required. The terms digital filter (as used in some instrument instructions) and averaging buffer (as

25、 used here) are interchangeable. Examples: OUTPUT 713;PEAK A INT TRIG -10.00! Configure sensor A for internal trigger at ! -10.00 dBm trigger level OUTPUT 713;PEAK B EXT TRIG 1.50! Configure sensor B for external trigger at ! 1.50 Vdc trigger level OUTPUT 713;PEAK A CW! Configure sensor A for CW mea

26、surements In this example, the address 713 means Type 7 GPIB instrument, and address 13 for the power meter. The GPIB control command (the portion to the left of the semicolon) may vary. Trigger Modes With a Peak Sensor Series 8035XA Peak Power Sensors 2-16Manual 21568, Rev. F, March 2008 Examples:

27、OUTPUT 713;TR3! Last measured value will be returned OUTPUT 713;TR2! Refill averaging buffer before measurement display OUTPUT 713;TR1! Wait for trigger before returning measurement OUTPUT 713;TR0! Measure, but no display TR0 The meter will measure power, but the display of measured data will be sup

28、pressed and the GPIB bus will not be updated with measurement data. TR1 This mode will wait until the sensor triggers before returning a measurement. The measurement returned will be after the application of any averaging. The display for the channel will follow the TR1 mode. When TR1 is received ov

29、er the bus, NO TRIG will be displayed until the sensor has triggered and measurement data is available. TR2 This mode will wait until enough measurements are made to completely refill the averaging buffer. The measurement returned will be the average of all measurements in the buffer. MEAS* will dis

30、play with one of the asterisk lines rotating for each measurement) while the averaging buffer is being filled. TR3 The last measured value will be returned. This mode will not wait for the peak sensor to trigger. 2.4.2Setting Delays When the sensor is configured for internal triggering, the delay fr

31、om trigger to measurement sample must be set. The valid range of delays is -20 ns to 100 ms, expressed in a floating point number. The smallest delay increment is 0.5 ns. Setting delays in CW trigger mode are invalid and ignored. Examples: OUTPUT 713;PEAK A DELAY 1.20E-6! Configure sensor A for a de

32、lay of 1.20 s OUTPUT 713;PEAK B DELAY 33.5E-9! Configure sensor B for a delay of 33.5 ns The offset command adds a known offset to the trigger delay value. The actual value of delay would be the DELAY set plus the OFFSET set. The default value of offset is 0. The valid range of offset is -20 ns to 1

33、00 ms, expressed in a floating point number. Example: OUTPUT 713;PEAK A OFFSET 1.00E-6! Configure sensor A for a delay offset of 1.00 s Operation Manual 21568, Rev. F, March 2008 2.4.3Reading Values These commands read the current settings of delay or offset. Examples: OUTPUT 713;PEAK A?! Query the

34、current sensor A trigger setting ENTER 713;TRIG$! Query the trigger mode setting of the sensor, and return: CW or INT_TRIG or EXT_TRIG OUTPUT 713;PEAK A DELAY?! Query the current sensor A delay setting ENTER 713;Delay OUTPUT 713;PEAK B OFFSET?! Query the current sensor B offset ENTER 713;Offset Seri

35、es 8035XA Peak Power Sensors 2-18Manual 21568, Rev. F, March 2008 2.4.4Commands for the 58542 The following peak power sensor GPIB commands are used with the Model 58542 VXI Universal Power Meter. Refer also to the Model 58542 Operation and Maintenance Manual for additional details. SENSe:TRIGger:SO

36、URce This command sets the sensor (1 or 2) peak trigger mode to either the INTernal, EXTernal, or CW mode. SENSe:TRIGger:DELay:MAGnitude This command sets the sensor (1 or 2) peak delay value to any desired time from -20e-9 to 100e-3 seconds, with 1e-6 seconds being the default setting. SENSeTRIGger

37、:OFFSet:MAGnitude This command sets the sensor (1 or 2) trigger offset time to any desired value from -20e-9 to 100e-3 seconds, with 0 seconds being the default setting. SENSeTRIGger:LEVel:MAGnitude When the INTernal trigger mode is in use, this command sets the trigger level to any desired power le

38、vel setting from -30 to +20 dBm. Default is -20 dBm. SENSeTRIGger:LEVel:MAGnitude When the EXTernal trigger mode is in use, this command sets the trigger level to any desired voltage level from -0.100 to 5.000 V. Default is 1.700 V. Manual 21568, Rev. F, March 2008 3 Theory of Operation 3.1Introduct

39、ion This chapter describes the electrical operation of the Series 8035XA Peak Power Sensors. Refer to the block diagram in Figure 3-1 to follow the general function of the sensor. The RF signal is rectified in the sensor element, and the video envelope is buffered and delayed by the input amplifier

40、and delay buffers. This buffered envelope is available at the Detector Out connector. The Track and Hold (T&H) function tracks and follows the signal and then holds it for hundreds of microseconds. The Sample and Hold (S&H) function acquires the S&H output and holds it for hundreds of milliseconds.

41、The timing circuitry generates the sample pulses from the trigger input or, if the sensor is in the free run mode, from an internal oscillator. The block diagrams, circuit descriptions, and the troubleshooting information in Chapter 4 are written around the circuit test points. The delay lines shown

42、 in Figure 3-1 are illustrated in the Analog Timing Diagram in Figure 3-3. Delay lines match the delay through the analog channel to the sample point, and the delay through the timing circuitry to the sample generator. Since fixed lumped constant delay lines are used, the match is not perfect. The d

43、elay through the Series 8035XA Peak Power Sensors 3-2Manual 21568, Rev. F, March 2008 INTernal trigger is slightly longer than the delay through the EXTernal trigger due to the delay of the input differential preamp. Figure 3-1: 8035XA High Level Block Diagram 3.2Analog Assembly Description Refer to

44、 Figure 3-2, the Analog Timing Diagram in Figure 3-3, and schematic diagram #21351 in Chapter 7 to follow the discussion of the Analog PC assembly circuit operation. The rectified signal from the detector goes into the resistors R1 or R2 (TP1 and TP2). The signal sees 2 k to ground from either input

45、 (the negative input sees 2 k to a virtual ground inside R100). R3 helps to balance the input bias current. U1 and U2 delay the signal so the trigger output and video output may be viewed close together. U4 and U5 are buffers for the delay lines (TP3). Theory of Operation Manual 21568, Rev. F, March

46、 2008 U10C and U7A provide a fast Track and Hold (T&H). U7A buffers the T&H capacitor C21, and U7B buffers the S&H capacitors, C1 & C2. Figure 3-2: Analog PC Assembly Block Diagram A track and hold differs from a sample and hold in the manner in which the signal prior to the hold is manipulated. In

47、a sample and hold, the sample gate turns on and the holding capacitor is charged to the signal potential, then the sample gate turns off and the hold capacitor maintains the value of the input at the time of the sample. In a track and hold circuit, the voltage on the hold capacitor is the same as th

48、e input (tracks) until the track gate goes off, after which the level is held until the track goes on and the hold capacitor again follows the input. The INTernal or EXTernal trigger source is selected by U10D and U11A. U11B functions as an inverter for HIGHGAIN. U6 amplifies the trigger signal by 1

49、 or 41. Trigger DAC U9 is loaded with a count from the serial chain. The DAC needs the data signal held after the clock for at least 80 ns. A2R12 and A2C25 on the Digital board take care of that requirement. That count gets translated into a voltage between -0.1 V and about +5 V by U8A. Digital board comparator A2U18 provides the TRIG-IN pulse (A2TP25). A2R42 provides hysteresis for A2U18. * NOTE: All times shown in Figure 3-3 are referenced to TP3, and are not to scale.