Rohde & schwartzSML_SHB_BD2_03 Service part 2 电路图.pdf

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1、1090.3123.2422E-3 Test and Measurement Division Service Manual SIGNALGENERATOR SML01 1090.3000.11 SML02 1090.3000.12 SML03 1090.3000.13 Volume 2 Service manual consists of 2 volumes Printed in the Federal Republic of Germany RadioFans.CN 收音机爱 好者资料库 RadioFans.CN 收音机爱 好者资料库 SMLTabbed Divider Overview

2、1090.3123.24REE-2 Tabbed Divider Overview Safety Instructions Certificate of Quality Support Center Address List of R ID = 250 mA Verstrkung ca. 10 dB 6.2.4 Steuerschnittstelle Stromlauf Blatt 5, 6 ber die 20polige Steckerleiste X381-11.20 werden die Steuerbits ber Durchfhrungsfilter Z3.Z5 und Z11.Z

3、14 auf die Baugruppe gefhrt. Bei Anliegen des Modul-Select-Signals MS_PULS_N (Low-Aktiv) werden die Daten seriell in die Schie- beregister D8.D10 eingelesen und mit dem Strobe-Signal STROBE_MOD in die Ausgangsregister bernommen bzw. an das FPGA bergeben. Im EEPROM D1 sind Variante, nderungszustand u

4、nd Baugruppenkennung eingespeichert. V15 dient als Pegelwandler von 3,3 V.5 V. VDIAG_MOD fhrt eine analoge Diagnosespannung von 2,5 V.+2,5 V zur weiteren Auswertung auf das Mainboard. Der Multiplexer D5 ermglicht die Auswahl zwischen 8 verschiedenen Diagnosepunkten. SMLPulsmodulator 1090.5410.00D-16

5、.3 6.3 Ausbau des Pulsmodulators Achtung! Befolgen Sie bitte genau die Anweisungen der folgenden Abschnitte, damit eine Be- schdigung des Gerts oder eine Gefhrdung von Personen vermieden wird. Beach- ten Sie bitte auch die allgemeinen Sicherheitshinweise am Anfang dieses Handbuchs. Zum ffnen des Pul

6、smodulators verfahren Sie wie folgt: ffnen des Gertes? Das Gert hochkant auf die beiden Griffe stellen und die vier Schrauben in den Gertefen lsen. Die Gertefe lassen sich nun entfernen. ? Den Gehusetubus vorsichtig nach oben abziehen. Gert ist nun offen. Baugruppe ausbauen und ffnen ? Alle Steckver

7、bindungen auf der Baugruppe lsen. ? HF-Kabel von X382 / X383 abschrauben. ? HF-Kabel von X384 /X385 abstecken. ? Die Befestigungsschrauben (Kreuzschlitz) des Pulsmodulators lsen. Baugruppe kann jetzt herausgenommen werden. ? Die Schirmdeckel der Baugruppe knnen nun abgeschraubt werden. ? Zur Fehlers

8、uche kann die Baugruppe in der sogenannten Service- stellung betrieben werden. Dazu sind alle Steckverbindungen wieder herzustellen und die HF-Kabel falls notwendig durch flexible Ausfh- rungen zu ersetzen. Einbau? Schritte in umgekehrter Reihenfolge wie oben beschrieben aus- fhren. PulsmodulatorSML

9、 1090.5410.006.4D-1 6.4 Spezielle Megerte und Hilfsmittel Eine Liste der fr den SML hufig gebrauchten Megerte und Hilfsmittel befindet sich am Anfang die- ses Handbuchs. Die in der folgenden Tabelle aufgelisteten Gerte sind speziell zum Prfen und zum Abgleich des Pulsmodulators erforderlich. Tabelle

10、 6-1 Megerte Pos.GerteartErforderliche Eigen- schaften Geeignetes R ID = 250 mA Gain approx. 10 dB 6.2.4 Control Interface Circuit diagram sheet 5, 6 The 20-contact multi-point connector X381-11 to 20 is used to apply the control bits via lead-through filters Z3 to 5 and Z11 to 14 to the module. Whe

11、n the module select signal MS_PULS_N (Low active) is applied, the data is serially read into shift registers D8 to D10 and transferred into the output registers or to the FPGA using the strobe signal STROBE_MOD. EEPROM D1 contains the version, revision and module identification. V15 is used as level

12、 converter from 3.3 V ? 5 V. VDIAG_MOD takes an analog diagnostic voltage of 2.5 V to +2.5 V to the mainboard for further analy- sis. Multiplexer D5 permits to select between 8 different diagnostic points. SMLPulse Modulator 1090.5410.006.3E-1 6.3 Removing the Pulse Modulator Caution! Make sure to o

13、bserve the instructions given in the following in order not to cause damage to the instrument or endanger anybody. Please also note the general safety instructions at the beginning of this manual. To open the Pulse Modulator proceed as follows: Opening the instrument? Put the instrument on end on th

14、e two handles and loosen the four screws in the instrument feet. The instrument feet can be removed now. ? Carefully lift off the instrument tube. The instrument is open now. Removing and opening the module ? Loosen all plug-in connections on the module. ? Unscrew RF cable from X382 / X383. ? Discon

15、nect RF cable from X384 /X385. ? Loosen the fixing screws (Phillips) of the pulse modulator. The module can be removed now. ? The screening covers of the module can be unscrewed now. ? For troubleshooting, the module can be operated in the so-called service position. For this purpose, restore all pl

16、ug-in connections and replace the RF cables by flexible ones, if necessary. Replacement? Proceed in the reverse order to the steps described above. Pulse ModulatorSML 1090.5410.006.4E-1 6.4 Special Measuring Instruments and Accessories A list of the measuring instruments and accessories frequently r

17、equired for the SML is to be found at the beginning of this manual. The instruments listed in the following table are required in particular for test- ing and adjustment of the Pulse Modulator. Table 6-1 Measuring instruments ItemType of instrumentSpecificationsSuitable R thus, the amplitude modulat

18、or that follows can always be operated in its optimum working point. An internal calibration routine LEVEL PRESET determines the setting values of the DAC for the preset element (V_PRESET). The subsequent modulation stage can be switched over between the internal AM modulator and an external add-on

19、I/Q modulator (IQMOD, 2084.4692.xx or 2084.5218.xx). The internal AM modulator provides a dynamic range of approx. 45 dB as well as low synchronous phase modulation. The output amplifier must supply a very high output level of up to +27 dBm due to the high insertion loss of the subsequent circuitry

20、(in particular, the external attenuator connected downstream). SMLOutput Unit 1090.4007.007.5E-2 Following lowpass filtering with a cutoff frequency of 3.5 GHz, a directional coupler functions as test point for level control (ALC). It is followed by the second GaAs switch of the detour line. The det

21、ector with a linear dynamic of approx. 30 dB in conjunction with an ALC is provided to set the exact output level and generate the AM. The stored calibration data provide for the linear operation of the detector via a D/A converter in dependence of the frequency such that the level is continuously r

22、educed by 25 dB. The command variable for the level (incl. AM modulation signal) is provided by the mainboard of the SML. 7.2.1 Control Interface and 30 V Generator Circuit diagram 1090.4007.01S, sheet 2 Connector X321 supplies the operating voltages, the digital control signals (see section 7.2.2)

23、and various special control lines for the OPU 3. The five operating voltages are filtered using sufficiently dimensioned chokes and electrolytic capacitors followed by feedthrough filters to suppress the RF. The digital control signals MS_OPU3_N, STROBE_N, SERDATA_N, EEDATA, SERCLK_N and EECLK_N are

24、 described in detail in the following chapter. The output signal MI_ALC2 is an interrupt signal which has a high logic level (+3.3 V) when the level control (ALC) can no longer maintain the output level. V_DIAG passes an analog diagnosis voltage of 2.5 V to +2.5 V to the SML mainboard for further ev

25、aluation. The multiplexers D3 and D4 allow selection from 16 different diagnosis test points. Since V_DIAG is a common line for all units in the Signal Generators SML, SMV or SFL-S, only one test point may be through-connected at a time. The other units then connect their diagnosis multiplexers to h

26、igh impedance. The BLANK signal allows for faster blanking of the RF output level in case of frequency or RF level variations. The reference level is input via the LEV_EXT connector in the OPU3 and is used for level setting as well as for AM modulation with an AF bandwidth of 50 kHz. The DC level of

27、 LEV_EXT is between 0 V and -5 V. From modification status 07.00 or higher, the OPU3 is equipped with a 30 V DC/DC converter to provide for a higher tuning voltage for bandpass filter tuning. It consists of the step-up control U4 and is effectively decoupled by the pre- and post-connected LC section

28、s in order to remove noise voltages from the signal processing unit of the OPU3. Output UnitSML 1090.4007.007.6E-2 7.2.2 Shift Registers & EEPROM Circuit diagram 1090.4007.01S, sheet 3 The OPU3 settings are made using shift registers. SERDATA_N, SERCLK_N and STROBE_N signals are therefore routed via

29、 the 26-pin multi-connector X321 to the board. Since SERDATA_N, SERCLK_N and STROBE_N lead to various external modules of the SML, there is a specific module-select signal MS_OPU3_N which provides for through-connection of the three signals via the NOR gate D2. The signals DATA, WR and CLK pass via

30、the feed-through filters Z4, Z6 and Z8 to the shift registers D8 to D12 and the 12-bit DAC D13. When applying the module-select signal MS_OPU3_N (low-active) the data are serially read in the shift registers D8 to D12 and in the 12-bit DAC D13 and strobed into the output registers by the signal STRO

31、BE_N. Section 7.6.4 lists the bits and their functions in table 7-18. D1 is the EEPROM which contains the module data (board identification OPU3, serial No., modification status, model and other manufacturing data) and the calibration data. Jumpers X1 and X2 provide for direct access to the EEPROM v

32、ia I2C bus (SCL and SDA), if necessary. The signal line EEDATA passes the read and write data (bi-directional). The SDA output of the EEPROM is an open-drain output and routes directly to the interface X321. A common pull-up resistor for the EEDATA line is provided on the SML mainboard. SCL is the c

33、lock input for clocking in and out data into the component. It is masked via NOR gate D2 by the module-select signal MS_OPU3_N such that a I2C clock signal passes to the EEPROM only with access to OPU3. Dat Clock HCT 4094 Strobe Data Clock SERDATA_N SERCLK_N Strobe_N MS_OPU3_N EEDATA 1 1 1 1 EEPROM

34、EECLK_N Fig. 7.2.2 Serial data interface of the Output Unit 2 GHz / 3 GHz SMLOutput Unit 1090.4007.007.7E-2 7.2.3 Diagnosis Multiplexer, Temperature Sensor, . Circuit diagram 1090.4007.01S, sheet 4 The diagnosis multiplexer D3 and D4 selects one out of 16 diagnosis voltages. The DMUX0_ON and DMUX1_O

35、N signals select the corresponding 8-bit multiplexer. The inverters D5 in these lines make it impossible to activate D3 or D4 after power-up and prior to initialization of the shift registers, since all diagnosis voltages - even those of other modules - are routed to the mainboard via line V_DIAGVD.

36、 D3 and D4 are operated by the +3.3 V supply and by a negative supply voltage of approx. -2.7 V, which is generated by the Zener diode V46 and the series resistor R246. The temperature sensor U5 measures the internal temperature of the module and outputs it via D_TEMP at 10 mV/oC. Example: +40 oC co

37、rresponds to 0.40 V on D_TEMP. The logic of BLANK, BLANK_ENA, BLANK_NORM and LEV_OFF provides for carrier switch-off. LEV_OFF switches off the carrier with HIGH level, if BLANK_ENA = 0. If BLANK_ENA = 1, the BLANK input becomes active: with BLANK_NORM = 0 LEV_OFF switches off only if the BLANK input

38、 is set to 0. With BLANK_NORM = 1 LEV_OFF switches off only if the BLANK input is set to 1. Table 7-3 Interaction of the BLANK signals with LEV_OFF and KLEMM_DOWN BLANKBLANK_E NA BLANK_NO RM LEV_OF F KLEMM_DOW N Remark x0 x00 x0 x11If BLANK_ENA = 0, then LEV_OFF is immediately effective 01000 01011

39、11000 11010 If BLANK_ENA = 1 and BLANK_NORM = 0, then LEV_OFF = 1 is effective only if BLANK = 0 01100 01110 11100 11111 If BLANK_ENA = 1 and BLANK_NORM = 1, then LEV_OFF = 1 is effective only if BLANK = 1 The circuit with comparator U3 is for monitoring the ALC amplitude control loop: if the contro

40、l voltage V_AMOD (see sheet 22) exceeds +9.4 V, output pin 1 of U3 assumes 0 V and the RC section R102, C8 initiates the interrupt signal ALC_INT with delay via D5. A high level (+3.3 V) indicates the interrupt. If the loop can no longer control the level, a message will be sent to the processor on

41、the SML mainboard via the interrupt. Output UnitSML 1090.4007.007.8E-2 7.2.4 Voltage Control Circuit diagram 1090.4007.01S, sheet 5 N11 provides a precise, non-adjusting reference voltage +10.0 V for all internal voltage regulators. After buffering by means of N29 the reference voltage passes to the

42、 five regulators for the internal operating and reference voltages. These voltages can be centrally measured at X5. Table 7-7 in section 7.5.4 lists the rated values. Besides, all of the five supply voltages generated internally can be measured using the diagnosis multiplexer. They are then divided

43、using voltage dividers to the V_DIAG voltage range of -2.5 V to +2.5 V. With display on the SML, however, these divisors are taken into account such that the non- divided voltages are displayed (see section 7.5.1). The two series resistors R276 and R121 reduce the +24 V at the collector of V106 in o

44、rder to reduce the thermal load of the transistor. The collector voltage of V106 should always be 1 V to 2 V above the +17.5 V output voltage of the +17 V regulator. 7.2.5 D/A Converter Circuit diagram 1090.4007.01S, sheet 6 The D/A converters U1, U2 and D13 (see sheet 3) generate the control voltag

45、es for the tunable bandpasses (sheets 10 to 15), the detector linearization (sheet 21) and the pin-diode preset element (see sheet 16). Sections 7.5.8, 7.5.12 and 7.5.9 mention the output voltages of these three DAC stages for troubleshooting. 7.2.6 GaAs FET Switch Circuit diagram 1090.4007.01S, she

46、ets 7 and 20 The GaAs FET switch D15 (sheet 7) and its counterpart D18 (sheet 20) connect the input socket X322 and the output socket X323 via the reverse-biased shorting diodes V83 and V84 to generate a path to the RF output for the frequency range from 9 kHz to 1210.5 MHz. C167 and C170 provide fo

47、r the necessary DC isolation and are adapted to 50 via L91, L134 or L137, L93. L136 is used to match the diodes V83 and V84. The control voltages of the RF switches D15 and D18 - measured on the control lines +8V_BRIDGED and -8V_BRIDGED - are +4.2 V and -8.2 V. If one of the lines carries +4.2 V, th

48、e other one carriers -8.2 V. These potentials change line with switchover. The two voltage values are supplied by the opamps N7 and can be measured at the amplifier outputs: N7.7. +8.0 V, N7.1: -8.2 V. With operation of the OPU3, the voltage passes via RF1 to the step recovery multiplier (see subseq

49、uent section). The PIN diodes V83 and V84 short-circuit the direct path to prevent crosstalk between the RF input X322 and the RF output X323. These shorting diodes are controlled by N24. With OPU3 bypassed the voltage measured at C289 is approx. -9.5 V. With OPU3 active it is +8.1 V The input level with OPU3 active is approx. +15 dBm, since the 1.2 GHz output unit of the SML mainboard (= OPU1) is clamped to this value. SMLOutput Unit 1090.4007.007.9E-2 7.2.7 SRD Multiplier Circuit diagram 1090.4007.01S, sheet 8 The RF1 signal is either switched to the