ad7524电路图.pdf

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1、REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or ot

2、herwise under any patent or patent rights of Analog Devices. a CMOS 8-Bit Buffered Multiplying DAC AD7524 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700Fax: 617/326-8703 FEATURES Microprocessor Compatible (6800, 8085, Z80, Etc.) TTL/CMOS Compatible Inputs On-Chip

3、 Data Latches Endpoint Linearity Low Power Consumption Monotonicity Guaranteed (Full Temperature Range) Latch Free (No Protection Schottky Required) APPLICATIONS Microprocessor Controlled Gain Circuits Microprocessor Controlled Attenuator Circuits Microprocessor Controlled Function Generation Precis

4、ion AGC Circuits Bus Structured Instruments GENERAL DESCRIPTION The AD7524 is a low cost, 8-bit monolithic CMOS DAC designed for direct interface to most microprocessors. Basically an 8-bit DAC with input latches, the AD7524s load cycle is similar to the “write” cycle of a random access memory. Usin

5、g an advanced thin-film on CMOS fabrication process, the AD7524 provides accuracy to 1/8 LSB with a typi- cal power dissipation of less than 10 milliwatts. A newly improved design eliminates the protection Schottky previously required and guarantees TTL compatibility when using a +5 V supply. Loadin

6、g speed has been increased for compatibility with most microprocessors. Featuring operation from +5 V to +15 V, the AD7524 inter- faces directly to most microprocessor buses or output ports. Excellent multiplying characteristics (2- or 4-quadrant) make the AD7524 an ideal choice for many microproces

7、sor con- trolled gain setting and signal control applications. FUNCTIONAL BLOCK DIAGRAM ORDERING GUIDE TemperatureNonlinearityPackage Model1Range(VDD = +15 V)Option2 AD7524JN40C to +85C1/2 LSBN-16 AD7524KN40C to +85C1/4 LSBN-16 AD7524LN40C to +85C1/8 LSBN-16 AD7524JP40C to +85C1/2 LSBP-20A AD7524KP4

8、0C to +85C1/4 LSBP-20A AD7524LP40C to +85C1/8 LSBP-20A AD7524JR40C to +85C1/2 LSBR-16A AD7524AQ40C to +85C1/2 LSBQ-16 AD7524BQ40C to +85C1/4 LSBQ-16 AD7524CQ40C to +85C1/8 LSBQ-16 AD7524SQ55C to +125C1/2 LSBQ-16 AD7524TQ55C to +125C1/4 LSBQ-16 AD7524UQ55C to +125C1/8 LSBQ-16 AD7524SE55C to +125C1/2

9、LSBE-20A AD7524TE55C to +125C1/4 LSBE-20A AD7524UE55C to +125C1/8 LSBE-20A NOTES 1To order MIL-STD-883, Class B processed parts, add/883B to part number. Contact your local sales office for military data sheet. For U.S. Standard Military Drawing (SMD) see DESC drawing #5962-87700. 2E = Leadless Cera

10、mic Chip Carrier: N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. RadioFans.CN 收音机爱 好者资料库 REV. B2 AD7524SPECIFICATIONS Limit, TA = +258C Limit, TMIN, TMAX1 ParameterVDD = +5 V VDD = +15 V VDD = 5 VVDD = +15 VUnitsTest Conditions/Comments STATIC PERFORMANCE Resolution8888Bits

11、Relative Accuracy J, A, S Versions1/21/21/21/2LSB max K, B, T Versions1/21/41/21/4LSB max L, C, U Versions1/21/81/21/8LSB max MonotonicityGuaranteed GuaranteedGuaranteedGuaranteed Gain Error22 1/21 1/43 1/21 1/2LSB max Average Gain TC340104010ppm/CGain TC Measured from +25C to TMIN or from +25C to T

12、MAX DC Supply Rejection,3 Gain/VDD0.080.020.160.04% FSR/% maxVDD = 10% 0.0020.0010.010.005% FSR/% typ Output Leakage Current IOUT1 (Pin 1)5050400200nA maxDB0DB7 = 0 V; WR, CS = 0 V; VREF = 10 V IOUT2 (Pin 2)5050400200nA maxDB0DB7 = VDD; WR, CS = 0 V; VREF = 10 V DYNAMIC PERFORMANCE Output Current Se

13、ttling Time3 (to 1/2 LSB)400250500350ns maxOUT1 Load = 100 , CEXT = 13 pF; WR, CS = 0 V; DB0DB7 = 0 V to VDD to 0 V. AC Feedthrough3 at OUT10.250.250.50.5% FSR maxVREF = 10 V, 100 kHz Sine Wave; DB0DB7 = at OUT20.250.250.50.5% FSR max0 V; WR, CS = 0 V REFERENCE INPUT RIN (Pin 15 to GND)45555k min 20

14、202020k max ANALOG OUTPUTS Output Capacitance3 COUT1 (Pin 1)120120120120pF maxDB0DB7 = VDD; WR, CS = 0 V COUT2 (Pin 2)30303030pF max COUT1 (Pin 1)30303030pF maxDB0DB7 = 0 V; WR, CS = 0 V COUT2 (Pin 2)120120120120pF max DIGITAL INPUTS Input HIGH Voltage Requirement VIH+2.4+13.5+2.4+13.5V min Input LO

15、W Voltage Requirement VIL+0.8+1.5+0.5+1.5V max Input Current IIN111010A maxVIN = 0 V or VDD Input Capacitance3 DB0DB75555pF maxVIN = 0 V WR, CS20202020pF maxVIN = 0 V SWITCHING CHARACTERISTICS Chip Select to Write Setup Time5See Timing Diagram tCStWR = tCS AD7524J, K, L, A, B, C170100220130ns min AD

16、7524S, T, U170100240150ns min Chip Select to Write Hold Time tCH All Grades0000ns min Write Pulse Width tWRtCS tWR, tCH 0 AD7524J, K, L, A, B, C170100220130ns min AD7524S, T, U170100240150ns min Data Setup Time tDS AD7524J, K, L, A, B, C1356017080ns min AD7524S, T, U13560170100ns min Data Hold Time

17、tDH All Grades10101010ns min POWER SUPPLY IDD1222mA maxAll Digital Inputs VIL or VIH 100100500500A maxAll Digital Inputs 0 V or VDD NOTES 1Temperature ranges as follows: J, K, L versions: 40C to +85C A, B, C versions: 40C to +85C S, T, U versions: 55C to +125C 2Gain error is measured using internal

18、feedback resistor. Full-Scale Range (FSR) = VREF. 3Guaranteed not tested. 4DAC thin-film resistor temperature coefficient is approximately 300 ppm/C. 5AC parameter, sample tested +25C to ensure conformance to specification. Specifications subject to change without notice. (VREF = +10 V, VOUT1 = VOUT

19、2 = 0 V, unless otherwise noted) RadioFans.CN 收音机爱 好者资料库 AD7524 REV. B3 ABSOLUTE MAXIMUM RATINGS* (TA = +25C, unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V, +17 V VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V VREF t

20、o GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Digital Input Voltage to GND . . . . . . . . 0.3 V to VDD +0.3 V OUT1, OUT2 to GND . . . . . . . . . . . . . 0.3 V to VDD +0.3 V Power Dissipation (Any Package) To +75C . . . . . . . . . . . . . . . . . . . . . . . . . . .

21、. . . . . 450 mW Derates above 75C by . . . . . . . . . . . . . . . . . . . . 6 mW/C Operating Temperature Commercial (J, K, L) . . . . . . . . . . . . . . . . . 40C to +85C Industrial (A, B, C) . . . . . . . . . . . . . . . . . . 40C to +85C Extended (S, T, U) . . . . . . . . . . . . . . . . . 55C

22、to +125C Storage Temperature . . . . . . . . . . . . . . . . . . 65C to +150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operatio

23、n of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic dischar

24、ge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7524 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic d

25、ischarges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. TERMINOLOGY RELATIVE ACCURACY: A measure of the deviation from a straight line through the end points of the DAC transfer function. Normally expressed as a percentage of full scale

26、 range. For the AD7524 DAC, this holds true over the entire VREF range. RESOLUTION: Value of the LSB. For example, a unipolar con- verter with n bits has a resolution of (2n) (VREF). A bipolar con- verter of n bits has a resolution of 2(n1) VREF. Resolution in no way implies linearity. GAIN ERROR: G

27、ain Error is a measure of the output error be- tween an ideal DAC and the actual device output. It is measured with all 1s in the DAC after offset error has been adjusted out and is expressed in LSBs. Gain Error is adjustable to zero with an external potentiometer. FEEDTHROUGH ERROR: Error caused by

28、 capacitive cou- pling from VREF to output with all switches OFF. OUTPUT CAPACITANCE: Capacity from OUT1 and OUT2 terminals to ground. OUTPUT LEAKAGE CURRENT: Current which appears on OUT1 terminal with all digital inputs LOW or on OUT2 terminal when all inputs are HIGH. This is an error current whi

29、ch contributes an offset voltage at the amplifier output. PIN CONFIGURATIONS DIP, SOICPLCC LCCC RadioFans.CN 收音机爱 好者资料库 AD7524 REV. B4 WRITE MODE When CS and WR are both LOW, the AD7524 is in the WRITE mode, and the AD7524 analog output responds to data activity at the DB0DB7 data bus inputs. In thi

30、s mode, the AD7524 acts like a nonlatched input D/A converter. HOLD MODE When either CS or WR is HIGH, the AD7524 is in the HOLD mode. The AD7524 analog output holds the value correspond- ing to the last digital input present at DB0DB7 prior to WR or CS assuming the HIGH state. MODE SELECTION TABLE

31、CSWRModeDAC Response LLWriteDAC responds to data bus (DB0DB7) inputs. HXHoldData bus (DB0DB7) is Locked Out: XHHoldDAC holds last data present when WR or CS assumed HIGH state. L = Low State, H = High State, X = Dont Care. WRITE CYCLE TIMING DIAGRAM Figure 3. Supply Current vs. Logic Level Typical p

32、lots of supply current, IDD, versus logic input voltage, VIN, for VDD = +5 V and VDD = +15 V are shown above. CIRCUIT DESCRIPTION CIRCUIT INFORMATION The AD7524, an 8-bit multiplying D/A converter, consists of a highly stable thin film R-2R ladder and eight N-channel current switches on a monolithic

33、 chip. Most applications require the addition of only an output operational amplifier and a voltage or current reference. The simplified D/A circuit is shown in Figure 1. An inverted R-2R ladder structure is usedthat is, the binarily weighted currents are switched between the OUT1 and OUT2 bus lines

34、, thus maintaining a constant current in each ladder leg indepen- dent of the switch state. Figure 1. Functional Diagram EQUIVALENT CIRCUIT ANALYSIS The equivalent circuit for all digital inputs LOW is shown in Figures 2. In Figure 2 with all digital inputs LOW, the refer- ence current is switched t

35、o OUT2. The current source ILEAKAGE is composed of surface and junction leakages to the substrate while the 1 256 current source represents a constant 1-bit cur- rent drain through the termination resistor on the R-2R ladder. The “ON” capacitance of the output N-channel switches is 120 pF, as shown

36、on the OUT2 terminal. The “OFF” switch capacitance is 30 pF, as shown on the OUT1 terminal. Analysis of the circuit for all digital inputs high is similar to Figure 2 however, the “ON” switches are now on terminal OUT1, hence the 120 pF appears at that terminal. Figure 2. AD7524 DAC Equivalent Circu

37、itAll Digital Inputs Low INTERFACE LOGIC INFORMATION MODE SELECTION AD7524 mode selection is controlled by the CS and WR inputs. AD7524 REV. B5 ANALOG CIRCUIT CONNECTIONS Figure 4. Unipolar Binary Operation (2-Quadrant Multiplication) Table I. Unipolar Binary Code Table Digital Input MSB LSBAnalog O

38、utput 1111 1111VREF (255/256) 1000 0001VREF (129/256) 1000 0000VREF (128/256) = VREF/2 0111 1111VREF (127/256) 0000 0001VREF (1/256) 0000 0000VREF (0/256) = 0 Note: 1 LSB = (28)(VREF) = 1/256 (VREF) MICROPROCESSOR INTERFACE Figure 6. AD7524/8085A Interface Figure 5. Bipolar (4-Quadrant) Operation Ta

39、ble II. Bipolar (Offset Binary) Code Table Digital Input MSB LSBAnalog Output 1111 1111+VREF (127/128) 1000 0001+VREF (1/128 ) 1000 00000 0111 1111VREF (1/128) 0000 0001VREF (127/128) 0000 0000VREF (128/128) Note: 1 LSB = (27)(VREF) = 1/128 (VREF) Figure 7. AD7524/MC6800 Interface AD7524AD7524 AD752

40、4 REV. B6 POWER GENERATION Figure 8. AD7524 REV. B7 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Terminal Ceramic Leadless Chip Carrier (E-20A) 1 20 4 9 8 13 19 BOTTOM VIEW 14 3 18 0.028 (0.71) 0.022 (0.56) 45 TYP 0.015 (0.38) MIN 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) BSC 0.075 (1.91)

41、 REF 0.011 (0.28) 0.007 (0.18) R TYP 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) BSC 0.200 (5.08) BSC 0.150 (3.81) BSC 0.075 (1.91) REF 0.358 (9.09) 0.342 (8.69) SQ 0.358 (9.09) MAX SQ 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) 16-Lead Plastic DIP (Narrow) (N-16) 16 18 9 0.840 (21.33) 0.745 (18.

42、93) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 20-Lead Plast

43、ic Leadless Chip Carrier (PLCC) (P-20A) 3 PIN 1 IDENTIFIER 4 19 18 8 9 14 13 TOP VIEW (PINS DOWN) 0.395 (10.02) 0.385 (9.78) SQ 0.356 (9.04) 0.350 (8.89)SQ 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) R 0.050 (1.27) BSC 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37)0.032 (0.

44、81) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.110 (2.79) 0.085 (2.16) 16-Lead Cerdip (Q-16) 16 18 9 0.310 (7.87) 0.220 (5.59) PIN 1 0.005 (0.13) MIN0.080 (2.03) MAX SEATING PLANE 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) MAX 0

45、.840 (21.34) MAX 0.150 (3.81) MIN 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 16-Lead Narrow-Body (SOIC) (R-16A) 169 81 0.3937 (10.00) 0.3859 (9.80) 0.2550 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (5.80) PIN 1 SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) BSC 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25)x 45 C542e511/86 PRINTED IN U.S.A. 8