ORBAN 9200 Manual Section 6 电路图.pdf

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1、Section 6 Technical Data pagecontents 6-2Specifications 6-5Circuit Description 6-5Overview 6-516.384MHz Oscillator and System Clocking 6-7Control Circuits 6-9User Control Interface and LED Display Circuits 6-10Input Circuits 6-13Output Circuits 6-15DSP Circuits 6-17Power Supply 6-19Parts List 6-20Ob

2、taining Spare Parts 6-27Vendor Codes 6-28Schematics, Assembly Drawings 6-47Abbreviations OPTIMOD-AM DigitalTECHNICAL DATA 6-1 RadioFans.CN 收音机爱 好者资料库 page Specifications It is impossible to characterize the listening quality of even the simplest limiter or compres- sor on the basis of the usual spec

3、ifications, because such specifications cannot adequately describe the crucial dynamic processes that occur under program conditions. Therefore, the only way to meaningfully evaluate the sound of an audio processor is by subjective listening tests. Certain specifications are presented here to assure

4、 the engineer that they are reasonable, to help plan the installation, and to help make certain comparisons with other processing equipment. Some specifications are for features that are only available on the 9200. Installation Analog Audio Input Configuration: One monophonic input. Impedance: Elect

5、ronically balanced 600 or 3.6k load impedance, jumper-selectable. Dynamic Range: 90dB. Common Mode Rejection: 70dB at 50-60Hz. 45dB at 60Hz-9.5kHz. Sensitivity: 20dBu to +20dBu to produce 10dB gain reduction at 1kHz, software- and jumper- adjustable. Maximum Input Level: +27dBu. Connector: XLR-type,

6、 female, EMI-suppressed. Pin 1 Chassis Ground, Pins 2 (+) and 3 electronically balanced, floating and symmetrical. A/D Conversion: 18-bit. Filtering: RFI-filtered. Analog Audio Output Configuration: Two monaural outputs for use with two transmitters, with separate level control and output amplifiers

7、. Source Impedance: 365, 5%, electronically balanced to ground. Load Impedance: 600 or greater, balanced or unbalanced. Termination not required. Output Level (100% peak modulation): Adjustable from 0dBu to +20dBu into 600 or greater load, with front-panel independent multi-turn potentiometers. Outp

8、ut Noise Level: 75dB (Bypass mode, referenced to 100% modulation). Distortion: 0.05% THD (Bypass mode). Connector: XLR-type, male, EMI-suppressed. Pin 1 Chassis Ground, Pins 2 and 3 electroni- cally balanced. Positive voltage on Pin 2 correlates to positive modulation. D/A Conversion: 18-bit. Filter

9、ing: RFI-filtered. 6-2 TECHNICAL DATA Orban 9200 RadioFans.CN 收音机爱 好者资料库 Digital Audio Input (Digital I/O option installed) Configuration: Two-channel per AES/EBU-standard. 20-bit resolution. Software selection of left, right, or sum as input source. Sample rate: 32, 44.1 or 48kH, automatically-sele

10、cted. Connector: XLR-type, female, EMI-suppressed. Pin 1 Chassis Ground, Pins 2 and 3 trans- former balanced and floating. Input Reference Level: Software-adjustable from 30dBFS to 20dBFS. J.17 De-emphasis: Software-selectable. Digital Audio Output (Digital I/O option installed) Configuration: Two-c

11、hannel AES/EBU-standard. 20-bit resolution. Both channels carry the same audio data. Status bits per AES3-1992 standard “single-channel mode. ” Sample rate: 32kHz, 44.1kHz, or 48kHz, software-selectable. Sync: Software-selectable for internal or external. In external, digital output is synchronous w

12、ith digital input. Connector: XLR-type, male, EMI-suppressed. Pin 1 Chassis Ground, Pins 2 and 3 transformer balanced and floating. Output Level (100% peak modulation) 0dBFS to 20dBFS, software-adjustable. Remote Control Interface Configuration: Eight opto-isolated inputs. Voltage: 6-24V AC or DC, m

13、omentary or continuous, optically-isolated. 9VDC provided to facilitate use with contact closure. Connector: DB-25 male. EMI-suppressed. Control: User-programmable, for any eight of User Presets, Factory Presets, Day, Night, Bypass, Sine, Wave Test, Analog Input, Digital Input (if Digital I/O Option

14、 installed). Power Voltage: 90-120VAC, 100-132VAC or 200-264VAC, 50-60Hz; 40VA. Connector: IEC; detachable 3-wire power cord supplied. AC is EMI-suppressed. Ground: Circuit ground is independent of chassis ground; can be isolated or connected with a rear panel switch. Safety Standards: UL, CE, CSA.

15、OPTIMOD-AM DigitalTECHNICAL DATA 6-3 RadioFans.CN 收音机爱 好者资料库 Environmental Operating Temperature Range: 32 to 122F/0 to 50C at nominal operating voltages. Humidity: 0-95% RH, non-condensing. Dimensions (W x H x D): 19“ x 3.5” x 14.25“/48.3cm x 8.9cm x 36.2cm. Two rack units high. Weight: 14 lbs/6.4k

16、g. Shipping Weight: 18.5 lbs/8.4kg. Warranty One Year, Parts and Labor: Subject to the limitations set forth in Orbans Standard Warranty Agreement. Specifications are subject to change without notice. 6-4 TECHNICAL DATA Orban 9200 Component-Level Description: The 16.384MHz digital output from crysta

17、l oscillator Y602 is buffered by IC606-D, which feeds the master clock (MCLK) inputs of both the input and the output SRC chips IC603 and IC615 (on digital I/O option board). The 16.384MHz clock also feeds flip-flop IC604, which divides by two to produce an 8.192MHz clock. The 8.192MHz clock is buff

18、ered by IC606-C, which feeds digital multiplexer chip IC610, which in turn routes the 8.192MHz to AES/EBU digital audio transmitter chip IC616 when an internally generated 32kHz output sample rate is selected. The 8.192MHz clock is also sent to an 8-bit synchronous counter implemented in programmabl

19、e logic array (PLA) IC613. This counter divides down to obtain the lower frequency system clocks. All outputs of the PLA have their transitions coincident with the rising edge of the 8.192MHz clock. The 8.192MHz clock is inverted by buffers IC605-A, -B to provide clocks 8.192MHZA and 8.192MHZB that

20、have falling edges coincident with the transitions of the lower frequency clocks. 8.192MHZA feeds the bit clock of the inter-DSP communication links following buffers IC710-B, -D. 8.192MHZB feeds the A/D input clock (256 x sample rate), and the output D/A master clock. The 2.048MHz clock output from

21、 IC613 feeds the PLL circuit made up of PLA IC618, 74HC4046 phase detector/VCO IC619 and associated components. The PLA first buffers the 2.048MHz signal, providing a clean 2.048MHz output at pin 12 used as the reference input to the PLL phase detector (IC619 pin 14). Of the three detectors included

22、 in the 74HC4046, the phase frequency detector (PFD) is used by the 9200. The output of the phase detector (pin 13) feeds the loop filter made up of resistors R607, R608 and capacitor C605 that provide a single pole low-pass filter forming a second order loop. Pin 9 of IC619 is the input control vol

23、tage to the VCO. Resistor R614 eliminates subharmonic frequency modula- tion of the VCO caused by parasitic capacitance. Resistors R605 and R606 set the PLLs lock-in frequency range. A divide-by-nine counter is placed between the VCO output and the phase detector comparator input. This places the VC

24、O output at 18.432MHz. The divide-by-nine is implemented by the PLA IC618 between pins 2 and 15. A 6.144MHz clock is derived at the counters divide-by-three point and is provided at pin 17 of the PLA. The PLA provides a buffered 18.432MHz output at pin 14 which feeds Z-180 microprocessor IC100. Inve

25、rter IC605-C provides the 2.048MHZD bit clock for the output D/A and, via buffer IC606-B, the 2.048MHZC bit clock for the output SRC, IC615. IC614-A, -D provide buffered clocks 2.048MHZA and 2.048MHZB for driving the EXTAL inputs (pin 27) of the DSP chips. Each buffer drives four DSP chips. The 128k

26、Hz clock output of IC613 (pin 14) is used for the inter-DSP word clock. The 128kHz, 64kHz and 32kHz clocks are all used in the LCD backlight drive circuit. The 32kHz clock is also used for the input word clock of both the output sample-rate converter (SRC) and the output D/A. The 32kHz clock is used

27、 to generate DSP interrupt request signals (IRQBA, IRQBB) required for process timing and interchip synchronization. The circuit consisting of flip-flop IC612 and IC614-B, -C is required to ensure that the first falling edges of all IRQB 6-6 TECHNICAL DATA Orban 9200 signals are coincident. This syn

28、chronization occurs every time the unit is powered up and when there is a processing algorithm change. It is controlled by the Z-180 via pin 2 of latch IC611. The 32kHz clock is also used, along with IC313, in the A/D clock synchronizing circuit. This circuit makes the IRQB and the L/R clocks, both

29、operating at 32kHz, phase synchronous. This ensures that the process-to- output buffer transfer internal to the DSP doesnt overlap the output buffer-to-pe- ripheral transfer. The 8.192MHZB clock that feeds the A/D input clock (IC312 pin 19) is internally divided down to produce a 32kHz word clock at

30、 IC312 pin 13 and a 2.048MHz bit clock at pin 14. These clocks are used to control the A/D-to-DSP serial interface and the input SRC-to-DSP serial interface. AC terminations are used on various clocks throughout the board to improve signal integrity for sensitive devices. Control Circuits The contro

31、l circuits process and execute user-initiated requests to the system. The source of these requests is the front panel buttons, the rear panel RS-232 port, and the remote contact closures. These changes affect hardware function and/or DSP processing. The control circuits also send information to the

32、LCD display, LED status, and LED meter circuits. A RAM chip stores code segments. For quick access, an EEPROM chip stores dynamic system state information. A ROM chip contains the executable form of 9200 DSP and Control software. 1.Microprocessor and Power Monitoring Circuit A Z-180 microprocessor e

33、xecutes software code required to control the functionality of the 9200. The EXTAL pin of the Z-180 receives an 18.432MHz clock signal from the clock divider/PLL circuit and is internally divided down to 9.216MHz to provide the Z-180 system clock frequency. ROM contains control software for the Z-18

34、0. User system setup and other dynamic system state information that must survive power down is stored in non-volatile EEPROM. Power monitoring circuitry prevents data corruption by placing and holding the Z-180 in reset if AC mains power is insufficient. The Z-180 communicates to the DSP through th

35、e synchronous serial data host port. When the DSP requires executable code, the Z-180 reads it from the ROM and sends it to the DSP. The Z-180 sends parameter control data to the DSP and receives status data from the DSP. If status from DSP is irregular, the Z-180 will place the 9200 hardware and DS

36、P in a reset state and execute initialization procedures. Component-Level Description: The Z-180 is IC100. Watchdog timer/voltage monitor IC122 provides the system reset function. IC122 pin 7 monitors pulses generated every 1 second by the Z-180. If the Z-180 is not operating correctly to provide th

37、e pulses, IC122 will reset the Z-180. IC122 also monitors the voltage on the +5V source that supplies power to the 9200 digital electronics. When the +5V line is above the minimum operating voltage of +4.75V, R103 will pull RESET high which allows the Z-180 to exit the reset condition. When the +5V

38、line is below the minimum operating OPTIMOD-AM DigitalTECHNICAL DATA 6-7 voltage, the open-collector output of IC122 pulls Z-180s RESET low which puts the Z-180 into the reset condition, thereby preventing the Z-180 and the 9200 electronics from executing incorrectly due to low +5V line voltage. Z-1

39、80 IC100 pins 55, 56, and 57 comprise the host serial data communication port. The Z-180 uses this port to communicate with the DSP IC700-IC707 via host port interface pins 26, 35, and 41; and with EEPROM IC107 via pins 2, 5, and 6. Communication is SPI type with Z-180 as master and DSP as slave. 2.

40、RAM, ROM and EEPROM A RAM chip provides temporary storage for Z-180 data and program code segments. A ROM chip provides permanent storage of the executable control software and the executable DSP software. System state information that must be maintained while the 9200 is powered down is stored in a

41、 EEPROM. The EEPROM does not lose data when the 9200 is powered down. Component-Level Description: IC104 decodes Z-180 memory addresses to access instructions to execute from ROM IC105 and to read or write data from 32KB RAM IC106. EEPROM IC107 is selected by latch IC611 pin 6. 3.Data Latches, Tri-S

42、tate Data Buffers and Address Decoders Digital logic decodes Z-180 I/O addresses, allowing the Z-180 to access RAM, ROM and EEPROM. The logic provides Z-180 data bus allocation by using latches and tri-state data buffers to allow other 9200 hardware to communicate to the Z-180. To control other hard

43、ware, the Z-180s data bus state is latched at the appropriate time, and the latched control signals are provided to other hardware. For the Z-180 to read information from other hardware, the Z-180s data bus is connected at appropriate times to other hardwares source signals through tri-state data bu

44、ffers (e.g. IC120). Component-Level Description: Decoder IC104 allows the Z-180 to access ROM IC105 and RAM IC106. Decoders IC101, IC102, and IC103 allow the Z-180 to access all other 9200 hardware. The decoded outputs from IC101, IC102, and IC103 are used to latch the state of the Z-180 data bus at

45、 appropriate times with data latches IC1, IC2, IC3 IC4, IC5, IC6, IC303, IC609, IC611, IC708, and IC709, and to allocate the Z-180 data bus at appropriate times to various peripherals via tri-state data buffers IC120, IC8, and IC601. IC120 buffers or tri-states status information from the remote con

46、tact closure circuitry onto the Z-180 data bus. IC8 buffers or tri-states information from the user control interface onto the Z-180 data bus. IC601 (on digital I/O option board) buffers or tri-states status information from AES/EBU Receiver IC600 onto the Z-180 data bus. 6-8 TECHNICAL DATA Orban 92

47、00 User Control Interface and LED Display Circuits The user control interface enables the user to control the functionality of the 9200 unit. A rear panel remote interface connector enables remote control of certain functions. Front panel pushbutton switches select between various operational modes

48、and functions. Data latches detect and store the commands entered with these switches. Front panel status LEDs indicate the control status of the unit, and meter LEDs indicate signal levels and processing activity within the unit. 1.Remote and RS-232 Interfaces A remote interface connector and circu

49、itry enables remote control of certain operating modes; the 9200 has eight remote contact closure inputs. A valid remote signal is a momentary pulse of current flowing through the particular remote signal pins. Current must flow consistently for 50msec for the signal to be interpreted as valid. Generally, the 9200 will respond to the most recent control operation whether it came from the front panel, remote interface, or RS-232. Component-Level Description: J101 is a 25-pin D-connector that connects the remote control input signals. The connector incorporates a ferrite block to filte