Philips-DVDR-3350-H-Service-Manual(1) 电路图 维修手册.pdf

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1、Published by KC-TE 0549 AV Systems Printed in the Netherlands Subject to modifi cation EN 3139 785 31500 DVDR3350H/DVDR3360H/DVDR3370HDVD-Video Recorder CLASS 1 LASER PRODUCT Contents Page 1 Technical Specifi cations and Connection Facilities 2 2 Safety Information, General Notes however, the SYSCLK

2、 output remains active. If the LPS input remains low for more than 26 s (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset. The LLC is conside

3、red active only if both the LPS input is active and the LCtrl register bit is set to 1, and is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0. 48CMOSILLC request input. The LLC uses this input to initiate a service request to the TSB41AB1. Bus holde

4、r is built into this terminal. 16 17 18 CMOSIPower class programming inputs. On hardware reset, these inputs set the default value of the power class indicated during self-ID. Programming is done by tying these terminals high or low. Refer to Table 9 for encoding. NAME DGND DVDD FILTER0 FILTER1 ISO

5、LPS LREQ PC0 PC1 PC2 PD12CMOSIPower-down input. A high on this terminal turns off all internal circuitry except the cable-active monitor circuits, which control the CNA output (64-terminal PAP package only). Asserting the PD input high also activates an internal pulldown on the RESET terminal to for

6、ce a reset of the internal control logic. (PD is provided for legacy compatibility and is not recommended for power management in place of IEEE 1394a-2000 suspend/resume LPS and C/LKON features.) EN 683139 785 309818.Circuit- and IC Description TERMINAL TYPEI/ODESCRIPTION NAMEPHP NO. TYPEI/ODESCRIPT

7、ION 41SupplyPLL circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. 40SupplyPLL circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 F and 0.001 F. Lower f

8、requency 10 F filtering capacitors are also recommended. This supply terminal is separated from DVDD and AVDD inside the device to provide noise isolation. It should be tied at a low-impedance point on the circuit board. 33 34 BiasCurrent setting resistor terminals. These terminals are connected thr

9、ough an external resistor to set the internal operating currents and cable driver output currents. A resistance of 6.34 k 1.0% is required to meet the IEEE Std 1394-1995 output voltage limits. 37CMOSILogic reset input. Asserting this terminal low resets the internal logic. An internal pullup resisto

10、r to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the Application Information section). The RESET terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a s

11、tandard logic input, and may also be driven by an open-drain type driver. 23CMOSITest control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal may be tied to GND through a 1-k pulldown resistor or it may be tied to GND directly. 24CMOSITest control input.

12、 This input is used in manufacturing test of the TSB41AB1. For normal use this terminal should be tied to GND. 1CMOSOSystem clock output. Provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC. 22CMOSITest control input. This input is used in manufacturing test of the TSB41

13、AB1. For normal use this terminal should be tied to VDD. 30CableI/OTwisted-pair cable A differential signal terminals. Board traces from the pair of positive and negative differential signal terminals should be kept matched and as 29CableI/O positive and negative differential signal terminals should

14、 be kept matched and as short as possible to the external load resistors and to the cable connector. 28CableI/OTwisted-pair cable B differential signal terminals. Board traces from the pair of positive and negative differential signal terminals should be kept matched and as 27CableI/O positive and n

15、egative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. 31CableI/OTwisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receive

16、rs, and for signaling to the remote nodes that there is an active cable connection. PLLGND PLLVDD R0 R1 RESET SE SM SYSCLK TESTM TPA+ TPA TPB+ TPB TPBIAS XI XO 42 43 CrystalCrystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant fundamental mode crystal. The optimum valu

17、es for the external shunt capacitors are dependent on the specifications of the crystal used (see crystal selection in the Application Information section). When an external clock source is used, XI should be the input and XO should be left open, and the clock must be supplied before the device is p

18、owered on. EN 693139 785 309818.Circuit- and IC description IC7401 - 4x10bit DigitalVideo Decoder with microvision BLOCK DIAGRAM Composite and S-Video Processor Y/C Separation 5-line Adaptive Comb Luma Processing Chroma Processing ADC1 ADC2 ADC3 ADC4 M U X Component Processor CVBS/Y C Y/G Pb/B Pr/R

19、Gain/Offset Color Space Conversion C Y Output Formatter Y9:0 YCbCr VBI Data Slicer Copy Protection Detector C9:0 Host Interface Timing Processor with Sync Detector VI_1_A VI_1_B VI_1_C VI_2_A VI_2_B VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A CVBS/ Y/G CVBS/ Pb/B/C CVBS/ Pr/R/C CVBS/Y CVBS/Y/G Analog Front E

20、nd Sampling Clock GPIO FSS HS/CS VS/VBLK FID AVID XTAL1 XTAL2 DATACLK RESETB GLCO DR DG DB FSO PWDN SCL SDA YCbCr Figure 8-14 PIN CONFIGURATION 22 23 C_6/GPIO/RED C_7/GPIO/GREEN C_8/GPIO/BLUE C_9/GPIO/FSO DGND DVDD Y_0 Y_1 Y_2 Y_3 Y_4 IOGND IOVDD Y_5 Y_6 Y_7 Y_8 Y_9 DGND DVDD 60 59 58 57 56 55 54 53

21、 52 51 50 49 48 47 46 45 44 43 42 41 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VI_1_B VI_1_C CH1_A33GND CH1_A33VDD CH2_A33VDD CH2_A33GND VI_2_A VI_2_B VI_2_C CH2_A18GND CH2_A18VDD A18VDD_REF A18GND_REF CH3_A18VDD CH3_A18GND VI_3_A VI_3_B VI_3_C CH3_A33GND CH3_A33VDD 25 26 27 28 PFP PACKA

22、GE (TOP VIEW) 79 78 77 76 75807472 71 7073 29 30 31 32 33 69 68 21 67 66 65 64 34 35 36 37 38 39 40 63 62 61 VI_1_A CH1_A18GND CH1_A18VDD PLL_A18GND PLL_A18VDD XTAL2 XTAL1 VS/VBLK/GPIO HS/CS/GPIO FID/GPIO C_0/GPIO C_1/GPIO DGND DVDD C_2/GPIO C_3/GPIO C_4/GPIO C_5/GPIO IOGND IOVDD CH4_A33VDD CH4_A33G

23、ND VI_4_A CH4_A18GND CH4_A18VDD AGND DGND SCL SDA INTREQ DVDD DGND PWDN RESETB FSS/GPIO AVID/GPIO GLCO/I2CA IOVDD IOGND DATACLK Figure 8-15 EN 703139 785 309818.Circuit- and IC Description PIN DESCRIPTION TERMINAL I/ODESCRIPTION NAMENUMBER I/ODESCRIPTION Analog Video VI_1_A VI_1_B VI_1_C VI_2_A VI_2

24、_B VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A 80 1 2 7 8 9 16 17 18 23 I VI_1_x: Analog video input for CVBS/Pb/B/C VI_2_x: Analog video input for CVBS/Y/G VI_3_x: Analog video input for CVBS/Pr/R/C VI_4_A: Analog video input for CVBS/Y Up to 10 composite, 4 S-video, and 2 composite or 3 component video inp

25、uts (or a combination thereof) can be supported. The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 F. The possible input configurations are listed in the input select register at I2C subaddress 00h (see Section 2.11.1). Clock Signals DATACLK40OLine-locked data output clock. XT

26、AL174I External clock reference input. It may be connected to an external oscillator with a 1.8-V compatible clock signal or a 14.31818-MHz crystal oscillator. XTAL275OExternal clock reference output. Not connected if XTAL1 is driven by an external single-ended oscillator. Digital Video C9:0/ GPIO9:

27、0 57, 58, 59, 60, 63, 64, 65, 66, 69, 70 O Digital video output of CbCr, C9 is MSB and C0 is LSB. Unused outputs can be left unconnected. Also, these terminals can be programmable general-purpose I/O. For the 8-bit mode, the two LSBs are ignored. D_BLUE58IDigital BLUE input from overlay device D_GRE

28、EN59IDigital GREEN input from overlay device D_RED60IDigital RED input from overlay device FSO57IFast-switch overlay between digital RGB and any video Y9:0 43, 44, 45, 46, 47, 50, 51, 52, 53, 54 O Digital video output of Y/YCbCr, Y9 is MSB and Y0 is LSB. For the 8-bit mode, the two LSBs are ignored.

29、 Unused outputs can be left unconnected. Miscellaneous Signals FSS/GPIO35I/O Fast-switch (blanking) input. Switching signal between the synchronous component video (YPbPr/RGB) and the composite video input. Programmable general-purpose I/O GLCO/I2CA37I/O Genlock control output (GLCO). Two Genlock da

30、ta formats are available: TI format and real time control (RTC) format. During reset, this terminal is an input used to program the I2C address LSB. INTREQ30OInterrupt request PWDN33I Power down input: 1 = Power down 0 = Normal mode RESETB34IReset input, active low EN 713139 785 309818.Circuit- and

31、IC description TERMINAL I/ODESCRIPTION NAMENUMBER I/ODESCRIPTION Host Interface SCL28II2C clock input SDA29I/OI2C data bus Power Supplies AGND26IAnalog ground. Connect to analog ground. A18GND_REF13IAnalog 1.8-V return A18VDD_REF12IAnalog power for reference 1.8 V CH1_A18GND CH2_A18GND CH3_A18GND CH

32、4_A18GND 79 10 15 24 IAnalog 1.8-V return CH1_A18VDD CH2_A18VDD CH3_A18VDD CH4_A18VDD 78 11 14 25 IAnalog power. Connect to 1.8 V. CH1_A33GND CH2_A33GND CH3_A33GND CH4_A33GND 3 6 19 22 IAnalog 3.3-V return CH1_A33VDD CH2_A33VDD CH3_A33VDD CH4_A33VDD 4 5 20 21 IAnalog power. Connect to 3.3 V. DGND 27

33、, 32, 42, 56, 68 IDigital return DVDD 31, 41, 55, 67 IDigital power. Connect to 1.8 V. IOGND39, 49, 62IDigital power return IOVDD38, 48, 61IDigital power. Connect to 3.3 V or less for reduced noise. PLL_A18GND77IAnalog power return PLL_A18VDD76IAnalog power. Connect to 1.8 V. Sync Signals HS/CS/GPIO

34、72I/O Horizontal sync output or digital composite sync output Programmable general-purpose I/O VS/VBLK/GPIO73I/O Vertical sync output (for modes with dedicated VSYNC) or VBLK output Programmable general-purpose I/O FID/GPIO71I/O Odd/even field indicator output. This terminal needs a pulldown resisto

35、r. Programmable general-purpose I/O AVID/GPIO36I/O Active video indicator output Programmable general-purpose I/O EN 723139 785 309818.Circuit- and IC Description IC7501 - Power Distribution Switches BLOCK DIAGRAM OUT OC IN EN GND Current Limit Driver UVLO Charge Pump CS Thermal Sense Power Switch C

36、urrent Sense Figure 8-16 PIN CONFIGURATION 1 2 3 4 8 7 6 5 GND IN IN EN OUT OUT OUT OC TPS2041 D OR P PACKAGE (TOP VIEW) Figure 8-17 EN 733139 785 309818.Circuit- and IC description PIN DESCRIPTION TERMINAL NO. I/ODESCRIPTION NAMED OR P I/ODESCRIPTION TPS2041TPS2051 EN4IEnable input. Logic low turns

37、 on power switch. EN4IEnable input. Logic high turns on power switch. GND11IGround IN2, 32, 3IInput voltage OC55OOver current. Logic output active low OUT6, 7, 86, 7, 8OPower-switch output IC7521 - 2A Switch Step Down Switching Regulator PIN DESCRIPTION AND CONFIGURATION PIN CONNECTION PIN DESCRIPTI

38、ON NPinFunction 1OUTRegulator Output. 2,3,6,7GNDGround. 4COMPE/A output for frequency compensation. 5FBFeedback input. Connecting directly to this pin results in an output voltage of 1.23V. An external resistive divider is required for higher output voltages. 8VCCUnregulated DC input voltage. OUT GN

39、D GND COMP 1 3 2 4 VCC GND GND FB 8 7 6 5 D02IN1367 EN 743139 785 309818.Circuit- and IC Description IC7595 - Voltage Detector Series with Programmable Delay BLOCK DIAGRAM NCP303LSNxxT1 Open Drain Output Configuration Vref 2Input 3Gnd5CD RD 1Reset Output Figure 8-18 PIN DESCRIPTION AND CONFIGURATION

40、 PIN CONNECTIONS AND MARKING DIAGRAM 1 3N.C. Reset Output 2 Input Ground 4 CD5 xxxYW (Top View) xxx = 302 or 303 Y= Year W= Work Week Figure 8-19 EN 753139 785 31500 3139 249 3240 2005-10-26 Exploded View of the Set Figure 9-1 9.Exploded View & Spare Parts List EN 763139 785 315009.Exploded View & S

41、pare Parts List DVDR3350H, DVDR3360H & DVDR3370H MISCELLANEOUS 0001 3139 247 11361 MODULE DRIVE D4.3 CLOSED (Aluminium) 0001 3139 247 11362 MODULE DRIVE D4.3 CLOSED (Copper) 0002 2822 062 00069 HDD 3.5” 80GB WD800BB-55JKC0 B DVDR3350H ONLY 0002 2822 062 00071 HDD 3.5” 160GB WD1600BB-55GUC0 DVDR3360H

42、 ONLY 0002 2822 062 00099 HDD 3.5” 250GB 6L250R0 (MAXT)Y DVDR3370H ONLY 0011 3139 247 11652 PSU 05H80 WR 0021 3139 248 85821 PCBAS DVDR3350H ANA BOARD NA /37, /55, /96 ONLY 0021 3139 248 86761 PCBAS DVDR3350H ANA BOARD AP /75, /97 ONLY 0031 3139 248 85811 PCBAS DVDR3350H DIGI BOARD NA /37 ONLY 0031

43、3139 248 87271 PCBAS DVDR3350H DIGI BOARD LA /55 ONLY 0031 3139 248 87781 PCBAS DVDR3350H DIGI BOARD/96 /96 ONLY 0031 3139 248 86771 PCBAS DVDR3350H DIGI BOARD AP /75, /97 ONLY 0041 3139 248 85801 PCBAS DVDR3350H FRONT BOARD 0051 3139 248 85791 PCBAS DVDR3350H STANDBY BOARD 0164 3103 601 20231 SPRIN

44、G GROUND 0196 3139 241 23061 COVER TOP DVDR3300H 0228 3139 241 60432 PLATE REAR DVDR3350H/37 /37 ONLY 0228 3139 241 23781 PLATE REAR DVDR3350H/55 /55 ONLY 0228 3139 241 23721 PLATE REAR DVDR3350H/96 /96 ONLY 0228 3139 241 60421 PLATE REAR DVDR3350H/97 /75, /97 ONLY 0258 3139 241 21371 BRACKET LOADER

45、 0261 3103 604 01141 COVER DUST 0262 3103 603 20122 FOAM RUBBER SEALING 0264 3139 241 23031 BRACKET HDD DVDR3300H 0272 2522 200 98475 SCR PAN TORX ST BK #6-32X6 0288 4822 532 60948 BUSH 0292 2822 031 00024 FAN 12VDC 0.8W 3100RPM B 0333 2422 549 00665 REMOTE CONTR DVDR3350H/NAFTA B 0336 2422 070 9820

46、2 MAINSCORD UL 6A 2M3 VH BK B /37 ONLY 0336 2422 070 00026 MAINSCORD BRZ 10A 1M85 VH B /55 ONLY 0336 2422 070 00093 MAINSCORD TWN 7A 1M8 VH BK B /96 ONLY 0336 2422 070 98233 MAINSCORD AUS 7A5 1M8 VH BK B /75 ONLY 0336 4822 321 11499 MAINSCORD 2.0M - EU /97 ONLY 0337 2422 076 00655 CBLE CINCH 1M5 CIN

47、CH YERDWH B 0344 3104 128 90403 ANTENNA CABLE NTSC /37, /55, /96 ONLY 0344 4822 320 50377 CONNECT. CABLE PAL /75, /97 ONLY 0385 3139 128 73010 MAINS PLUG ADAPTER GR1-AX /55 ONLY 8002 3139 241 01371 FFC FOIL 14P/480/14P BD 1MMP 8003 3139 241 01361 FFC FOIL 20P/340/20P BD 1MMP 8004 3139 111 03991 FFC

48、FOIL 22P/280/22P BD 1MMP 8005 3139 110 35851 FFC FOIL 24P/180/24P BD 1mmP 8021 3139 241 00921 CBLE IDE 40P/280/40P IDE UL 8022 3139 241 00921 CBLE IDE 40P/280/40P IDE UL 8031 3103 601 00472 CBLE HR 4P/180/4P LC UL 8032 3139 241 01211 CBLE HR 04P/340/04P LC UL P001 3141 079 34251 CAB. FRONT ASSY DVDR

49、3350H/37 /37, /55 ONLY P001 3141 079 34401 CAB ASSY DVDR3360H/97 DVDR3360H/75, /97 ONLY P001 3141 079 34661 CAB ASSY DVDR3360H/96 DVDR3360H/96 ONLY P001 3141 079 34761 CAB. FRONT ASSY DVDR3370H/75 DVDR33570H/75, /96, /97 ONLY P002 3141 079 34271 COVER TRAY ASSY DVDR 3350H/37 P003 3141 079 34261 FRAME ASSY DVDR3350H/37 PCBAS DVDR3350H ANA BOARD NA (DVDR3350H/37/55, DVDR3360H/96 & DVDR3370H/96 ONLY) MISCELLANEOUS 1100 2422 542 00023 TUMOD V U PLL F MN B 1201 2422 026 05291 SO