Philips-FWV-330-Service-Manual(1) 电路图 维修手册.pdf

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1、CLASS 1 LASER PRODUCT COMPACT DIGITAL AUDIO Service Service Service Service Service FW-V330/21M TABLE OF CONTENTS Page Location of pc boards fr Reparaturen sind Original-Ersatzteile zu verwenden. I Le norme di sicurezza esigono che lapparecchio venga rimesso nelle condizioni originali e che siano ut

2、ilizzati i pezzi di ricambio identici a quelli specificati. After servicing and before returning set to customer perform a leakage current measurement test from all exposed metal parts to earth ground to assure no shock hazard exist. The leakage current must not exceed 0.5mA. CLASS 1 LASER PRODUCT 3

3、122 110 03420 GB Warning ! Invisible laser radiation when open. Avoid direct exposure to beam. SVarning ! Osynlig laserstrlning nr apparaten r ppnad och sprren r urkopplad. Betrakta ej strlen. SFVaroitus ! Avatussa laitteessa ja suojalukituksen ohitettaessa olet alttiina nkymttmlle laseristeilylle.

4、l katso steeseen! DK Advarse ! Usynlig laserstrling ved bning nr sikkerhedsafbrydere er ude af funktion. Undg udsaettelse for strling. PREPARATIONS AND CONTROLS 1-7 Preparations SPEAKERS 6R R + L + SUBWOOFER? OUT? AM ANTENNA FM ANTENNA LR speaker (right) speaker (left) FM wire antenna AM loop antenn

5、a B C AUX/CDR A AC power cord VOLTAGE SELECTOR 110V- 127V 220V- 240V VIDEO OUT VIDEO IN Television L R AUDIO OUT D E Rear connections The type plate is located at the rear of the system. APower Before connecting the AC power cord to the wall outlet, ensure that the following are done; If your system

6、 is equipped with a Voltage Selector, set the VOLTAGE SELECTOR to the local power line voltage. All other connections have been made. WARNING! For optimal performance,use only the original power cable. Never make or change any connections with the power switched on. BAntennas Connection Connect the

7、supplied AM loop antenna and FM antenna to the respective terminals. Adjust the position of the antenna for optimal reception. AMAntenna Position the antenna as far as possible from a TV, VCR or other radiation source. FM Antenna For better FM stereo reception, connect an outdoor FM antenna to the F

8、M ANTENNA terminal. VOLTAGE SELECTOR 110V- 127V 220V- 240V English Preparations CSpeakers Connection Front Speakers Connect the speaker wires to the SPEAKERS terminals, right speaker to R and left speaker to L, coloured (marked) wire to + and black (unmarked) wire to -. 12 Fully insert the stripped

9、portion of the speaker wire into the terminal as shown. Notes: For optimal sound performance, use the supplied speakers. Do not connect more than one speaker to any one pair of +/- speaker terminals. Do not connect speakers with an impedance lower than the speakers supplied. Please refer to the SPEC

10、IFICATIONS section of this manual. DVideo Out Connection Connect the VIDEO OUT terminal at the rear of the system to the TV or VCR VIDEO IN for viewing or recording. Note: To avoid magnetic interference with the picture on your TV, do not position the front speakers too close to the TV. EConnecting

11、other equipment to your system Use a cinch cable to connect AUX/CDR IN to the analogue audio out terminals of an external equipment (TV, VCR, Laser Disc player, DVD player or CD Recorder). Note: If you are connecting equipment with a mono output (a single audio out terminal), connect it to the AUX/C

12、DR IN left terminal. Alternatively,you can use a “single to double” cinch cable (the output sound still remain mono). Inserting batteries into the remote control Insert two batter ies type R06 or AA into the remote control with the correct polar ity as indicated by the + and - symbols inside the bat

13、tery compartment. CAUTION! Remove batteries if they are exhausted or will not be used for a long time. Do not use old and new or different types of batteries in combination. Batteries contain chemical substances , so they should be disposed off properly. PREPARATIONS AND CONTROLS 1-8 1 2 6 4 5 7 8 9

14、 0 ! #$ ( * % two times the actual pixel clock for screen video interface. PCLK44I/OPixel clock qualifier in for screen video interface. AUX7:054, 52, 53, 49:45 I/OAuxiliary control pins (AUX0 and AUX1 are open collectors). LD7:062:55I/ORISC interface data bus. LWR#63ORISC interface write enable (ac

15、tive low). LOE#64ORISC interface output enable (active low). LCS3,1,0#65,66,67ORISC interface chip select (active low). LA17:087:82, 79:68ORISC interface address bus. VPP81IDigital supply voltage for 5 V. ACLK88I/OMaster clock for external audio DAC (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344 MHz,

16、and 18.432 MHz). AOUT/ SEL_PLL0 89ODual-purpose pin. AOUT is the audio interface serial data output IPins SEL_PLL1:0 select phase-lock loop (PLL) clock frequency CPUCLK for the Visba: 00=bypass PLL. 01=54 MHz PLL. 10=67.5 MHz PLL. 11=81 MHz PLL. ATCLK90I/OAudio transmit bit clock. ATFS/ SEL_PLL1 91O

17、Dual-purpose pin. ATFS is the audio interface transmit frame sync. IPins SEL_PLL1:0 select phase-lock loop (PLL) clock frequency CPUCLK for the Visba. See the SEL_PLL0 pin above for the settings. DA9/DOE#92ODual purpose pin: DRAM output enable (active low)/DRAM multiplexed row and column address bus

18、. AIN93IAudio interface serial data input. ARCLK94IAudio receive bit clock. ARFS95IAudio interface receive frame sync. TDMCLK96ITDM interface serial clock. TDMDR97ITDM interface serial data receive. TDMFS98ITDM interface frame sync. CAS#99ODRAM column address strobe bank 0 (active low). ES3880 VIDEO

19、 CD PROCESSOR CHIP 1 VSS AUX4 AUX3 AUX2 AUX1 AUX0 PCLK PCLK2X CPUCLK HSYNC VSYNC YUV7 YUV6 YUV5 YUV4 YUV3 YUV2 YUV1 YUV0 VDD VPP LA12 LA13 LA14 LA15 LA16 LA17 ACLK AOUT/SEL_PLL0 ATCLK ATFS/SEL_PLL1 DA9/DOE# AIN ARCLK ARFS TDMCLK TDMDR TDMFS CAS# VSS DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 DA

20、8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DWE# RAS# VDD VSS RESET# DBUS15 DBUS14 DBUS13 DBUS12 DBUS11 DBUS10 DBUS9 DBUS8 LD6 LD7 LWR# LOE# LCS3# LCS1# LCS0# LA0 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 VSS VDD AUX5 AUX6 AUX7 LD0 LD1 LD2 LD3 LD4 LD5 31 30 51 50 80 81 100 ESS 2 3 4 5 6 7 8 9 10 11 12 13

21、14 15 16 17 18 1921 22 23 24 25 26 27 28 29 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52535455565758596061626364656667686970717273747576777879 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 20 Visba ES3880 Video CD PC 100-pin PQFP Visba Video CD PC Block Diagram DRAM DMA Controlle

22、r DRAM Interface Huffman Decoder 64x32 ROM 32x32 SRAM Registers On Screen MPEG Video Output 2Kx32 ROM 512x32 SRAM Processor RISC Serial Audio TDM Processor Display Interface Interface AOUT ARFS AIN ATCLK ACLK AUX7:0 CPUCLK DBUS15:0 CAS# DOE# RAS# DWE# HSYNC LCS3#, LCS#1:0 LOE# LA17:0 LWR# LD7:0 DA8:

23、0 PCLK2X PCLK RESET# ATFS SEL_PLL1:0 TDMCLK TDMDR VSYNC YUV7:0 Serial Audio Interface TDM Interface DRAM AUX Screen Display Misc. Processor Interface TDMFS ARCLK 8-58-5 PIN DESCRIPTION NameNumberI/ODefinition VSS1,25:26,31,72,75,77,91,100IGround. VCC5,16,32,66,73,78,90IVoltage supply, 5 V. DSC_C6ICl

24、ock for programming to access internal registers. AUX0 7I/OServo Forward or Control Pin. AUX19I/OServo Reverse or Control Pin. AUX211I/OServo LDON or Control Pin. AUX370I/OServo CW/Limit or Control Pin. AUX469I/OServo CCW/Close or Control Pin. AUX568I/OServo Data or Control Pin. AUX667I/OServo XLAT

25、or Control Pin/VFD_DO. AUX714I/OServo BRKM/Sense or Control Pin/VFD_DI. AUX818I/OServo Mute/Open or Control Pin/VFD_CLK. AUX920I/OServo SQS0 or Control Pin. AUX1034I/OServo SQCK or Control Pin. AUX1135I/O3880 IRQ or Interrupt Output or Control Pin. AUX1236I/OCD C2PO or Interrupt Input or Control Pin

26、. AUX1338I/OSerial Interrupt/CD-Mute or Control Pin. AUX1439I/OServo SCOR (S0S1) or Interrupt Input or Control Pin. AUX1540I/OInterrupt Input or Control Pin. DSC_D7:081,83,85,93,95,97,99,8I/OData for programming to access internal registers. DSC_S10IStrobe for programming to access internal register

27、s. DCLK 12 ODual-purpose pin DCLK is the MPEG decoder clock. EXT_CLKIEXT_CLK is the external clock EXT_CLK is an input during bypass PLL mode. RESET_B13IVideo reset (active-low). MUTE15OAudio mute. MCLK17IAudio master clock. TWS 19 IDual-purpose pin TWS is the transmit audio frame sync. SPLL_OUTOSPL

28、L_OUT is the select PLL output. TSD21ITransmit audio data input. TBCK22ITransmit audio bit clock. RWS 23 ODual-purpose pin RWS is the receive audio frame sync. SEL_PLL1IPins SEL_PLL1:0 select the PLL clock frequency for the DCLK output. RSTOUT_B24OReset output (active-low). NC2:4,27:30,76No connect.

29、 Do not connect to these pins. RSD 33 ODual-purpose pin. RSD is the receive audio data input. SEL_PLL0 ISEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK output. See the table for pin number 23. RBCK 37 ODual-purpose pin. RBCK is the receive audio bit clock. SER_IN ISER_IN is

30、the serial input DSC mode. 0 - Parallel DSC mode. 1 - Serial DSC mode. VSSAA41,51IAudio Analog Ground. VCM 42 IADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25 V. Bypass to analog ground with 47 m F electrolytic in parallel with 0.1 m F. VREFP43IDAC and ADC maximum reference.

31、 Bypass to VCMR with 10 m F in parallel with 0.1 m F. VCCAA44IAnalog VCC, 5 V. AOR+, AOR-45:46ORight channel output. AOL-, AOL+47:48OLeft channel output. MIC149IMicrophone input 1. MIC250IMicrophone input 2. VREF 52 IInternal resistor divider generates Common Mode Reference (CMR) voltage. Bypass to

32、ana- log ground with 0.1 m F. VREFM53IDAC and ADC minimum reference. Bypass to VCMR with 10 m F in parallel with 0.1 m F. RSET 54IFull scale DAC current adjustment. COMP55ICompensation pin. VSSAV56:57,62:63IVideo Analog Ground CDAC58OModulated chrominance output. VCCAV59,60IVideo VCC, 5 V YDAC61OY l

33、uminance data bus for screen video port. VDAC64OComposite video output. ACAP65IAudio CAP XOUT71OCrystal output. XIN74I27 MHz crystal input. PCLK79I/O13.5 MHz pixel clock. 2XPCLK80I/O27 MHz (2 times pixel clock). HSYN_B82OHorizontal sync (active-low). VSYN_B84OVertical sync (active-low). YUV7:086:89,

34、92,94,96,98IYUV data bus for screen video port. NameNumberI/ODefinition SEL_PLL1SEL_PLL0DCLK 00Bypass PLL (input mode) 0127 MHz (output mode) 1032.4 MHz (output mode) 1140.5 MHz (output mode) 1 MIC2 MIC1 AOL+ AOL- AOR- AOR+ VCCAA VREFP VCM VSSAA AUX15/IR AUX14/SOS1 AUX13/SP RBCK/SER_IN AUX12/C2PO AU

35、X11/IRQ AUX10/SQCK RSD/SEL_PLL0 VCC VSS DSC_D7 HSYN_B DSC_D6 VSYN_B DSC_D5 YUV7 YUV6 YUV5 YUV4 VCC VSS YUV3 DSC_D4 YUV2 DSC_D3 YUV1 DSC_D2 YUV0 DSC_D1 VSS TSD AUX9/SQS0 TWS/SPLL_OUT AUX8/VFD_CLK MCLK VCC MUTE AUX7/VFD_DI RESET_B DCLK/EXT_CLK AUX2 DSC_S AUX1 DSC_D0 AUX0 DSC_C VCC NC NC VSS NC NC NC N

36、C NC VSS VSS RSTOUT_B RWS/SEL_PLL1 TBCK YDAC VSSAV VSSAV VDAC ACAP VCC AUX6/VFD_DO AUX5 AUX4 AUX3 XOUT VSS VCC XIN VSS NC VSS VCC PCLK 2XPCLK VSSAA VREF VREFM RSET COMP VSSAV VSSAV CDAC VCCAV VCCAV 31 30 515080 81 100 2345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 49 48 47 46 45

37、 44 43 42 41 40 39 38 37 36 35 34 33 32 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Visba ES3883 Video CD Companion Chip ES3883 VIDEO CD COMPANION CHIP 3139 113 3448 pt2 dd wk01413139 113 3448 pt2 dd wk0141

38、 8-68-6 MPEG-01B BOARD LAYOUT PROCESSOR INTERFACE AUX SCREEN DISPLAY SERIAL INTERF TDM INTERFACE HUFFMAN DRAM DMA CONTROLLER ON SCREEN DISPLAY VIDEO OUTPUT MPEG PROCESSOR 512x32 SRAM 2Kx32 ROM DRAM INTERF DECODER RISC PROCESSOR 64x32 ROM 32x32 SRAM REGISTERS AUDIO & EPROM DRAM Video Reset & & F 1601

39、 D1 2201 E9 2206 E9 2210 E9 2223 A3 2235 B3 2258 E9 2268 D1 2270 B1 2271 E1 2272 F1 2273 C1 2276 C2 2277 B2 2279 D1 2280 C9 2281 C9 2282 C9 3204 C3 3205 C8 3206 D4 Row write 123456789 123456789 A B C D E F A B C D E & To ES3883 LD(7:0) 5V O/P enable Chip enable 85ms 6ms 5us 3207 C4 3208 C3 3209 D3 3

40、210 E3 3211 F3 3213 B9 3214 B9 3217 B8 3228 A8 3234 E8 3270 B2 3271 B2 3272 B2 3273 B8 3274 B8 3275 B8 3276 B2 5205 B3 5207 E9 5212 A3 5213 D9 7201 B4 From front uP to ES3880 & 5V Data Bus (8X) Address bus (18X) True for audio with 44.1KHz sampling frequency only To servo uP 7202 A6 7203 F6 7205-A F

41、2 7205-B E1 7205-C E2 7205-D F2 7205-E D2 7205-F D1 Data bus (16X) Address bus (9X) 5V & PROVISION ON THE LAYOUT Column O/P enable ES3883 select 100u 2258 3271100R 9 7 14 8 4K7 3208 5212 VCC7 VCC2 7205-C VCC7 3205 22K VCC1 2282 10n 34 YUV335 YUV436 YUV537 YUV638 YUV739 220R 3209 98 VDD1 1 VDD231 VDD

42、3 51 VPP81 VSS1100 VSS2 30 VSS350 VSS4 80 VSYNC40 YUV032 YUV133 YUV2 55 LD1 56 LD2 57 LD3 58 LD4 59 LD5 60 LD6 61 LD7 62 LOE_ 64 LWR_ 63 PCLK44 PCLK2X43 RAS_ 2 RESET_ 29 TDMCLK96 TDMDR97 TDMFS 83 LA1484 LA1585 LA1686 LA1787 LA2 70 LA3 71 LA4 72 LA5 73 LA6 74 LA7 75 LA8 76 LA9 77 LCS0_ 67 LCS1_ 66 LC

43、S3_ 65 LD0 28 DBUS2 15 16 DBUS3 DBUS4 17 DBUS5 18 DBUS6 19 DBUS7 20 DBUS8 21 DBUS9 22 DWE_ 3 HSYNC41 LA0 68 LA1 69 LA10 78 LA11 79 LA1282 LA13 5 DA2 6 DA3 7 DA4 8 DA5 9 DA6 10 DA7 11 DA8 12 DA9|DOE_92 DBUS0 13 DBUS1 14 DBUS10 23 DBUS11 24 DBUS12 25 DBUS13 26 DBUS14 27 DBUS15 89 ARCLK94 ARFS95 ATCLK9

44、0 ATFS|SEL-PLL191 AUX045 AUX146 AUX247 AUX348 AUX449 AUX5 52 AUX6 53 AUX7 54 CAS_99 CPUCLK42 DA0 4 DA1 ES3880 7201 ACLK88 AIN93 AOUT|SEL-PLL0 3213 22K 100n 2235 3217 22K 40 VSS3 WE_ 13 10 I|O9 31 LCAS_ 29 NC1 11 NC2 12 NC3 15 30 NC4 27 OE_RAS_ 14 UCAS_ 28 VCC1 1 VCC2 6 VCC3 20 VSS1 21 35 VSS2 25 A8

45、26 I|O1 2 I|O10 32 I|O11 33 I|O12 34 36 I|O13 37 I|O14 I|O15 38 I|O16 39 I|O2 3 I|O3 4 I|O4 5 I|O5 7 8 I|O6 9 I|O7 I|O8 7203 MSM514265E A0 16 A1 17 A2 18 19 A3A4 22 23 A5 A6 24 A7 VCC7 3273220R 7205-B 74HC04D 3 7 14 4 100R 3270 2210 100n 13 7 14 12 5205 100n 2206 74HC04D 7205-F 22 3 4 5 6 7 8 9 1 10

46、 11 12 13 14 15 16 17 18 19 2 20 21 1601 4K7 3206 5207 2271 100p 100n 2201 VCC8 100p 2280 VCC2 5213 100n 2279 7205-A 74HC04D 1 7 14 2 100p 2268 2223 100n 100p 2276 100R 3272 3228 4K7 VCC1 VCC1 74HC04D 5 7 14 6 3211 220R 100p 2281 2270100p 220R3274 AGND 7205-E 74HC04D 11 7 14 10 1 VPPVSS 16 +5V A8 26

47、 A9 E_ 22 G_ 24 31 P_ Q0 13 Q1 14 Q2 15 Q3 17 Q4 18 Q5 19 Q6 20 Q7 21 VCC 32 A1 23 A10 25 A11 4 A12 28 A13 29 A14 3 A15 2 A16 30 A17 10 A2 9 A3 8 A4 7 A5 6 A6 5 A7 27 7202 AT27C020 12 A0 11 VCC7 3275220R 3204 4K7 10K 3214 VCC8 VCC8 100p 2277 +5V 4K7 3207 74HC04D 7205-D VCC7 VCC3 3210 220R VCC7 3234

48、1K +5V +5V 100p 2272 VCC8 3276 100R 100p2273 IIS_SCLK IIS_WCLK IIS_DATA DSA_S DSA_D DSA_A SDA SILD SICL RAB VCC7 LA(11) LA(12) LA(13) LA(14) LA(15) LA(17) LA(16) AUX5 VDD3 LA(0:17) DSA_STB DSA_STB VCC2 LD(7) LD(0:7) IIS_DATA IIS_WCLK IIS_SCLK LEFT RIGHT DSA_ACK DSA_STB DSA_DAT CD10_RST YUV(2) YUV(3)

49、 YUV(4) YUV(5) YUV(6) YUV(7) DA(0:8) DBUS(0:15) RSTOUT# DSA_DAT DSA_ACK LD(7) LD(6) LD(5) LD(4) LD(3) LD(2) LD(1) LD(0) LA(0) LA(1) LA(2) LA(3) LA(4) LA(5) LA(6) LA(7) LA(8) LA(9) LA(10) DBUS(7) DBUS(8) DBUS(9) HSYNC LA(0) LA(1) LA(10) LA(11) LA(2) LA(3) LA(4) LA(5) LA(6) LA(7) LA(8) LA(9) LCS1# LD(0) LD(1) LD(2) LD(3) LD(4) LD(5) LD(6) 135M10 PCLKCSCN VDD3 VDD3 VSYNC YUV(0) YUV(1) DBUS(1) DBUS(2) DBUS(3) DBUS(4) DBUS(5) DBUS(6) DBUS(7) DBUS(8) DA(0) DA(1) DA(2) DA(3) DA(4) DA(5) DA(6) DA(7) DA(8) DBUS(0) DBUS(1) DBUS(10) DBUS(11) DBUS(12) DBUS(13) DBUS(14) DB