Onkyo-TXSR304-avr-sm 电路图 维修手册.pdf

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1、TX-SR304(HT-S4100) SERVICE MANUALSERVICE MANUAL AV RECEIVER Black and Silver models MODEL TX-SR304 Ref. No. 4059 042007 120V AC, 60Hz 120V AC, 60Hz B MDC S MDC For HT-S4100 TONE+STEREOLISTENING MODEDISPLAYDIGITAL INPUTDIMMERMEMORYTUNING MODE RETURN TUNING/ PRESET ENTER SETUP STANDBY STANDBY/ON CLEAR

2、 PHONES MULTl CHDVDVIDEO 1/VCRVIDEO 2VIDEO 3TAPETUNERCD MASTER VOLUME A SPEAKERS B RC-645S MUTING PREVIOUS MENU GUIDE TOP MENU SP A / B SETUPRETURN PLAYLISTPLAYLIST RANDOMSUBTITLE PLAY MODE AUDIOREPEAT RC- 645S -/- TAPE ON/STANDBY DIMMERSLEEP INPUT SELECTOR REMOTE MODE V1V2V3 C DT A PETUNER DVDMULTI

3、 CH LISTENING MODE DISPLAY TEST TONECH SEL SURROUNDSTEREO CINE FLTR LEVEL+LEVEL- L NIGHT VOL HDD CDR MD DVDRECEIVER C D +10 0CLR 123 456 789 ENTER CH DISC ALBUM SAFETY-RELATED COMPONENT WARNING! COMPONENTS IDENTIFIED BY MARK ON THE SCHEMATIC DIAGRAM AND IN THE PARTS LIST ARE CRITICAL FOR RISK OF FIR

4、E AND ELECTRIC SHOCK. REPLACE THESE COMPONENTS WITH ONKYO PARTS WHOSE PART NUMBERS APPEAR AS SHOWN IN THIS MANUAL. MAKE LEAKAGE-CURRENT OR RESISTANCE MEASUREMENTS TO DETERMINE THAT EXPOSED PARTS ARE ACCEPTABLY INSULATED FROM THE SUPPLY CIRCUIT BEFORE RETURNING THE APPLIANCE TO THE CUSTOMER. RadioFan

5、s.CN 收音机爱 好者资料库 Re q u e s t I D T MA I - 7 A 9 D C 9 ONKYO Service Manual W r i t t e n By : Te r u k a z u M a t u m i Re q u e s t Da t e : 2 0 0 8 / 0 4 / 1 5 Status: Completed I s s u e rA p p r o v e rRe v i e w e rW r i t e r Te c h n i c a l s u p p o r tT o s h i y u k i O t a n i 2 0 0 8 /

6、 0 9 / 0 1 T o s h i a k i O k u y a m a 2 0 0 8 / 0 4 / 1 5 T e r u k a z u M a t u m i 2 0 0 7 / 1 2 / 2 6 Model:TX-SR304(HT-S4100) Ref No:4059 C o m p o n e n t :HT-S4100 = TX-SR304 + HTP-460 + DS-A1XP P r i n t e d s e r v i c e m a n u a l i s n o t p r e p a r e d . T i t l eA p p r o v e ( D

7、a t e ) A t t a c h e d f i l e C o v e r2 0 0 8 / 0 2 / 1 2 S p e c i f i c a t i o n s / P a n e l v i e w / R e m o t e c o n t r o l l e r - - -R e f e r t o i n s t r u c t i o n m a n u a l . E x p l o d e d v i e w2 0 0 8 / 0 2 / 1 3 B l o c k d i a g r a m s- - -R e f e r t o s e r v i c e m

8、 a n u a l o f T X - S R 3 0 4 / 3 0 4 E ( R e f . N o . : 3 9 2 5 ) S c h e m a t i c d i a g r a m s2 0 0 8 / 0 2 / 1 2 - - - 2 P a g e s ( L / R ) A u d i o i n p u t s e c t i o n - - - A l l ( T a b l o i d s i z e ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

9、- - - - - - 2 P a g e s ( L / R ) P o w e r a m p l i f i e r s e c t i o n - - - A l l ( T a b l o i d s i z e ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2 P a g e s ( L / R ) D S P ALE is used in conjunction with an external latch to retain the valu

10、es of the A238. For 16-bit mode: ALE is automatically asserted whenever a change occurs in the address bits, A150; ALE is used in conjunction with an external latch to retain the values of the A150. To use these pins as flags (FLAG150) set (=1) Bit 20 of the SYSCTL register and disable the parallel

11、port. See Table 4 on Page 14 for a list of how the AD150 pins map to the flag pins. When configured in the IDP_PDAP_CTL register, the IDP Channel 0 can use these pins for parallel input data. Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or 16-bit data from an external m

12、emory device. When AD150 are flags, this pin remains deasserted. Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or 16-bit data to an external memory device. When AD150 are flags, this pin remains deasserted. Parallel Port Address Latch Enable. ALE is asserted whenever t

13、he DSP drives a new address on the parallel port address pin. On reset, ALE is active high. However, it can be reconfigured using software to be active low. When AD150 are flags, this pin remains deasserted. Flag Pins. Each FLAG pin is configured via control bits as either an input or output. As an

14、input, it can be tested as a condition. As an output, it can be used to signal external peripherals. These pins can be used as an SPI interface slave select output during SPI mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals. In SPI master boot mode, FLAG0 is the slave

15、select pin that must be connected to an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When Bit 16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0. When Bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1. When Bit 18 is set (=1) in the SY

16、SCTL register, FLAG2 is configured as IRQ2. When Bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which indicates that the system timer has expired. Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The SRU configuration registers define the

17、 combination of on-chip peripheral inputs or outputs connected to the pin and to the pins output enable. The configuration registers of these peripherals then determine the exact behavior of the pin. Any input or output signal present in the SRU may be routed to any of these pins. The SRU provides t

18、he connection from the serial ports, input data port, precision clock generators, and timers to the DAI_P201 pins. These pins have internal 22.5 k ohms pull-up resistors which are enabled on reset. These pull-ups can be disabled in the DAI_PIN_PULLUP register. I/O/T O O O I/O/A I/O/T AD150 RD WR ALE

19、 FLAG30 DAI_P201 PinTypeFunction IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-3 Q201 : ADSP-21266(32 bit, Floating-point SHARC DSP)-3/5 TERMINAL DESCRIPTION(2/3) TX-SR304/304E Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. T

20、he master may transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). S

21、PICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfe

22、r format. SPICLK has a 22.5 k ohms internal pull-up resistor. If SPI master boot mode is selected, MOSI and SPICLK pins are driven during reset. These pins are not three-stated during reset in SPI master boot mode. Serial Peripheral Interface Slave Device Select. An active low signal used to select

23、the DSP as an SPI slave device. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster mode the DSPs SPIDS signal can be driven by a slave device to signal to the DSP (as SPI master) that an error has occurred, as some other device is

24、 also trying to be the master device. If asserted low when the device is in master mode, it is considered a multimaster error. For a single master, multiple-slave configuration where flag pins are used, this pin must be tied or pulled high to VDDEXT on the master device. For ADSP-21266 to ADSP-21266

25、 SPI interaction, any of the master ADSP-21266s flag pins can be used to drive the SPIDS signal on the ADSP-21266 SPI slave device. SPI Master Out Slave In. If the ADSP-21266 is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-21266 is

26、configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In an ADSP-21266 SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 k OHMS internal pull-up resistor. If

27、SPI master boot mode is selected, MOSI and SPICLK pins are driven during reset. These pins are not three-stated during reset in SPI master boot mode. SPI Master In Slave Out. If the ADSP-21266 is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the AD

28、SP-21266 is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In an ADSP-21266 SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has a 22.5 k ohms internal pull-

29、up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register. Note: Only one slave is allowed to transmit data at any given time. To enable broadcast transmission to multiple SPI slaves, the DSPs MISO pin may be disabled by setting (=1) Bit 5 (DMISO) of the SPICTL registe

30、r. Boot Configuration Select. Selects the boot mode for the DSP. The BOOTCFG pins must be valid before reset is asserted. See Table 5 on Page 14 for a description of the boot modes. I/O I I/O (O/D) I/O (O/D) I SPICLK SPIDS MOSI MISO BOOTCFG10 PinTypeFunction TX-SR304/304E IC BLOCK DIAGRAMS AND TERMI

31、NAL DESCRIPTIONS-4 Q201 : ADSP-21266(32 bit, Floating-point SHARC DSP)-4/5 TERMINAL DESCRIPTION(3/3) Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21266 clock input. It configures the ADSP-21266 to use either its internal clock generator or an external clock source. Connecting the

32、 necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21266 to use the external clock source such as an external clock oscillator. The core is clocked either by the PLL output or this cl

33、ock input depending on the CLKCFG10 pin settings. CLKIN may not be halted, changed, or operated below the specified frequency. Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 6

34、for a description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. Reset Out/Local Clock Out. Drives out the core reset signal to an external device. C

35、LKOUT can also be configured as a reset out pin (RSTOUT). The functionality can be switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL register. The default is reset out. Processor Reset. Resets the ADSP-21266 to a known state. Upon deassertion, there is a 4096 CLKIN c

36、ycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up. Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low fo

37、r proper operation of the ADSP-21266. Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 k ohms internal pull-up resistor. Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5 k ohms internal pull-up resistor. Test Data Output (JTAG).

38、Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21266. TRST has a 22.5 k ohms internal pull-up resistor. Emulation Status. Must be connected to the ADSP-2126

39、6 Analog Devices DSP Tools product line of JTAG emulators target board connector only. EMU has a 22.5 k ohms internal pull-up resistor. Core Power Supply. Nominally +1.2 V dc and supplies the DSPs core processor (13 pins on the BGA package, 32 pins on the LQFP package). I/O Power Supply. Nominally +

40、3.3 V dc (6 pins on the BGA package, 10 pins on the LQFP package). Analog Power Supply. Nominally +1.2 V dc and supplies the DSPs internal PLL (clock generator). This pin has the same specifications as VDDINT, except that added filtering circuitry is required. For more information, see Power Supplie

41、s on Page 8. Analog Power Supply Return. Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package). I O I O I/A I I/S I/S O I/A O (O/D) P P P G G CLKIN XTAL CLKCFG10 RSTOUT/ CLKOUT RESET TCK TMS TDI TDO TRST EMU VDDINT VDDEXT AVDD AVSS GND PinTypeFunction TX-SR304/304E IC BLOCK

42、DIAGRAMS AND TERMINAL DESCRIPTIONS-5 Q201 : ADSP-21266(32 bit, Floating-point SHARC DSP)-5/5 PIN CONFIGURATION 1 36 3772 73 108 109144 ADSP-21266 VDDINT CLKCFG0 CLKCFG1 BOOTCFG0 BOOTCFG1 GND VDDEXT GND VDDINT GND VDDINT GND VDDINT GND FLAG0 FLAG1 AD7 GND VDDINT GND VDDEXT GND VDDINT AD6 AD5 AD4 VDDI

43、NT GND AD3 AD2 VDDINT GND AD1 AD0 WR VDDINT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VDDINT GND RD ALE AD15 AD14 AD13 GND VDDEXT AD12 VDDINT GND AD11 AD10 AD9 AD8 DAI_P1(SD0A) VDDINT GND DAI_P2(SD0B) DAI_P3(SCLK0) GND VDDEXT VDDINT GND DAI_P4

44、(SFS0) DAI_P5(SD1A) DAI_P6(SD1B) DAI_P7(SCLK1) VDDINT GND VDDINT GND DAI_P8(SFS1) DAI_P9(SD2A) VDDINT 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 1

45、02 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VDDEXT GND VDDINT GND DAI_P10(SD2B) DAI_P11(SD3A) DAI_P12(SD3B) DAI_P13(SCLK23) DAI_P14(SFS23) DAI_P15(SD4A) VDDINT GND GND DAI_P

46、16(SD4B) DAI_P17(SD5A) DAI_P18(SD5B) DAI_P19(SCLK45) VDDINT GND GND VDDEXT DAI_P20(SFS45) GND VDDINT FLAG2 FLAG3 VDDINT GND VDDINT GND VDDINT GND VDDINT GND VDDINT VDDINT GND VDDINT GND VDDINT GND VDDINT GND VDDEXT GND VDDINT GND VDDINT RESET SPIDS GND VDDINT SPICLK MISO MOSI GND VDDINT VDDEXT AVDD

47、AVSS GND CLKOUT EMU TDO TDI TRST TCK TMS GND CLKIN XTAL VDDEXT Pin No. Pin NamePin No. Pin NamePin No. Pin NamePin No. Pin Name TX-SR304/304E IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-6 Q301 : CS42516-CQZ (192 kHz, 6-Ch Codec with S/PDIF Receiver)-1/3 BLOCK DIAGRAM PIN CONFIGURATION TXPVARXAGNDLPF

48、LTDGND DGND VDVD INT RST AD0/CS AD1/CDIN SDA/CDOUT SCL/CCLK VLC OMCK RMCK SAI_LRCK SAI_SCLK SAI_SDOUT VLS ADCIN1 ADCIN2 CX_SDOUT CX_LRCK CX_SCLK CX_SDIN1 CX_SDIN2 CX_SDIN3 RXP0 RXP1/GPO1 RXP7/GPO7 RXP4/GPO4 RXP5/GPO5 RXP6/GPO6 RXP3/GPO3 RXP2/GPO2 MUTEC FILT+ VQ REFGND VA AGND AINL+ AINL- AINR+ AINR-

49、 AOUTA1+ AOUTA1- AOUTA3+ AOUTA3- AOUTB2+ AOUTB2- AOUTA2+ AOUTA2- AOUTB1+ AOUTB1- AOUTB3+ AOUTB3- DAC#1 DAC#2 DAC#3 DAC#4 DAC#5 DAC#6 Analog Filter ADC#1 ADC#2 Digital Filter Digital Filter Gain & Clip Gain & Clip DEM Digital Filter ADC Serial Data Serial Audio Interface Port Mult/Div Internal MCLK Control Port C&U Bit Data Buffer Format Detector S/PDIF Decoder Clock/Data Recovery Rx GPO MUTE Ref Volume Control CODEC Serial Port 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CX_SDIN1 CX_SCLK CX_LRCK VD DGND VLC SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS INT RST AI