Marantz-PMD-620-Service-Manual(1) 电路图 维修手册.pdf

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1、SERVICE MANUAL Handheld Solid State Recorder MODEL PMD620 For U.S.A., Canada, Europe, China A0A8 x8; A0A7 x16; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine if all banks are to be precha

2、rged (A10HIGH) or bank selected by BA0, BA1 (A1LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 DQ0DQ15x16: I/OData input/output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51 are NCs for x8; an

3、d 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for x4). DQ0DQ7x8: I/OData input/output: Data bus for x8 (2, 8, 47, 53 are NCs for x4). DQ0DQ3x4: I/OData input/output: Data bus for x4. E2NCNo connect: These pins should be left unconnected. G1NCAddress input (A12) for the 256Mb and 512Mb dev

4、ices A7, B3, C7, D3 VDDQSupplyDQ power: Isolated DQ power on the die for improved noise immunity. A3, B7, C3, D7 VSSQSupplyDQ ground: Isolated DQ ground on the die for improved noise immunity. A9, E7, J9VDDSupplyPower supply: +3.3V 0.3V. A1, E3, J1VSSSupplyGround. 34 Q006 : S29AL016D70BFI020 Input/O

5、utput Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator Timer VCC Detector State Control Command Register VCC VSS WE# BYTE# CE# OE# STB STB DQ0DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address Latch A0A19 BLOCK DI

6、AGRAM A1B1C1D1E1F1G1H1 A2B2C2D2E2F2G2H2 A3B3C3D3E3F3G3H3 A4B4C4D4E4F4G4H4 A5B5C5D5E5F5G5H5 A6B6C6D6E6F6G6H6 DQ15/A-1VSSBYTE#A16A15A14A12A13 DQ13DQ6DQ14DQ7A11A10A8A9 VCCDQ4DQ12DQ5A19NCRESET#WE# DQ11DQ3DQ10DQ2NCA18NCRY/BY# DQ9DQ1DQ8DQ0A5A6A17A7 OE#VSSCE#A0A1A2A4A3 FBGA Top View, Balls Facing Down CONN

7、ECTION DIAGRAMS 35 Q006 : S29AL016D70BFI020 A0A19=20 addresses DQ0DQ14=15 data inputs/outputs DQ15/A-1=DQ15 (data input/output, word mode), ? A-1 (LSB address input, byte mode) BYTE#=Selects 8-bit or 16-bit mode CE#=Chip enable OE#= Output enable WE#=Write enable RESET#=Hardware reset pin RY/BY#= Re

8、ady/Busy output VCC =3.0 volt-only single power supply? (see Product Selector Guide for speed? options and voltage supply tolerances) VSS=Device ground NC=Pin not connected internally mbol 20 16 or 8 DQ0DQ15 (A-1) A0A19 CE# OE# WE# RESET# BYTE#RY/BY# PIN CONFIGURATION LOGIC SYMBOL 36 Q083 : NJU7700-

9、F4/F15 34 12 1. VOUT 2. VDD 3. NC 4. VSS VOUT VREF VDD VSS 37 Q201 : NJU3713A Package Outline SSOP20 P51 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD P4 P3 P2 P1 NC CLR STB CLK DATA P6 P7 P8 VSS NC P9 P10 P11 P12 PIN CONFIGURATION P1 Shift Register Controller Circuit Latch Circuit P2 P3 P11

10、P12 DATA CLK STB CLR BLOCK DIAGRAM No. SYMBOL I/O FUNCTION 1 P5 O 2 P6 O 3 P7 O 4 P8 O Parallel Conversion Data Output Terminals 5 VSS - GND 6 NC - Non Connection 7 P9 O 8 P10 O 9 P11 O 10 P12 O Parallel Conversion Data Output Terminals 11 DATA I Serial Data Input Terminal 12 CLK I Clock Signal Inpu

11、t Terminal 13STB I Strobe Signal Input Terminal 14CLRI Clear Signal Input Terminal 15 NC - Non Connection 16 P1 O 17 P2 O 18 P3 O 19 P4 O Parallel Conversion Data Output Terminals 20 VDD - Power Supply Terminal (2.4 to 5.5V) TERMINAL DESCRIPTION 38 Q202 : NJU3754 Package Outline SSOP16 PIN CONFIGURA

12、TION P0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD CE CLK SO P10 P9 P8 P7 P1 P2 P3 P4 P5 P6 VSS P0 Latch Circuit Control Circuit P1 P2 P9 P10 SO CE CLK Shift Register VDDVSS BLOCK DIAGRAM No.SYMBOL I/O FUNCTION 1 P0 I 2 P1 I 3 P2 I 4 P3 I 5 P4 I 6 P5 I 7 P6 I Parallel Data Input Terminals (with pull

13、-up resistors) 8 VSS - Ground 9 P7 I 10 P8 I 11 P9 I 12 P10 I Parallel Data Input Terminals (with pull-up resistors) 13 SO O Serial Data Output Terminal 14CLKI Serial Clock Input Terminal 15CEI Chip Enable Input Terminal 16 VDD - Power Supply Terminal (2.7 to 5.5V) TERMINAL DESCRIPTION 39 Q207 : M66

14、592FP AFED33G AFED33V DM DP VBUS AFEA15V AFEA15G REFRIN AFEA33G XIN XOUT AFEA33V AFED15V AFED15G VIF TEST D8 D7 D6/AD6 D5/AD5 D4/AD4 D3/AD3 D2/AD2 D1/AD1 D0 A6/ ALE A5 A4 A3 A2 A1 MPBUS M66592FP (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1

15、9 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SD6 SD7 INT_N SOF_N RD_N WR0_N WR1_N CS_N DREQ0_N DACK0_N DEND0_N DREQ1_N DACK1_N/DSTB0_N DEND1_N RST_N VIF SD5 SD4 SD3 SD2 SD1 SD0 VIF DGND VDD D15 D14 D13 D12 D11 D10 D9 Package M66592FP : 64pinLQFP (0.5mm pit

16、ch) *The “_N” in the signal name indicates that the signal is in the “L” active state. PIN LAYOUT DIAGRAM 40 Q207 : M66592FP State of pin *7) Category Pin name NameI/OFunction Pin count (Pin nos.) RST_N=” L” RST_N goes “H” PCUT=1 D15-0 Data Bus I/O This is a 16-bit data bus. 24-39*4) *4) AD6-1 Multi

17、plex Address Bus I/O When a multiplex bus is specified, this group of pins is used on a time-shared basis for some of the data buses (D6-D1), or for 6 bits of the address bus (A6-A1). Input (Hi-z) A6-1 Address Bus IN This is a 6-bit address bus. Because the data bus consists of 16 bits, there is no

18、A0. 18-23Input *5) Input *5) ALE Address Latch Enable IN When a multiplex bus is specified, the A6 pin is used as the ALE signal. Input Input Input (Hi-z) Input CS_N Chip Select IN Setting this to the “L” level selects this controller. 56Input *6) Input *6) Input RD_N Read Strobe IN Setting this to

19、the “L” level reads data from the controller registers. 53Input Input Input WR0_N D7-0 Byte Write Strobe IN At the rising edge, D7-D0 are written to the registers of the controller. 54Input *6) Input *6) Input WR1_N D15-8 Byte Write Strobe IN At the rising edge, D15-D8 are written to the registers o

20、f the controller. 55Input *6) Input *6) Input CPU bus interface MPBUS*3 Bus Mode Selection IN Setting this to the “L” level selects a separate bus. Setting this to the “H” level selects a multiplex bus. This should be fixed at either the “H” or “L” level. 17Input *3) Input *3) Input *3) Split bus in

21、terface SD7-0 Split Data Bus I/O If a split bus is selected, this functions as the data bus for the split bus. 43-50Input (Hi-z) Input (Hi-z) Input (Hi-z) DREQ0_N*1 DREQ1_N*1 DMA Request OUT This notifies the system of a D0FIFO port or D1FIFO port DMA transfer request. 57, 60H H H/L *8) DACK0_N*1 DA

22、CK1_N*1 DMA Acknowledge IN Input the DMA Acknowledge signal for the D0FIFO or D1FIFO port. 58, 61Input Input DSTB0_N*2 Data Strobe 0 IN This functions as the data strobe signal for the D0FIFO port. Because it is also used for the DMA Acknowledge signal of the D1FIFO port, the DSTB0_N function cannot

23、 be used if the DACK1_N function is being used. Input DMA bus interface DEND0_N*1 DEND1_N*1 DMA Transfer End I/O This receives the Transfer End signal from another peripheral chip or the CPU as an input signal. This indicates the transfer end data as an output signal. 59, 62Input (Hi-z) Input (Hi-z)

24、 Input (Hi-z) INT_N Interrupt OUT In the “L” active state, this notifies the system of various types of interrupts relating to USB communication. 51H H H Interrupt/ SOF output SOF_N SOF pulse output OUT When an SOF is detected in the “L” active state, an SOF pulse is output. 52H H H 10 NI tupn i no

25、i ta l l i csO NIXClock XOUT Oscillation output OUT A crystal oscillator should be connected between XIN and XOUT. When using external clock input, the external clock signal should be connected to XIN, and XOUT should be open. 11 PIN DESCRIPTIONS 41 State of pin *7) Category Pin name NameI/OFunction

26、 Pin count (Pin nos.) RST_N=” L” RST_N goes “H” PCUT=1 RST_N Reset signal IN At “L” level, the controller is initialized. 63 Input (L) Input (H) Input (H) System control TEST Test signal IN This should be fixed at “L” or open. 16 DP USB D+ data I/O This should be connected to the D+ pin of the USB b

27、us. 4Input (Hi-z) Input (Hi-z) Input (Hi-z) USB bus interface DM USB D- data I/O This should be connected to the D- pin of the USB bus. 3Input (Hi-z) Input (Hi-z) Input (Hi-z) VBUS monitor input VBUS VBUS input IN This should be connected directly to the Vbus of the USB bus. The connected or disconn

28、ected state of the Vbus can be detected. If This pin is not connectted with Vbus of a USB bus, connect it with 5V. 5Input (Hi-z) Input (Hi-z) Input (Hi-z) Reference resistance REFRIN Reference input IN This should be connected to AFEA33G through a 5.6 k1% resistance. 8 AFEA33V Transceiver unit analo

29、g power supply - This should be connected to 3.3 V. 12 AFEA33G Transceiver unit analog GND 9 - AFED33V Transceiver unit digital power supply - This should be connected to 3.3 V. 2 AFED33G Transceiver unit digital GND 1 - AFEA15V Transceiver unit analog 1.5 V power supply - This should be connected t

30、o 1.5 V. 6 AFEA15G Transceiver unit analog GND 7 - AFED15V Transceiver unit digital 1.5 V power supply - This should be connected to 1.5 V. 13 AFED15G Transceiver unit digital GND 14 - VDD Core power supply - This should be connected to 1.5 V. 40 VIF IO power supply - This should be connected to 3.3

31、 V or 1.8 V. 15, 42, 64 Power supply / GND 41 - DNG l at i g iD DNGD *1) *1) The “L” active and “H” active states of these pins can be specified using the control program for the user system. ” _N” indicates that the “L” active state is the default state. *2) *2) DSTB0_N and DACK1_N are assigned to

32、the same pin, so the functions of one or the other are valid. *3) *3) The input level of the MPBUS pin needs to be established just before the end of H/W reset. Also, this should not be switched during operation. *4) *4) When CS_N and RD_N are “L” , these pins output “H” or “L” . *5) *5) If MPBUS is

33、 “H” , these pins can be made to open. *6) *6) CS_N, WR0_N, and WR1_N should be kept as (a) or (b) during RST_N=” L” (from RST_N goes L to right after RST_N goes H). (a) CS_N=” H” (b) WR0_N=” H” and WR1_N=” H” *7) *7) Discription of “State of pin” (a) Input : Pins are Hi-z state. Please do not make

34、it “open” on a board. (b) Input(Hi-z) : Pins are Hi-z state. Pins can be “open” on a board. (c) H, L, H/L : Output states is shown. *8) *8) These pins are in an inactive state. 42 Q207 : M66592FP CPU bus interface D15-7,D6-1(/AD6-1),D0 A6/ALE,A5-1 CS_N RD_N WR0_N WR1_N MPBUS Interrupt / SOF output I

35、NT_N SOF_N DMA interface DREQ0_N DACK0_N DEND0_N DREQ1_N DACK1_N/DSTB0_N DEND1_N Split bus SD7-0 System control RST_N TEST 16 6 Clock XIN XOUT VBUS monitor input VBUS USB interface DP, DM Reference resistance REFRIN M66592 8 2 PIN FUNCTION CONFIGURATION DIAGRAM A6(/ALE), A5-1, D15-7, D6-1(/AD6-1), D

36、0, CS_N, RD_N, WR0_N,WR1_N MPBUS CPU bus interface INT_N, SOF_N CPU_IF_Reg Int_Ctrl Interrupt /SOF output GroundAFE Ground VDDVIF AFEA33V, AFED33V AFEA15V, AFED15V AFEA33G,AFED33G AFEA15G,AFED15G DGND Buf_Mem BIU FIFO_Port Pipe_Ctrl Prctl_Eng AFE USB interface SPLIT bus SD7-0 DP, DM DREQ0_N, DREQ1_N

37、 DACK0_N, DACK1_N/DSTB0_N, DEND0_N, DEND1_N DMA interafce VBUS monitor input VBUS System control RST_N, TEST Renerence registor REFRIN Clock XIN, XOUT SIE BLOCK DIAGRAM 43 Q301 : LT1615ES5 SW 1 GND 2 FB 3 5 VIN 4 SHDN S5 PACKAGE 5-LEAD PLASTIC SOT-23 TOP VIEW + + 5 400ns ONE-SHOT DRIVER RESET ENABLE

38、 42mV* 0.12 A2 A1 Q3 2 R4 140k R3 30k R6 40k R5 40k Q2 X10 Q1 3 VIN FB 4 SHDN 1 SW GND 1615/-1 BD L1 C2 VOUTVIN D1 R2 (EXTERNAL) R1 (EXTERNAL) VOUT C1 * 12mV FOR LT1615-1 BLOCK DIAGRAM 44 Q304, Q604 : LTC3400BES6 SW 1 GND 2 FB 3 6 VIN 5 VOUT 4 SHDN S6 PACKAGE 6-LEAD PLASTIC SOT-23 TOP VIEW 1.23V REF

39、 Burst Mode OPERATION CONTROL SHUTDOWN CONTROL SLOPE COMP PWM CONTROL START-UP OSC MUX A B A/B RAMP GEN 1.2MHz FB 3400 BD 3 VOUT OPTIONAL SCHOTTKY L1 4.7H 5 SW1VIN SINGLE CELL INPUT 6 SHDN 4 GND2 + gm ERROR AMP + VOUT GOOD + PWM COMPARATOR RC 80k SHUTDOWN CC 150pF CP2 2.5pF R2 604k 1% (EXTERNAL) R1

40、1.02M 1% (EXTERNAL) SLEEP SYNC DRIVE CONTROL 0.35 0.45 2.3V COUT 4.7F 3.3V OUTPUT CIN 1F + CURRENT SENSE CFF (OPTIONAL) BLOCK DIAGRAM 45 Q311 : S-35390A-I8T1G 1 2 3 4 8 7 6 5 VDD SDA SCL INT2 INT1 XOUT XIN VSS SNT-8A (TOP VIEW) Pin No. Symbol Description Configuration 1 INT1 Interrupt 1 signal outpu

41、t pin Depending on the mode set by INT1 register_1 and the status register, it outputs low or a clock when the time is reached. It is disabled by rewriting the status register. Nch open-drain output (no protective diode on the side of VDD) 2 XOUT Crystal oscillator connect pin (32,768 Hz) 3 XIN (Cd

42、built in, Cg external) 4 VSS Negative power supply pin (GND) 5 INT2 Interrrupt 2 signal output pin Depending on the mode set by INT1 register_2 and the status register, it outputs low or clock when time is reached. It is disabled by rewriting the status register. Nch open-drain output (no protective

43、 diode on the side of VDD) 6 SCL Serial clock input pin Since signal processing is done on the SCL signal rising/falling edge, give great care to the rising/falling time and comply strictly with the specifications. CMOS input (no protective diode on the side of VDD) 7 SDA Serial data I/O pin Normall

44、y, it is pulled up to the VDD voltage by a resistor and connected with another open-drain output or open-collector output device via a wired-OR connection. Nch open-drain output (no protective diode on the side of VDD) CMOS input 8 VDD Positive power supply pin PIN DESCRIPTION Realtime data register

45、? Status register_1 Oscillator SCL SDA Power supply voltage detector VDD VSS Comparator 1 Second MinuteHour Day of week DayMonthYear Shift register Serial interface INT1 XIN XOUT INT2 Comparator 2 Clock adjustment register INT1 controller Division, timing generator INT2 controller Constant voltage c

46、ircuit Status register_2 INT1 register_1 INT1 register_2 BLOCK DIAGRAM 46 Q405 : ADG736 PIN CONFIGURATION (10-Lead SOIG) 10 9 8 7 6 1 2 3 4 5 IN1 S1A GND S2A IN2 D1 S1B VDD S2B D2 TOP VIEW (Not to Scale) ADG736 LogicSwitch ASwitch B 0OFFON 1ONOFF Truth Table S1A S1B IN1 S2A S2B IN2 ADG736 D1 D2 SWIT

47、CHES SHOWN FOR A LOGIC 1 INPUT BLOCK DIAGRAM 47 Q412 : TLV320AIC32 LINE_OUT_L+ LINE_OUT_L- LINE_OUT_R+ LINE_OUT_R- HPR+ HPL-/HPLCOM HPL+ MIC2/LINE2L MIC1/LINE1L MIC1/LINE1R MIC3/LINE3R MIC3/LINE3L PGA 0/+59.5dB 0.5dB steps ADC ADC Audio Serial Bus DAC L DAC R DIN DOUT BCLK WCLK I C 2 Control Bus Aud

48、io Clock Generation MCLK Bias/ Reference MICBIAS Voltage Supplies AVDD_DAC AVSS_DAC DRVDD DVDD DVSS IOVDD Volume Ctl & Effects Volume Ctl & Effects DRVDD DRVSS SCL SDA AVSS_ADC RESETB MIC2/LINE2R + + VCM + + + HPR-/HPRCOM/ SPKFC + VCM PGA 0/+59.5dB 0.5dB steps + + SIMPLIFIED BLOCK DIAGRAM 1 (bottom

49、view) 8 9 16 17 24 25 32 This is a test PIN ASSIGNMENTS 48 Q412 : TLV320AIC32 TERMINAL DESCRIPTION NAMEQFN NO.I/O MCLK1IMaster clock input BCLK2I/OAudio serial data bus bit clock input/output WCLK3I/OAudio serial data bus word clock input/output DIN4IAudio serial data bus data input DOUT5OAudio serial data bus data output DVSS6I/ODigital core / I/O Ground Supply, 0 V IOVDD7I/ODigital I/O voltage supply, 1.1 V 3.6 V SCL8I/OI2C serial clock input SDA9I/OI2C