Marantz-UD9004v5-sacd-sm 电路图 维修手册.pdf

《Marantz-UD9004v5-sacd-sm 电路图 维修手册.pdf》由会员分享，可在线阅读，更多相关《Marantz-UD9004v5-sacd-sm 电路图 维修手册.pdf（190页珍藏版）》请在收音机爱好者资料库上搜索。

1、START:|g1cz3Z09ximWbk6cjE4rRA=|O/B7VA7yBQVHcCPDfxgwIpsYp1GCUBgZ0KV4Yh5wOTM=|bzK1xj2aIclqATWPkJDTOw=|:END Service Manual Some illustrations using in this service manual are slightly different from the actual set. Please use this service manual with referring to the operating instructions without fail

2、. UD9004 /U1B/N1B/S1B/R1B UD9004 S0743-1V05DM/DG1309Copyright 2013 D UDQS corresponds to the data on DQ8-DQ15. LDM,UDMInput Data in Mask. Data In is masked by DM Latency=0 when DM is high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. DQ

3、0 DQ15Input/OutputData inputs/Outputs are multiplexed on the same pins. BA0, BA1InputSelects which bank is to be active. A0 A11Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 RA11, Column addresses : CA0 CA8. VDD/VSSPower SupplyPower and ground for the input buffers

4、and core logic. VDDQ/VSSQPower Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. VREFPower SupplyReference voltage for inputs, used for SSTL interface. NC/RFUNo connection/ Reserved for future use This pin is recommended to be left No connection on th

5、e device 54 UD9004 ADV7344BSTZ (8U-310002 : IC802) ADV7344BSTZ Block Diagram 64 GND_IO 63 CLKIN_B 62 S9 61 S8 60 S7 59 S6 58 S5 57 DGND 56 VDD 55 S4 54 S3 53 S2 52 S1 51 S0 50 S_HSYNC 49 S_VSYNC 47RSET1 46VREF 45COMP1 42DAC 3 43DAC 2 44DAC 1 48SFL/MISO 41VAA 40AGND 39DAC 4 37DAC 6 36RSET2 35COMP2 34

6、PVDD 33EXT_LF1 38DAC 5 2 Y0 3Y1 4 Y2 7 Y5 6 Y4 5Y3 1 VDD_IO 8Y6 9Y7 10VDD 12Y8 13 Y9 14 C0 15 C1 16 C2 11 DGND 17 C3 18 C4 19 ALSB/SPI_SS 20 SDA/SCLK 21 SCL/MOSI 2223 P_HSYNC 24 P_VSYNC 25 P_BLANK 26 C6 C5 27 C7 28 C8 29 C9 30 CLKIN_A 3132 PGND PIN 1 ADV7344 TOP VIEW (Not to Scale) EXT_LF2 R GND_IO

7、VDD_IO 10-BIT SD VIDEO DATA 20-BIT ED/HD VIDEO DATA RESETS_HSYNCP_HSYNC P_VSYNC P_BLANKS_VSYNC 14-BIT DAC 1 DAC 1 14-BIT DAC 2 DAC 2 14-BIT DAC 3 DAC 3 14-BIT DAC 4 DAC 4 14-BIT DAC 5 DAC 5 14-BIT DAC 6 DAC 6 MULTIPLEXER REFERENCE AND CABLE DETECT 16x/4x OVERSAMPLING DAC PLL VIDEO TIMING GENERATOR P

8、OWER MANAGEMENT CONTROL CLKIN (2) PVDDPGNDEXT_LFVREFCOMP (2) RSET (2) ED/HD INPUT DEINTERLEAVE PROGRAMMABLE HDTV FILTERS SHARPNESS AND ADAPTIVE FILTER CONTROL YCbCr HDTV TEST PATTERN GENERATOR YCbCr TO RGB MATRIX G/B RGB ASYNC BYPASS RGB DGND (2)VDD (2) SCL/ MOSI SDA/ SCLK ALSB/ SPI_SS SFL/ MISO MPU

9、 PORT SUBCARRIER FREQUENCY LOCK (SFL) YUV TO YCrCb/ RGB PROGRAMMABLE CHROMINANCE FILTER ADD BURST RGB/YCrCb TO YUV MATRIX 4:2:2 TO 4:4:4 HD DDR DEINTERLEAVE SIN/COS DDS BLOCK 16 FILTER 16 FILTER 4 FILTER AGNDVAA ADD SYNC VBI DATA SERVICE INSERTION PROGRAMMABLE LUMINANCE FILTER ADV7344 55 UD9004 ADV7

10、344BSTZ Pin Function Pin No. Mnemonic Input/ Output Description 13, 12, 9 to 2 Y9 to Y0 I 10-Bit Pixel Port (Y9 to Y0). Y0 is the LSB. Refer to Table 31 for input modes. 29 to 25, 18 to 14 C9 to C0 I 10-Bit Pixel Port (C9 to C0). C0 is the LSB. Refer to Table 31 for input modes. 62 to 58, 55 to 51 S

11、9 to S0 I 10-Bit Pixel Port (S9 to S0). S0 is the LSB. Refer to Table 31 for input modes. 30 CLKIN_A I Pixel Clock Input for HD only (74.25 MHz), ED1 only (27 MHz or 54 MHz) or SD only (27 MHz). 63 CLKIN_B I Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or

12、 a 74.25 MHz reference clock for HD operation. 50 S_HSYNC I/O SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD horizontal synchronization signal. See the External Horizontal and Vertical Synchronization Control section. 49 S_VSYNC I/O SD Vertical Synch

13、ronization Signal. This pin can also be configured to output an SD, ED, or HD vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control section. 22 P_HSYNC I ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical Synchronization Cont

14、rol section. 23 P_VSYNC I ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization Control section. 24 P_BLANK I ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section. 48 SFL/MISO I/O Multifunctional Pin: Subcarrier Fre

15、quency Lock (SFL) Input/SPI Data Output. The SFL input is used to drive the color subcarrier DDS system, timing reset, or subcarrier reset. 47 RSET1 I This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive operation (for example, into a 37.5 load), a 510 re

16、sistor must be connected from RSET1 to AGND. For low drive operation (for example, into a 300 load), a 4.12 k resistor must be connected from RSET1 to AGND. 36 RSET2 I This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 k resistor must be connected from RSET2 to

17、 AGND. 45, 35 COMP1, COMP2 O Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to VAA. Pin No. Mnemonic Input/ Output Description 44, 43, 42 DAC 1, DAC 2, DAC 3 O DAC Outputs. Full and low drive capable DACs. 39, 38, 37 DAC 4, DAC 5, DAC 6 O DAC Outputs. Low drive only capable DACs.

18、21 SCL/MOSI I Multifunctional Pin: I2C Clock Input/SPI Data Input. 20 SDA/SCLK I/O Multifunctional Pin: I2C Data Input/Output. Also, SPI clock input. 19 ALSB/SPI_SS I Multifunctional Pin: This signal sets up the LSB2 of the MPU I2C address. Also, SPI slave select. 46 VREF Optional External Voltage R

19、eference Input for DACs or Voltage Reference Output. 41 VAA P Analog Power Supply (3.3 V). 10, 56 VDD P Digital Power Supply (1.8 V). For dual-supply configurations, VDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering. 1 VDD_IO P Input/Output Digital Power Suppl

20、y (3.3 V). 34 PVDD P PLL Power Supply (1.8 V). For dual-supply configurations, PVDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering. 33 EXT_LF1 I External Loop Filter for On-Chip PLL 1. 31 EXT_LF2 I External Loop Filter for On-Chip PLL 2. 32 PGND G PLL Ground Pi

21、n. 40 AGND G Analog Ground Pin. 11, 57 DGND G Digital Ground Pin. 64 GND_IO G Input/Output Supply Ground Pin. 1 ED = enhanced definition = 525p and 625p. 2 LSB = least significant bit. In the ADV7344, setting the LSB to 0 sets the I2C address to 0 xD4. Setting it to 1 sets the I2C address to 0 xD6.

22、56 UD9004 ADV7340BSTZ (8U-310002 : IC808) ADV7340BSTZ Block Diagram 64 GND_IO 63 CLKIN_B 62 S9 61 S8 60 S7 59 S6 58 S5 57 DGND 56 VDD 55 S4 54 S3 53 S2 52 S1 51 S0 50 S_HSYNC 49 S_VSYNC 47RSET1 46VREF 45COMP1 42DAC 3 43DAC 2 44DAC 1 48SFL/MISO 41VAA 40AGND 39DAC 4 37DAC 6 36RSET2 35COMP2 34PVDD 33EX

23、T_LF1 38DAC 5 2Y0 3Y1 4 Y2 7Y5 6Y4 5Y3 1 VDD_IO 8Y6 9Y7 10VDD 12Y8 13 Y9 14C0 15 C1 16 C2 11 DGND 17 C3 18 C4 19 ALSB/SPI_SS 20 SDA/SCLK 21 SCL/MOSI 2223 P_HSYNC 24 P_VSYNC 25 P_BLANK 26 C6 C5 27 C7 28 C8 29 C9 30 CLKIN_A 3132 PGND PIN 1 ADV7340/ADV7341 TOP VIEW (Not to Scale) EXT_LF2 R GND_IO VDD_I

24、O 10-BIT SD VIDEO DATA 20-BIT ED/HD VIDEO DATA RESETS_HSYNCP_HSYNC P_VSYNC P_BLANKS_VSYNC 14-BIT DAC 1 DAC 1 14-BIT DAC 2 DAC 2 14-BIT DAC 3 DAC 3 14-BIT DAC 4 DAC 4 14-BIT DAC 5 DAC 5 14-BIT DAC 6 DAC 6 MULTIPLEXER REFERENCE AND CABLE DETECT 16x/4x OVERSAMPLING DAC PLL VIDEO TIMING GENERATOR POWER

25、MANAGEMENT CONTROL CLKIN (2) PVDDPGNDEXT_LFVREFCOMP (2) RSET (2) ED/HD INPUT DEINTERLEAVE PROGRAMMABLE HDTV FILTERS SHARPNESS AND ADAPTIVE FILTER CONTROL YCbCr HDTV TEST PATTERN GENERATOR YCbCr TO RGB MATRIX G/B RGB ASYNC BYPASS RGB DGND (2)VDD (2) SCL/ MOSI SDA/ SCLK ALSB/ SPI_SS SFL/ MISO MPU PORT

26、 SUBCARRIER FREQUENCY LOCK (SFL) YUV TO YCrCb/ RGB PROGRAMMABLE CHROMINANCE FILTER ADD BURST RGB/YCrCb TO YUV MATRIX 4:2:2 TO 4:4:4 HD DDR DEINTERLEAVE SIN/COS DDS BLOCK 16 FILTER 16 FILTER 4 FILTER AGNDVAA ADD SYNC VBI DATA SERVICE INSERTION PROGRAMMABLE LUMINANCE FILTER ADV7344 57 UD9004 ADV7340BS

27、TZ Pin Function Pin No. Mnemonic Input/ Output Description 13, 12, 9 to 2 Y9 to Y0 I 10-Bit Pixel Port (Y9 to Y0). Y0 is the LSB. Refer to Table 31 for input modes. 29 to 25, 18 to 14 C9 to C0 I 10-Bit Pixel Port (C9 to C0). C0 is the LSB. Refer to Table 31 for input modes. 62 to 58, 55 to 51 S9 to

28、S0 I 10-Bit Pixel Port (S9 to S0). S0 is the LSB. Refer to Table 31 for input modes. 30 CLKIN_A I Pixel Clock Input for HD Only (74.25 MHz), ED1 Only (27 MHz or 54 MHz), or SD Only (27 MHz). 63 CLKIN_B I Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a 7

29、4.25 MHz reference clock for HD operation. 50 S_HSYNCI/O SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD horizontal synchronization signal. See the External Horizontal and Vertical Synchronization Control section. 49 S_VSYNC I/O SD Vertical Synchroniz

30、ation Signal. This pin can also be configured to output an SD, ED, or HD vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control section. 22 P_HSYNCI ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical Synchronization Control se

31、ction. 23 P_VSYNCI ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization Control section. 24 P_BLANKI ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section. 48 SFL/MISO I/O Multifunctional Pin: Subcarrier Frequency L

32、ock (SFL) Input/SPI Data Output. The SFL input is used to drive the color subcarrier DDS system, timing reset, or subcarrier reset. 47 RSET1 I This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive operation (for example, into a 37.5 load), a 510 resistor m

33、ust be connected from RSET1 to AGND. For low drive operation (for example, into a 300 load), a 4.12 k resistor must be connected from RSET1 to AGND. 36 RSET2 I This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 k resistor must be connected from RSET2 to AGND. P

34、in No. Mnemonic Input/ Output Description 44, 43, 42 DAC 1, DAC 2, DAC 3 O DAC Outputs. Full and low drive capable DACs. 39, 38, 37 DAC 4, DAC 5, DAC 6 O DAC Outputs. Low drive only capable DACs. 21 SCL/MOSI I Multifunctional Pin: I2C Clock Input/SPI Data Input. 20 SDA/SCLK I/O Multifunctional Pin:

35、I2C Data Input/Output. Also, SPI clock input. 19 ALSB/SPI_SS I Multifunctional Pin: This signal sets up the LSB2 of the MPU I2C address. Also, SPI slave select. 46 VREF Optional External Voltage Reference Input for DACs or Voltage Reference Output. 41 VAA P Analog Power Supply (3.3 V). 10, 56 VDD P

36、Digital Power Supply (1.8 V). For dual-supply configurations, VDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering. 1 VDD_IO P Input/Output Digital Power Supply (3.3 V). 34 PVDD P PLL Power Supply (1.8 V). For dual-supply configurations, PVDD can be connected to

37、other 1.8 V supplies through a ferrite bead or suitable filtering. 33 EXT_LF1 I External Loop Filter for On-Chip PLL 1. 31 EXT_LF2 I External Loop Filter for On-Chip PLL 2. 32 PGND G PLL Ground Pin. 40 AGND G Analog Ground Pin. 11, 57 DGND G Digital Ground Pin. 64 GND_IO G Input/Output Supply Ground

38、 Pin. 1 ED = enhanced definition = 525p and 625p. 2 LSB = least significant bit. In the ADV7344, setting the LSB to 0 sets the I2C address to 0 xD4. Setting it to 1 sets the I2C address to 0 xD6. 58 UD9004 PT6302-R-001(L) (8U-37AK53000 : IC401) PT6302-R-001(L) Block Diagram 1 66 PIN TSOP(II) (400mil

39、 x 875mil) 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 27 26 25 24 23 22 21 54 53 52 51 50 49 48 47 46 45 44 43 35 36 37 38 39 40 41 42 55 56 57 58 59 60 34 (0.65 mm Pin Pitch) 33 32 31 30 29 28 61 62 63 64 65 66 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ BA0 CS RAS CAS WE LDM VDDQ DQ7

40、 VDD A3 A2 A1 A0 AP/A10 BA1 NC LDQS NC NC NC VDD VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ A11 CKE CK UDM VREF VSSQ DQ8 VSS A4 A5 A6 A7 A8 A9 NC UDQS NC VSS CK NC NC BLOCK DIAGRAM 8-BIT SHIFT REGISTER COMMAND DECODER CONTROL CIRCUIT DIN VDD CLKB OSCO GR1 SG1 P1 AD1 P2 AD2 GR16 SG35 V

41、SS CSB OSCI VEE RSTB DCRAM 16 words x 8 bits CGROM 248 words x 35 bits SEGMENT DRIVER AD DRIVER CGRAM 8 words x 35 bits ADRAM 16 words x 2 bits ADDRESS SELECTOR WRITE ADDRESS COUNTER READ ADDRESS COUNTERPORT DRIVER DIGIT CONTROL GRID DRIVER DUTY CONTROL TIMING GENERATOR 2 TIMING GENERATOR 1 OSCILLAT

42、OR 59 UD9004 PT6302-R-001(L) Pin Function Pin No. Pin Name I/ODescription LQFPSSOP SG5 to SG35 SG4 to SG1 O Segment driver output pin 1 31 64 61 9 39 8 5 GR1 to GR16 O Grid driver output pin 32 4740 55 VEE - Power supply 48 56 VSS - Ground pin 49 57 OSCI I Oscillator input pin 50 58 OSCO O Oscillato

43、r output pin 51 59 RSTB I Reset input pin When this pin is set to LOW, all functions are initialized. 52 60 CSB I Chip select input pin When this pin is set to High Level, the serial data transfer is disabled. 53 61 CLKB I Shift clock input pin The serial data is shifted at the rising edge of CLKB.

44、54 62 DIN I Serial data input pin 55 63 VDD - Positive power supply 56 64 P1 to P2 O General purpose output pin 57 581 2 AD2 to AD1 O Segment driver output pin 59 603 4 60 UD9004 S29GL064N90TFI040# (8U-310002 : IC213) S29GL064N90TFI040# Block Diagram 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 1

45、1 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 A15 A18 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A1 A17 A7 A6 A5 A4 A3 A2 A15 A18 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE# RESET# ACC WP# A19 A1 A17 A7 A6 A5 A4 A3 A2 A16 DQ2 BYTE# VSS DQ15/A-1

46、DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 A16 DQ2 VIO VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 S29GL064N, S29GL032N (Models 03, 04 only) S29GL064N (Models 06, 07, V6, V7 only) NC on S29GL032N Note *AMAX GL064N

47、= A21, GL032N = A20. Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator Timer VCC Detector State Control Command Register VCC VSS WE# WP#/ACC BYTE# CE# OE# STB STB DQ15DQ0 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell

48、 Matrix Address Latch AMax*A0 61 UD9004 S29GL064N90TFI040# Pin Functionp PinDescription A21A022 Address inputs (S29GL064N) A20A021 Address inputs (S29GL032N) DQ7DQ08 Data inputs/outputs DQ14DQ015 Data inputs/outputs DQ15/A-1DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode) CE#C

49、hip Enable input OE#Output Enable input WE#Write Enable input WP#/ACCHardware Write Protect input/Programming Acceleration input ACCAcceleration input WP#Hardware Write Protect input RESET#Hardware Reset Pin input RY/BY#Ready/Busy output BYTE#Selects 8-bit or 16-bit mode VCC 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VIOOutput Buffer Power VSSDevice Ground NCPin Not Connected Internally 62 UD9004 AK4399EQ (8U-210016 : IC101) AK4399EQ Blo