Marantz-SA8001-sacd-sm 电路图 维修手册.pdf

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1、Super Audio CD Player SA8001 SA8001 /F N/K1G/F S/U1B SA8001SA8001 Please use this service manual with referring to the user guide ( D.F.U. ) without fail. Service Manual Part no. 90M29AK855020 First Issue 2006.06 MZ TABLE OF CONTENTS SECTION 1 PAGE 1. TECHNICAL SPEC I FI CA TIONS AND UPDATE DISC . 1

2、-1 2. SERVICE HINTS AND TOOLS . 1-2 3. WARNING AND LASER SAFETY IN STRUC TIONS . 1-3 4. TAKING THE DISC OUT OF EMERGENCY . 1-4 5. UPDATA FIRMWARE . 1-5 6. SERVICE MODE . 1-6 7. BLOCK DIAGRAM . 1-7 8. SCHEMATIC DIAGRAM . 1-9 9. PARTS LOCATION . 1-15 10. MICROPROCESSOR AND IC DATA . 1-21 11. EXPLODED

3、VIEW AND PARTS LIST . 1-25 12. ELECTRICAL PARTS LIST . 1-29 SECTION 2 (MECHA LOADER AND MECHA TRAVERSE) 1. EXPLODED VIEW AND PARTS LIST . 2-2 SECTION 3 (SUPER AUDIO CD PWB MODULE) 1. IC DATA . 3-2 2. BLOCK DI A GRAM . 3-23 3. SCHEMATIC DIAGRAM . 3-25 4. PARTS LOCATION . 3-37 5. ELECTRICAL PARTS LIST

4、 . 3-41 PROGALLTOTALSING AMS REMAINSACD RNDMTRKAB 1 1TEXT23 45 67 89 1011 12 13 14 15 16 17 18 19 20STEREO POWER ON/OFFPOWER ON/OFF SUPER AUDIO CD PLAYER SA8001 PROGALLTOTALSING AMS REMAINSACD RNDMTRKAB 1 1TEXT23 45 67 89 1011 12 13 14 15 16 17 18 19 20STEREO POWER ON/OFFPOWER ON/OFF DISPLAY OFFTEXT

5、TIMESOUND MODE 2nd EDITION The model no.SA8001/K1G was added in this service manual. SA8001/K1G仕向追加。 RadioFans.CN 收音机爱 好者资料库 MARANTZ DESIGN AND SERVICE Using superior design and selected high grade components, MARANTZ company has created the ultimate in stereo sound. Only original MARANTZ parts can

6、insure that your MARANTZ product will continue to perform to the specifi cations for which it is famous. Parts for your MARANTZ equipment are generally available to our National Marantz Subsidiary or Agent. ORDERING PARTS : Parts can be ordered either by mail or by Fax. In both cases, the correct pa

7、rt number has to be specifi ed. The following information must be supplied to eliminate delays in processing your order : 1. Complete address 2. Complete part numbers and quantities required 3. Description of parts 4. Model number for which part is required 5. Way of shipment 6. Signature : any orde

8、r form or Fax. must be signed, otherwise such part order will be considered as null and void. SHOCK, FIRE HAZARD SERVICE TEST : CAUTION : After servicing this appliance and prior to returning to customer, measure the resistance between either primary AC cord connector pins ( with unit NOT connected

9、to AC mains and its Power switch ON ), and the face or Front Panel of product and controls and chassis bottom. Any resistance measurement less than 1 Megohms should cause unit to be repaired or corrected before AC power is applied, and verifi ed before it is return to the user/customer. Ref. UL Stan

10、dard No. 6500. In case of diffi culties, do not hesitate to contact the Technical Department at above mentioned address. 060223MZ USA MARANTZ AMERICA, INC 1100 MAPLEWOOD DRIVE ITASCA, IL. 60143 USA PHONE : 630 - 741 - 0300 FAX: 630 - 741 - 0301 EUROPE / TRADING MARANTZ EUROPE B.V. P. O. BOX 8744, BU

11、ILDING SILVERPOINT BEEMDSTRAAT 11, 5653 MA EINDHOVEN THE NETHERLANDS PHONE : +31 - 40 - 2507844 FAX: +31 - 40 - 2507860 AUSTRALIA QualiFi Pty Ltd, 24 LIONEL ROAD, MT. WAVERLEY VIC 3149 AUSTRALIA PHONE : +61 - (0)3 - 9543 - 1522 FAX: +61 - (0)3 - 9543 - 3677 NEW ZEALAND WILDASH AUDIO SYSTEMS NZ 14 MA

12、LVERN ROAD MT ALBERT AUCKLAND NEW ZEALAND PHONE : +64 - 9 - 8451958 FAX: +64 - 9 - 8463554 THAILAND MRZ STANDARD CO., LTD 746 - 754 MAHACHAI ROAD., WANGBURAPAPIROM, PHRANAKORN, BANGKOK, 10200 THAILAND PHONE : +66 - 2 - 222 9181 FAX: +66 - 2 - 224 6795 TAIWAN PAI- YUING CO., LTD. 6 TH FL NO, 148 SUNG

13、 KIANG ROAD, TAIPEI, 10429, TAIWAN R.O.C. PHONE : +886 - 2 - 25221304 FAX: +886 - 2 - 25630415 MALAYSIA WO KEE HONG ELECTRONICS SDN. BHD. 2ND FLOOR BANGUNAN INFINITE CENTRE LOT 1, JALAN 13/6, 46200 PETALING JAYA SELANGOR DARUL EHSAN, MALAYSIA PHONE : +60 - 3 - 7954 8088 FAX: +60 - 3 - 7954 7088 KORE

14、A MARANTZ KOREA CO., LTD. ROOM 604, ELECTRO OFFICE, 16-58, HANGGANG-RO 3GA, YONGSAN-KU, SEOUL, 140-013, KOREA PHONE : +82 - 2 - 323 - 2155 FAX: +82 - 2 - 323 - 2154 SINGAPORE WO KEE HONG DISTRIBUTION PTE LTD No.1 JALAN KILANG TIMOR #08-03 PACIFIC TECH CENTRE SINGAPORE 159303 PHONE : +65 6376 0338 FA

15、X: +65 6376 0166 CANADA MARANTZ CANADA INC. 5-505 APPLE CREEK BLVD. MARKHAM, ONTARIO L3R 5B1 CANADA PHONE : 905 - 415 - 9292 FAX: 905 - 475 - 4159 JAPAN D either 128x, 192x 256x or 384x the input sample rate in Double Speed Mode; or 64x, 96x 128x or 192x the input sample rate in Quad Speed Mode. Tab

16、les 4-6 illustrate the standard audio sample rates and the required master clock frequencies. Sample Rate (kHz) MCLK (MHz) 256x384x512x768x 328.192012.288016.384024.5760 44.111.289616.934422.579233.8688 4812.288018.432024.576036.8640 Table 4. Single Speed (16 to 50 kHz sample rates) Common Clock Fre

17、quencies Serial Clock - SCLK Pin 11, Input Function: Clocks individual bits of serial data into the SDATA pin. The required relationship between the Left/Right clock, serial clock and serial data is defi ned by either the Mode Control Byte in Control Port Mode or the M0 - M4 pins in Hardware Mode. T

18、he options are detailed in Figures 29-33 Left/Right Clock - LRCK Pin 12, Input Function: The Left/Right clock determines which channel is currently being input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in Left/Right s

19、ample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period difference. The required relationship between the Left/Right clock, serial clock and serial data is defi ned by the Mode Control Byte and the options are de- taile

20、d in Figures 29-33 Serial Audio Data - SDATA Pin 13, Input Function: Serial audio data is input on this pin. The selection of the Digital Interface Format is determined by set- tings of the Mode select as detailed in Figures 29-33. The data is clocked into SDATA via the serial clock and the channel

21、is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defi ned by the Mode Control Byte and the options are detailed inin Figures 29-33 Soft Mute - MUTE Pin 15, Input Function: The analog outputs will ramp to a muted state when

22、 enabled. The ramp requires 1152 left/right clock cy- cles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The bias volt- age on the outputs will be retained and MUTEC will go active at the completion of the ramp period. The analog outputs will ramp to a normal state

23、 when this function transitions from the enabled to disabled state. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The MUTEC will release immediately on setting MUTE = 1. The converter analog outputs will mute when enab

24、led. The bias voltage on the outputs will be retained and MUTEC will go active during the mute period. MuteDESCRIPTION 0Enabled 1Normal operation mode PCM MODE 1 2 3 4 5 6 7 8 9 10 11 12 5 1 2 6 28 27 26 25 24 23 22 21 20 19 18 17 13 14 16 15 ResetRSTVREFVoltage Reference See DescriptionM4(AD0/CS)FI

25、LT+Reference Filter See DescriptionM3(AD1/CDIN)FILT-Reference Ground See DescriptionM2(SCL/CCLK)CMOUTCommon ModeS Voltage See Description M0(SDA/CDOUT)AOUTL-Differential Output Digital GroundDGNDAOUTL+Differential Output Digital PowerVDVAAnalog Power Digital PowerVDAGNDAnalog Ground Digital GroundDG

26、NDAOUTR+Differential Output Master ClockMCLKAOUTR-Differential Output Serial ClockSCLKAGNDAnalog Ground Left/Right ClockLRCKMUTECMute Control Serial DataSDATAC/HControl port/Hardware select See DescriptionM1MUTESoft Mute 1-231-24 SCLK MCLK M4 LRCK SDATA AOUTL+ AOUTR+ SERIAL INTERFACE AND FORMAT SELE

27、CT INTERPOLATION SOFT MUTE MODULATOR DYNAMIC DE-EMPHASIS SWITCHED AOUTL- AOUTR- FILT+ FILTER INTERPOLATION FILTER FILTER MULTI-BIT MODULATOR MULTI-BIT ELEMENT MATCHING LOGIC DYNAMIC ELEMENT MATCHING LOGIC CAPACITOR-DAC AND FILTER SWITCHED CAPACITOR-DAC AND FILTER VREFCMOUTFILT- VOLTAGE REFERENCE HAR

28、DWARE MODE CONTROL CLOCK DIVIDER (CONTROL PORT) (AD0/CS) M3M2 (AD1/CDIN) (SCL/CCLK) M1M0 (SDA/CDOUT) RESETMUTEC MUTE QD61 : CS4397 Master Clock - MCLK Pin 10, Input Function: The master clock frequency must be either 4x or 6x the DSD data rate for 64x oversampled DSD data and 2x or 3x the DSD data r

29、ate for 128x oversampled DSD data, refer to Table 7. CLKMODE Pin 12, Input Function: This pin determines the allowable Master Clock to DSD data ratio as defi ned in Table 7. CLKMODE 01 DSD Over-Sampling Ratio 64x4x6x 128x2x3x Table 7. MCLK to DSD Data Rate Clock Ratios DSD Serial Clock -DSD_SCLK Pin

30、 11, Input Function: Clocks the individual bits of the DSD audio data into the DSD_L and DSD_R pins. Audio Data -DSD_L and DSD_R Pins 13 and 14, Inputs Function: Direct Stream Digital audio data is clocked into DSD_L and DSD_R via the DSD serial clock. DSD MODE Refer to PCM modeRST VREFRefer to PCM

31、mode Refer to PCM mode M4(ADO/CS)FILT+Refer to PCM mode Refer to PCM modeM3(AD1/CDIN)FILT-Refer to PCM mode Refer to PCM modeM2(SCL/CCLK)CMOUTRefer to PCM mode Refer to PCM mode M0(SDA/CDOUT)AOUTL-Refer to PCM mode Refer to PCM modeDGNDAOUTL+Refer to PCM mode Refer to PCM modeVDVARefer to PCM mode R

32、efer to PCM modeVDAGNDRefer to PCM mode Refer to PCM modeDGNDAOUTR+Refer to PCM mode Master ClockMCLKAOUTR-Refer to PCM mode DSD Serial ClockDSD_SCLKAGNDRefer to PCM mode Master Clock ModeCLKMODE MUTECRefer to PCM mode Left Channel DataDSD_LC/HRefer to PCM mode Right Channel DataDSD_RMUTERefer to PC

33、M mode 1 2 3 4 5 6 7 8 9 10 11 12 5 1 2 6 28 27 26 25 24 23 22 21 20 19 18 17 13 14 16 15 Control Port / Hardware Mode Select - C/H Pin 16, Input Function: Determines if the device will operate in either the Hardware Mode or Control Port Mode. C/HDESCRIPTION 0Hardware Mode Enabled 1Control Port Mode

34、 Enabled Mute Control - MUTEC Pin 17, Output Function: The Mute Control pin goes low during power-up initialization, reset, muting, master clock to left/right clock frequency ratio is incorrect or power-down. This pin is intended to be used as a control for an external mute circuit to prevent the cl

35、icks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Analog Ground - AGND Pins 18 and 21, Inputs Function: Analog ground reference. Differential Analog Outpus - AOUTR-

36、, AOUTR+ and AOUTL- , AOUTL+ Pins 19, 20, 23 and 24, Outputs Function: The full scale differential analog output level is specifi ed in the Analog Characteristics specifi cations table. Analog Power - VA Pin 22, Input Function: Power for the analog and reference circuits. Typically 5VDC. Common Mode

37、 Voltage - CMOUT Pin 25, Output Function: Filter connection for internal bias voltage, typically 50% of VREF. Capacitors must be connected from CMOUT to analog ground, as shown in Figure 6. CMOUT has a typical source impedence of 25 k and any current drawn from this pin will alter device performance

38、 Reference Ground - FILT- Pin 26, Input Function: Ground reference for the internal sampling circuits. Must be connected to analog ground. Reference Filter - FILT+ Pin 27, Output Function: Positive reference for internal sampling circuits. External capacitors are required from FILT+ to analog ground

39、, as shown in Figure 6. FILT+ is not intended to supply external current. Voltage Reference Input- VREF Pin 28, Input Function: Analog voltage reference. Typically 5VDC. HARDWARE MODE Mode Select - M0, M1, M2, M3, M4 Pins 2, 3, 4, 5 and 14, Inputs Function: The Mode Select pins determine the operati

40、onal mode of the device as detailed in Tables 9-14. The op-tions include; Selection of the Digital Interface Format which determines the required relationship between the Left/Right clock, serial clock and serial data as detailed in Figures 29-33 Selection of the standard 15 s/50 s digital de-emphas

41、is fi lter response, Figure 28, which requires re-confi guration of the digital fi lter to maintain the proper fi lter response for 32, 44.1 or 48 kHz sample rates. Selection of the appropriate clocking mode to match the input sample rates. Access to the Direct Stream Digital Mode Access to the 8x I

42、nterpolation Input Mode CONTROL PORT MODE Address Bit 0 / Chip Select - AD0 / CS Pin 2, Input Function: In I2C mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The device will enter the SPI mode at anytime a high to low transition is detected on this pin.

43、 Once the device has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle. Address Bit 1 / Control Data Input - AD1/CDIN Pin 3, Input Function: In I2C mode, AD1 is a chip address bit. CDIN is the control data input line for the control port interface in

44、 SPI mode. Serial Control Interface Clock - SCL/CCLK Pin 4, Input Function: In I2C mode, SCL clocks the serial control data into or from SDA/CDOUT. In SPI mode, CCLK clocks the serial data into AD1/CDIN and out of SDA/CDOUT. Serial Control Data I/O - SDA/CDOUT Pin 5, Input/Output Function: In I2C mode, SDA is a data input/output. CDOUT is the control data output for