Yamaha-mLAN16E-meb-sm 电路图 维修手册.pdf

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1、mLAN16E 1 SERVICE MANUAL SY 011725 HAMAMATSU, JAPAN 20040325-49800 CONTENTS SPECIFICATIONS. 3 PANEL LAYOUT. 4 BLOCK DIAGRAM. 5 CIRCUIT BOARD LAYOUT. 6 DISASSEMBLY PROCEDURE. 7 LSI PIN DESCRIPTION. 8 IC BLOCK DIAGRAM. 14 CIRCUIT BOARDS. 15 TEST PROGRAM. 19/23 PARTS LIST CIRCUIT DIAGRAM mLAN16E mLAN E

2、XPANSION BOARD Copyright (c) Yamaha Corporation. All rights reserved. PDF-K247 04.03 （目次） （総合仕様） （） （） （） （分解手順） （LSI端子機能表） （IC図） （基板図） （） （回路図） RadioFans.CN 收音机爱 好者资料库 2 mLAN16E WARNING: CHEMICAL CONTENT NOTICE! The solder used in the production of this product contains LEAD. In addition, other ele

3、ctrical/electronic and/or plastic (Where applicable) components may also contain traces of chemicals found by the California Health and Welfare Agency (and possibly other entities) to cause cancer and/or birth defects or other reproductive harm. DO NOT PLACE SOLDER, ELECTRICAL/ELECTRONIC OR PLASTIC

4、COMPONENTS IN YOUR MOUTH FOR ANY REASON WHAT SO EVER! Avoid prolonged, unprotected contact between solder and your skin! When soldering, do not inhale solder fumes or expose eyes to solder/flux vapor! If you come in contact with solder or components located inside the enclosure of this product, wash

5、 your hands before handling food. IMPORTANT NOTICE This manual has been provided for the use of authorized Yamaha Retailers and their service personnel. It has been assumed that basic service procedures inherent to the industry, and more specifically Yamaha Products, are already known and under- sto

6、od by the users, and have therefore not been restated. WARNING :Failure to follow appropriate service and safety procedures when servicing this product may result in per- sonal injury, destruction of expensive components and failure of the product to perform as specified. For these reasons, we advis

7、e all Yamaha product owners that all service required should be performed by an authorized Yamaha Retailer or the appointed service representative. IMPORTANT :This presentation or sale of this manual to any individual or firm does not constitute authorization certifi- cation, recognition of any appl

8、icable technical capabilities, or establish a principal-agent relationship of any form. The data provided is belived to be accurate and applicable to the unit(s) indicated on the cover. The research engineering, and service departments of Yamaha are continually striving to improve Yamaha products. M

9、odifications are, therefore, inevitable and changes in specification are subject to change without notice or obligation to retrofit. Should any discrepancy appear to exist, please contact the distributors Service Division. WARNING :Static discharges can destroy expensive components. Discharge any st

10、atic electricity your body may have accumulated by grounding yourself to the ground bus in the unit (heavy gauge black wires connect to this bus.) IMPORTANT :Turn the unit OFF during disassembly and parts replacement. Recheck all work before you apply power to the unit. Components having special cha

11、racteristics are marked and must be replaced with parts having specification equal to those originally installed. WARNING 印商品、安全維持重要部品。交換場合、安全必指定部品使用。 RadioFans.CN 收音机爱 好者资料库 mLAN16E 3 SPECIFICATIONS 機能 Data RateS400,S200（付属mLAN Graphic Patchbay 、自動設定） Audio 入出力16In 16Out（MOTIF ES 接続場合、4StereoIN 、16

12、OUT ） 対応周波数 44.1kHz 、48kHz 、88.2kHz 、96kHz (+6%, 10%) （機Fs 変更、 mLAN上種Fs 可能） MIDI 入出力数 6In 6Out（MOTIF ES 接続場合、4IN 、4OUT ） PLL応答性切替slow/fast （付属mLAN Graphic Patchbay mLAN Auto Connector 設定可能） 表示 LEDACTIVE(青） 接続端子 To IEEE13946Pin x 2 To Mother100P 寸法、重量127mm (W)x 164.5mm (D)x 36mm (H) 325g （接続用無）,415g

13、（接続用付） 総合仕様 Functions Data RateS400, S200(Automatically set by included mLAN Graphic Patchbay.) Audio Inputs and Outputs 16 Ins, 16 Outs(4 Stereo Ins, 16 Outs when MOTIF ES is connected.) Sampling rate44.1kHz, 48kHz, 88.2kHz, 96kHz (+6%, 10%) (Enables you to match other sampling frequencies in the n

14、etwork without changing the rate on the mother unit.) MIDI connectors 6 Ins, 6 Outs(4 Ins, 4 Outs when MOTIF ES is con-nected.) Wordclock Transition Speed setting Slow/Fast mode(Specified by included mLAN Graphic Patchbay or Auto Connector.) Display LEDACTIVE (blue) Jacks To IEEE13946-pin x 2 To Mot

15、her100P Dimensions 127(W) x 164.5(D) x 36(H) mm Weight 325g (excluding mother unit connecting cables) 415g (including mother unit connecting cables) RadioFans.CN 收音机爱 好者资料库 4 mLAN16E PANEL LAYOUT Front view q mLAN (EEE1394) connectors w ACTIVE lamp （） （mLAN（IEEE1394）端子） （ ） mLAN16E 5 BLOCK DIAGRAM M

16、L2 SRC ACTIVE IEEE1394 I/F PHY 1 2 Xtal Up to 393.216MHz by Internal PLL PHY - LINK I/F EEPROM (16Kbit) I C GUID/ModuleName/Config. Xtal Up to 40MHz by Internal PLL SCLK mLAN-PH2 AUDIO Packet Isochronous Bus ICLK 3.072MHz,48KHz for MIDI Packet CPLD Phase Comparator VCO PCA(SYT-Match) PCB(DividerOut)

17、 512fs PLL LPF Control Voltage PLL-Response(PLLRESP) LowJitter/VariPitchFollowing PLL-Lock CPU Bus mLAN-NC1s CPU core (BusClock=20MHz) MIDI IN/OUT (4port) UART (1port/38400bps) Exp.I/O port CPLD Divider PLL-Response Packet-Master/Slave SRC-Bypass SRC SRC +5V Regulator +3.3V Packet-Master/Slave Packe

18、t-Master/Slave MIDI (UART) I/F 16bit CPU bus I/F mLAN2 I/F ACTV SRC:Custum 16ch I/O Sampling Rate Converter Tx Digital Audio (16ch) Rx Digital Audio (16ch) Digital Audio I/F +5V +3.3V DigitalAudio Format:24bit/MSB-First/LeftJustified/2ch line WCK (Fs) ,BCK (64Fs) WCK(Fs) Selector Fs=44.1KHz 16bit 8b

19、it 8bit 16bit 8bit 100pin Connector Reset(Host-Active,Audio-MUTE) Selector ECKO(256Fs) MCK (256Fs) ACTV mLAN-NC1 MIDI Packet CN007 (52P) CN001 (52P) IC001 (100P) CN006 (100P) IC002 (100P) 110,111 333 29,30 38,39 42,43 14,15 6,5 IC009 (8P) IC010 (64P) IC014 (100P) IC004 (3P) IC002 (14P) IC007 (208P)

20、IC008 (256P) CN002 CN003 57 4 6 5 58 a:24-27 (MIDI IN) b:24-27 (MIDI OUT) a:22 b:22 92-95 209IN 210OUT MIDI IN MIDI OUT 97-100 R4,R10,C6,C7 C3 TR1 6 12 3 69 76 232 89 AUDIO IN(1-8) 147,149-151,153-155,157 WCKI BCKI 90 88 b:23 ECKI 82IC044 4 a:6-13a:3-10 71-74, 57-60 52-55 66-69, b:3-10 a:2,3 a:4 b:6

21、-13 a:46 35 IC014 (100P) LOCKN a:22,21 3 32,94 IC003 (16P) b:12-19 66-69, 52-55 71-74, 57-60 a:12-19 114,116,118-120,122-124 AUDIO OUT(1-8) 108 1 100 BCK(64Fs) b:22 11,14 2 19,12 6,10 33,93 3,13 32,94 33,93 78 30 b:1 29 21 36 IC037 (20P) MIDI IN/OUT (2port) 2 56 102 IC004 (20P) 13,11 b:21 Buffer 7,9

22、 44,82 43,83 a:19,20 (MIDI IN) b:19,20 (MIDI OUT) Buffer 38,39 58,60 MIDI IN MIDI OUT 15,165,4 9,8 11,12 a:23 48 Vcc 1,19,29,34,59 75,81,85,89,96,109,117 134,148,161,176 194,219,226,242 Vcc 20 +3.3D 20 +3.3D 16 +3.3D *a *a: 1,18,20,26,37,45, 51,61,70,76,85,95 +3.3D *a Vcc 16 93 90 BCKI Vcc 2,7,17,18

23、,22,53 +3.3A 28,32,35,47 3,4 44,45 5,6 3,4 5,6 40,41 8-11,13-16 20-23,25-28 Vcc 8 Vcc 3,18,34,39,61,56 LD4 Vcc 4,11,22,33,43,51,59,66,78,91, 103,110,117,126,129,132,143, 152,160,168,178,190,201 14 Vcc 1 IC00416 12 8 4 IC004 18 14 7 4 43,83 44,82 2 6 Vcc=+3.3V 42,43 17,96 NCD 0-7 NCA 0-8 3,205,206,20

24、8 169,170,173,175-177,179,182NCD 0-7: NCA 0-8:192-200 *b *b IDATA 0-15 1,2,6-10,21,23 IDATA 0-15: 28,29,32,34-36,39,40, 42,44-46,48-50,52 *c *c NCWCKI,NCBCKI (S400) 229,230,232,227,256,255,254 253,252 IDATA 0-15 : 234-241,243-250 *e *e 69,120,123 NCD 0-7: 137-140,142-147,149-154 NCA 0-8: 164-168,170

25、-175,177-180, 184,186,188,190 （） 6 mLAN16E CIRCUIT BOARD LAYOUT MLN2 SRC Top view （） mLAN16E 7 DISASSEMBLY PROCEDURE 1.SRC Circuit Board (Time required: About 1 minutes) 1-1.Remove the two (2) double locking spacers. The SRC circuit board can then be removed. (Photo. 1) 2.SRC Circuit Board (Time req

26、uired: About 1 minutes) 2-1.Remove the SRC circuit board. (See Procedure 1.) 2-2.Remove the two (2) screw marked 30 and the two (2) screw marked 40. The MLN2 circuit board can then be removed. (Photo. 1, 2) 30 40 Support, PCB （） SRC MLN2 Front view Top view 30: Bind Head Tapping Screw-S 4.0X8 MFZN2B

27、L (V6655200) Photo. 1 40: Bind Head Tapping Screw-B 3.0X6 MFNI33 (VZ544100) Photo. 2 （分解手順） 1.SRC (所要時間:約1分) 1-1. 2 所外、SRC 外。 (写真1) 2.MLN2 (所要時間:約1 分) 2-1.SRC 外。 (1項参照) 2-2.302本40 2本外、 MLN2 外。 (写真1, 2) （） （写真1） （） （写真2） 8 mLAN16E LSI PIN DESCRIPTION S1L54423F21B000 (X4072A00) SRC16 . 8 YTS440B-FZ (X

28、3009B00) mLAN-PH2 . 9 mLAN-NC1 (X2150A00) mLAN TM Link Controller.10/11 XCR3064XL-10 (X3628C00) CPLD. 12 MD8408B (XZ762A00) PHY (Physical Layer) . 13 SRC: IC001,002 PIN NO. I/OFUNCTIONNAME PIN NO. I/OFUNCTIONNAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

29、33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD JUMPSEL TABLESEL SCANENB ATPGENE VSS PLLTEST PLLRESN PLLVSS MVDD PLLVSS AVDD PLLCHGO LPVSS PLLBP VSS EXTCLK1 VDD EXTCLK0 VDD TESTENB TESTIP0 TESTIP1 TESTIP2 VSS VDD PHASEMATCH VSS XI XO VSS BOBCLK BOLRCK BOFMT2 BOFMT1 BOFMT0 VDD BIFMT2 BIFMT1

30、 BIFMT0 VSS B_WCK_OK BIBCLK BILRCK VDD BISFTUP1 BISFTUP0 BIBYPASS BODAMPN VSS - I I I I - I I - - - - O I I - I - O - I I I I - - I - I O - I/O I/O I I I - I I I - O I/O I/O - I I I I - Power supply +3.3V Digital PLL sensitivity select Digital PLL capture speed select Test pin (GND connect with norm

31、al) Test pin (GND connect with normal) Ground Test pin (GND connect with normal) Reset input (Master clock PLL) Ground (Master clock PLL) Power supply (Digital) Ground (Master clock PLL) Power supply (Analog) Output signal for external filter of master clock PLL Input signal for external filter of m

32、aster clock PLL Test pin (GND connect with normal) Ground (Digital) Input for master clock PLL Power supply +3.3V (Digital) Output XO terminal Power supply +3.3V Test pin (GND connect with normal) Test pin (GND connect with normal) Test pin (GND connect with normal) Test pin (GND connect with normal

33、) Ground Power supply +3.3V Phase muching mode ON/OFF Ground Crystal osc. input Crystal osc. output Ground Bit clock input/output for B block data output Word clock input/output for B block data output Data output format for B block Data output format for B block Data output format for B block Power

34、 supply +3.3V Data input format for B block Data input format for B block Data input format for B block Ground Lock frag for B block input/output Bit clock input/output for B block data input Word clock input/output for B block data input Power supply +3.3V Shiftup for B block input data Shiftup for

35、 B block input data Bypass for B block input/output Damp output data for B block Ground 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VDD BOSD3 BOSD2 BOSD1 BOSD0 VSS BISD3 BISD2 BISD1 BISD0 VDD D

36、IVSEL1 DIVSEL0 DIVCLK0 VSS AOSD3 AOSD2 AOSD1 AOSD0 VDD AISD3 AISD2 AISD1 AISD0 VSS VDD AODAMPN AIBYPASS AISFTUP0 AISFTUP1 VSS AILRCK AIBCLK A_WCK_OK VDD AIFMT0 AIFMT1 AIFMT2 VSS AOFMT0 AOFMT1 AOFMT2 AOLRCK AOBCLK VDD REGDAT REGCLK REGENB ICN VSS - O O O O - I I I I - I I O - O O O O - I I I I - - I

37、I I I - I/O I/O O - I I I - I I I I/O I/O - I I I I - Power supply +3.3V Serial data output for B block Serial data output for B block Serial data output for B block Serial data output for B block Ground Serial data input for B block Serial data input for B block Serial data input for B block Serial

38、 data input for B block Power supply +3.3V Clock frequency for DIVCLK0 terminal Clock frequency for DIVCLK0 terminal Master clock output Ground Serial data output for A block Serial data output for A block Serial data output for A block Serial data output for A block Power supply +3.3V Serial data i

39、nput for A block Serial data input for A block Serial data input for A block Serial data input for A block Ground Power supply +3.3V Damp output data for A block Bypass for A block input/output Shiftup for A block input data Shiftup for A block input data Ground Word clock input/output for A block i

40、nput data Bit clock input/output for A block input data Lock frag for A block input/output Power supply +3.3V Data input format for A block Data input format for A block Data input format for A block Ground Data output format for A block Data output format for A block Data output format for A block

41、Word clock input/output for A block output data Bit clock input/output for A block output data Power supply +3.3V Data input for serial register Clock input for serial register Enable signal input for serial register Initial clear input Ground S1L54423F21B000 (X4072A00) SRC16 （LSI 端子機能表） mLAN16E 9 P

42、IN NO. I/OFUNCTIONNAME PIN NO. I/OFUNCTIONNAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 8

43、8 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 IRERRN IRCVN IRXN VDD VSS ICLK CYCLEOUT ICS CT ITXN VDD VSS NC NC SCANE TSTI0 TSTI1 TSTI2 TSTI3 VSS ITREQN VDD IEOPN NC NC NC VSS IDATA0 IDATA1 NC NC IDATA2 VDD IDATA3 IDATA4 IDATA5 VSS NC IDATA6 IDATA7 NC IDATA8 VDD IDATA9 IDATA10 IDATA11 VSS I

44、DATA12 IDATA13 IDATA14 VDD IDATA15 SEQO DBC VSS LOCKN PCA PCB VDD TSTI4 TSTI5 TSTI6 TSTI7 NC TXE VDD NC VSS VCOCLK SVCO0 SVCO1 SMCK0 NC NC SMCK1 SLV SEQI VDD NC NC VSS ECKI EWCKI PAR PDIR PDE BCK128I BCKI NC WCKI VDD VSS SWCK TSTI8 TSTI9 TSTI10 TSTI11 VSS NC WCKOD WCKO BCKO VDD NC I I I - - I I I I

45、I I I - - I I I I I - OD - OD - - - - I/O I/O - - I/O - I/O I/O I/O - - I/O I/O - I/O - I/O I/O I/O - I/O I/O I/O - I/O O O - O O O - I I I I - I/O - - - I I I I - - I I I - - - - I I I I I I I - I - - I/O I I I I - - O O O - - Isochronous packet error flag input (Low active) Isochronous reception e

46、nable input (Low active) Isochronous reception data enable input (Low active) +3.3 V Ground Isochronous master clock input (24.576MHz) Isochronous cycle out signal input Isochronous cycle start signal input Isochronous cycle timer enable input Isochronous transmission data enable input (Low active)

47、+3.3 V Ground Input for LSI test (usually connected to ground) Input for LSI test (usually connected to ground) Ground Isochronous transmission request output (Low active) +3.3 V Isochronous transmission packet test data signal output (Low active) Ground Isochronous data input/output Isochronous dat

48、a input/output +3.3 V Isochronous data input/output Ground Isochronous data input/output Isochronous data input/output +3.3 V Isochronous data input/output Ground Isochronous data input/output +3.3 V Isochronous data input/output Loop connection output when 2 to 4 chips are used simultaneously DBC timing output Ground PLL lock flag output (Low active) Output for PLL external phase comaparator Output for PLL external phase comapa