Denon-AVRX4000-avr-sm 电路图 维修手册.pdf

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1、MODELJPE3E2EKEAE1E1KE1C AVR-X4000PPP INTEGRATED NETWORK AV RECEIVER Ver. 1 Please use this service manual with referring to the operating instructions without fail. Some illustrations using in this service manual are slightly different from the actual set. For purposes of improvement, specifications

2、 and design are subject to change without notice. e SERVICE MANUAL e D this pad must be robustly connected to GND. 175 W9864G6JH-6 (DIGITAL : IC409) W9864G2IH Publication Release Date: Aug. 28, 2009 - 4 - Revision A03 4. PIN CONFIGURATION 176 W9864G6JH-6 Block diagram W9864G2IH Publication Release D

3、ate: Aug. 28, 2009 - 6 - Revision A03 6. BLOCK DIAGRAM DQ0 DQ31 DQM03 CLK CKE A10 CLOCK BUFFER COMMAND DECODER ADDRESS BUFFER REFRESH COUNTER COLUMN COUNTER CONTROL SIGNAL GENERATOR MODE REGISTER COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #2 COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #0 COLU

4、MN DECODER SENSE AMPLIFIER CELL ARRAY BANK #3 DATA CONTROL CIRCUIT DQ BUFFER COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #1 ROW DECODER ROW DECODER ROW DECODERROW DECODER A0 A9 BS0 BS1 CS RAS CAS WE 177 W9864G6JH-6 Pin description Publication Release Date: Aug. 28, 2009 - 5 - Revision A03 5. PIN

5、DESCRIPTION PIN NUMBER PIN NAME FUNCTION DESCRIPTION 24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 A0A10 Address Multiplexed pins for row and column address. Row address: A0A10. Column address: A0A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank select

6、ed by BS0, BS1. 22, 23 BS0, BS1 Bank Select Select bank to activate during row address latch time, or bank to read/write during address latch time. 2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82, 83, 85 DQ0DQ31 Data Input/ Output Mul

7、tiplexed pins for data output and input. 20 CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. 19 RAS Row Address Strobe Command input. When sampled at the rising edge of the clock RAS , CAS and WE define t

8、he operation to be executed. 18 CAS Column Address Strobe Referred to RAS 17 WE Write Enable Referred to RAS 16, 28, 59, 71 DQM0DQM3 Input/Output Mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the writ

9、e operation with zero latency. 68 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. 67 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. 1, 15, 29, 43 VDD Power Power fo

10、r input buffers and logic circuit inside DRAM. 44, 58, 72, 86 VSS Ground Ground for input buffers and logic circuit inside DRAM. 3, 9, 35, 41, 49, 55, 75, 81 VDDQ Power for I/O Buffer Separated power from VDD, to improve DQ noise immunity. 6, 12, 32, 38, 46, 52, 78, 84 VSSQ Ground for I/O Buffer Sep

11、arated ground from VSS, to improve DQ noise immunity. 14, 21, 30, 57, 69, 70, 73 NC No Connection No connection. 178 MX25L1606EM2I-12G(DIGITAL:IC410,IC423) MX25L1606EM2I-12G Block Diagram 8-PIN SOP (200mil, 150mil) BLOCK DIAGRAM 179 PCM5100 (DIGITAL:IC552,553) PCM5100 Block Diagram PCM510X (top view

12、) Table 2. TERMINAL FUNCTIONS, PCM510 x TERMINAL I/ODESCRIPTION NAMENO. CPVDD1-Charge pump power supply, 3.3V CAPP2OCharge pump flying capacitor terminal for positive rail CPGND3-Charge pump ground CAPM4OCharge pump flying capacitor terminal for negative rail VNEG5ONegative charge pump rail terminal

13、 for decoupling, -3.3V OUTL6OAnalog output from DAC left channel OUTR7OAnalog output from DAC right channel AVDD8-Analog power supply, 3.3V AGND9-Analog ground DEMP10IDe-emphasis control for 44.1kHz sampling rate(1): Off (Low) / On (High) FLT11IFilter select : Normal latency (Low) / Low latency (Hig

14、h) SCK12ISystem clock input BCK13IAudio data bit clock input DIN14IAudio data input LRCK15IAudio data word clock input FMT16IAudio format selection : I2S (Low) / Left justified (High) XSMT17ISoft mute control : Soft mute (Low) / soft un-mute (High) LDOO18-Internal logic supply rail terminal for deco

15、upling DGND19-Digital ground DVDD20-Digital power supply, 3.3V (1)Failsafe LVCMOS Schmitt trigger input Audio Interface 8x Interpolation Filter 32bit Modulator Current Segment DAC Current Segment DAC I/VI/V Analog Mute Analog Mute Zero Data Detector UVP/Reset PLL Clock Power Supply Ch. PumpPOR Clock

16、 Halt Detection Advanced Mute Control MCK BCK LRCK CAPP CAPM VNEG LINE OUT DIN (i2s) PCM510 x CPVDD (3.3V) AVDD (3.3V) DVDD (3.3V) GND Figure 1. PCM510 x Functional Block Diagram 180 AK5358BET (DIGITAL : IC451) AK5358BET Pin Function 181 PCM1690(DIGITAL:IC441,IC541) PCM1690 Pin Function TERMINAL I/O

17、 PULL- DOWN 5-V TOLERANT DESCRIPTION NAMEPIN RSV21Reserved, tied to analog ground RSV12Reserved, left open RSV23Reserved, tied to analog ground RSV14Reserved, left open RSV25Reserved, tied to analog ground LRCK6IYesNoAudio data word clock input BCK7IYesNoAudio data bit clock input DIN18INoNoAudio da

18、ta input for DAC1 and DAC2 DIN29INoNoAudio data input for DAC3 and DAC4 DIN310INoNoAudio data input for DAC5 and DAC6 DIN411INoNoAudio data input for DAC7 and DAC8 VDD12Digital power supply, +3.3 V DGND13Digital ground SCKI14INoYesSystem clock input RST15IYesYesReset and power-down control input wit

19、h active low ZERO116ONoNoZero detect flag output 1 ZERO217ONoNoZero detect flag output 2 AMUTEI18INoYesAnalog mute control input with active low AMUTEO19ONoYesAnalog mute status output(1) with active low MD/SDA/DEMP20I/ONoYesInput data for SPI, data for I2C(1), de-emphasis control for hardware contr

20、ol mode MC/SCL/FMT21INoYesClock for SPI, clock for I2C, format select for hardware control mode MS/ADR0/RSV22IYesYes Chip Select for SPI, address select 0 for I2C, reserve (set low) for hardware control mode TEST/ADR1/RSV23I/ONoYes Test (factory use, left open) for SPI, address select 1 for I2C, res

21、erve (set low) for hardware control mode MODE24INoNoControl port mode selection. Tied to VDD: SPI, left open: H/W mode, tied to DGND: I2C VCC125Analog power supply 1, +5 V VCOM26Voltage common decoupling AGND127Analog ground 1 RSV228Reserved, tied to analog ground VOUT8+29ONoNoPositive analog output

22、 from DAC8 VOUT8-30ONoNoNegative analog output from DAC8 VOUT7+31ONoNoPositive analog output from DAC7 VOUT7-32ONoNoNegative analog output from DAC7 VOUT6+33ONoNoPositive analog output from DAC6 VOUT6-34ONoNoNegative analog output from DAC6 VOUT5+35ONoNoPositive analog output from DAC5 VOUT5-36ONoNo

23、Negative analog output from DAC5 VOUT4+37ONoNoPositive analog output from DAC4 VOUT4-38ONoNoNegative analog output from DAC4 VOUT3+39ONoNoPositive analog output from DAC3 VOUT3-40ONoNoNegative analog output from DAC3 VOUT2+41ONoNoPositive analog output from DAC2 VOUT2-42ONoNoNegative analog output f

24、rom DAC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 RSV2 VCC2 AGND2 RSV2 VOUT1? VOUT1+ VOUT2? VOUT2+ VOUT3? VOUT3+ VOUT4? VOUT4+ VOUT5? VOUT5+ VOUT6? VOUT6+ VOUT7? VOUT7+ VOUT8? VOUT8+ RSV2 AGND1 VCOM VCC1 RS

25、V2 RSV1 RSV2 RSV1 RSV2 LRCK BCK DIN1 DIN2 DIN3 DIN4 VDD DGND SCKI RST ZERO1 ZERO2 AMUTEI AMUTEO MD/SDA/DEMP MC/SCL/FMT MS/ADR0/RSV TEST/ADR1/RSV MODE PCM1690 Thermal?Pad PCM1690 SBAS448AOCTOBER 2008REVISED JANUARY DCA PACKAGE HTSSOP-48 (12 mm x 8 mm) (TOP VIEW) TERMINAL FUNCTIONS TERMINAL PULL-5-V N

26、AMEPINI/ODOWNTOLERANTDESCRIPTION RSV21Reserved, tied to analog ground RSV12Reserved, left open RSV23Reserved, tied to analog ground RSV14Reserved, left open RSV25Reserved, tied to analog ground LRCK6IYesNoAudio data word clock input BCK7IYesNoAudio data bit clock input DIN18INoNoAudio data input for

27、 DAC1 and DAC2 DIN29INoNoAudio data input for DAC3 and DAC4 DIN310INoNoAudio data input for DAC5 and DAC6 DIN411INoNoAudio data input for DAC7 and DAC8 6Submit Documentation FeedbackCopyright 20082009, Texas Instruments Incorporated Product Folder Link(s): PCM1690 182 TERMINAL I/O PULL- DOWN 5-V TOL

28、ERANT DESCRIPTION NAMEPIN VOUT1+43ONoNoPositive analog output from DAC1 VOUT1-44ONoNoNegative analog output from DAC1 RSV245Reserved, tied to analog ground AGND246Analog ground 2 VCC247Analog power supply 2, +5 V RSV248Reserved, tied to analog ground (1) Open-drain configuration in out mode. PCM1690

29、 FUNCTIONAL BLOCK DIAGRAM H27U1G8F2BTR-BC (DIGITAL : IC394) DAC VOUT1+ VOUT1? DAC VOUT2+ VOUT2? DAC VOUT3+ VOUT3? DAC VOUT4+ VOUT4? DAC VOUT5+ VOUT5? DAC VOUT6+ VOUT6? AGND2 VDD DGND VCOM VCC1 AGND1 VCC2 DAC VOUT7+ VOUT7? DAC VOUT8+ VOUT8? Digital?Filter and Volume Power?Supply?and Common?Voltage SC

30、KI SCK?Manager RST AMUTEO AMUTEI ZERO2 ZERO1 MODE MD/SDA/DEMP MC/SCL/FMT MS/ADR0/RSV TEST/ADR1/RSV Control?Interface (SPI/I C/HW) 2 LRCK BCK DIN4 DIN3 DIN2 DIN1 Audio?Interface PCM1690 SBAS448AOCTOBER 2008REVISED JANUARY 8Submit Documentation FeedbackCopyright 20082009, Texas Instruments Incorporate

31、d Product Folder Link(s): PCM1690 Rev 1.1 / Sep. 20095 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash VCC VSS WP CLE ALE RE WE CEIO0IO7 R/B NC NC NC NCNC NCNC NC CLE ALEVss Vss Vss Vcc Vcc NC NC NC WP RE CE WERB NC NC NC NC NC NC NC NC NC NC NC NC NC I/O0 I/O1 I/O9 I/O2 I/O3 I/O10 I/O11I/O4 I

32、/O15 I/O12I/O14 I/O13 I/O6 I/O7 I/O5 NC NCNCNC NC PRE I/O8 NC NCNC NCNC A B C D E F G H J K L M 1 2 3 4 5 6 7 8 9 10 ? ? ? Figure 2 : 48-TSOP1 / 63-FBGA Contact, x8 Device IO7 - IO0Data Input / Outputs CLECommand latch enable ALEAddress latch enable CEChip Enable RERead Enable WEWrite Enable WPWrite

33、 Protect R/BReady / Busy VccPower Supply VssGround NCNo Connection Figure 1 : Logic Diagram Table 1 : Signal Names ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 183 H27U1G8F2BTR-BC Pin Function H27U1G8F2BTR-BC Block Diagram Rev 1.

34、1 / Sep. 20096 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash 1.2 PIN DESCRIPTION Table 2 : Pin Description NOTE : 1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must

35、 be sufficient to carry the currents required during program and erase operations. Pin NameDescription IO0 IO7 DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE).

36、 The I/O buffer float to High-Z when the device is deselected or the outputs are disabled. CLE COMMAND LATCH ENABLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write Enable (WE). ALE ADDRESS LATCH ENABLE This input activates the latching of th

37、e IO inputs inside the Address Register on the Rising edge of Write Enable (WE). CE CHIP ENABLE This input controls the selection of the device. WE WRITE ENABLE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge of WE. RE READ ENABLE The RE input

38、is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WP WRITE PROTECT The WP pin, when Low, provides an Hardware protection against undesired modify (program

39、 / erase) operations. R/B READY BUSY The Ready/Busy output is an Open Drain pin that signals the state of the memory. Vcc SUPPLY VOLTAGE The Vcc supplies the power for all the operations (Read, Write, Erase). VssGROUND NCNO CONNECTION Rev 1.1 / Sep. 200915 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit)

40、NAND Flash Figure 4 : Block Diagram ADDRESS REGISTER/ COUNTER PROGRAM ERASE CONTROLLER HV GENERATION COMMAND INTERFACE LOGIC COMMAND REGISTER DATA REGISTER IO RE BUFFERS Y DECODER PAGE BUFFER X D E C O D E R 1024 Mbit + 32 Mbit NAND Flash MEMORY ARRAY WP CE WE CLE ALE A27 A0 184 A3V56S30FTP-G6(DIGIT

41、AL:IC392,393), A3V56S40FTP-G6(DIGITAL:IC422) BA0 BA1 Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS A10(AP) A2 A3 Vdd A0 A1 Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0 BA1 A10(AP) A2 A3 Vdd A0 A1 DQM CKE Vss DQ15 VssQ DQ14 DQ13

42、 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE A12 A11 A8 A7 A6 A5 A4 Vss A9 Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC CLK A12 A11 A8 A7 A6 A5 A4 Vss A9 PIN CONFIGURATION (TOP VIEW) PIN CONFIGURATION (TOP VIEW) x8 x16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

43、 22 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2332 2431 2530 2629 2728 185 A3V56S30FTP-G6 Pin Function A3V56S30FTP A3V56S40FTP 256M Single Data Rate Synchronous DRAM Revision 1.1 Mar., 2010Page 4 / 39 Pin Descriptions SYMBOLTYPEDESCRIPTION CLKInput Clock: CLK is driven by the

44、 system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKEInput Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and

45、 SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank), or CLOCK SUSPEND operation (burst / access in progress). CKE is synchronous except after the device enters self refresh mode, where CKE becomes asynchronous until after exiting the same mode. The input buffers, inc

46、luding CLK, are disabled during self refresh mode, providing low standby power. CKE may be tied HIGH. /CSInput Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when /CS is registered HIGH. /CS provides for external bank selection o

47、n systems with multiple banks. /CS is considered part of the command code. /CAS, /RAS, /WE Input Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered. DQM, DQML, DQMU, Input Input / Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and a

48、n output disable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. DQM corresponds to DQ0DQ7 (A3V56S30FTP). DQML corresponds to DQ0DQ7, DQMU corresponds to DQ8DQ15 (A3V56S40FTP). BA0, BA1Input Bank Address Input(s): BA0 and BA1 define to which bank the AC