HarmanKardon-AVR245-avr-sm 电路图 维修手册.pdf

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1、 harman/kardon AVR245 AVR245 7 X 50W 7.1 CHANNEL A/V RECEIVER SERVICE MANUAL CONTENTS ESD WARNING.2 LEAKAGE TESTING.3 BASIC SPECIFICATIONS.4 PACKAGING.5 FRONT PANEL CONTROLS.6 REAR PANEL CONNECTIONS.8 REMOTE CONTROL FUNCTIONS.11 CONNECTIONS/INSTALLATION.14 OPERATION.25 TROUBLESHOOTING GUIDE.32 REMOT

2、E MM 200V DESCRIPTION The 74LCX32 is a low voltage CMOS QUAD 2-INPUT OR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for inputs. It has same speed

3、 performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LCX32 LOW VOLTAGE CMOS QUAD 2-INPUT OR GATE WITH 5V TOLERANT INPUTS

4、 Figure 1: Pin Connection And IEC Logic Symbols Table 1: Order Codes PACKAGET -5.2; -6;-8; -9; -12;-15; -18; -20; -22;-24V ITHERMAL OVERLOADPROTECTION ISHORTCIRCUIT PROTECTION IOUTPUT TRANSITION SOAPROTECTION DESCRIPTION The L7900 series ofthree-terminal negative regulators is available in TO-220, I

5、SOWATT220 TO-3 and D2PAK packages and several fixed output voltages, making it useful in a wide range of applications.Theseregulators can provide local on-card regulation, eliminating the distribution problems associated with single point regulation; furthermore, having the same voltage option as th

6、e L7800 positive standard series, they are particularly suited for split power supplies. In addition, the -5.2V is also available for ECL system.If adequate heat sinking is provided, theycandeliverover1.5Aoutputcurrent. Although designed primarily as fixed voltage regulators, these devices can be us

7、ed with externalcomponentstoobtainadjustable voltagesand currents. 1 2 TO-3 TO-220ISOWATT220 1 2 3 1 3 D2PAK SCHEMATIC DIAGRAM 1/13 118 AVR245 h ha ar rmmanan/k/karard do on n CONNECTION DIAGRAM AND ORDERING NUMBERS (top view) TO-220 DQ15A1 Low will select the LSB of the Word on the other addresses,

8、 DQ15A1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address In- puts to include this pin when BYTE is Low except when stated explicitly otherwise. Chip Enable (E). The Chip Enable, E, activates

9、 the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of t

10、he memorys Com- mand Interface. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect

11、Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 15. and Figure 15., Reset/ Block Temporary Unprotect AC Waveforms,

12、for more details. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be us

13、ed to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is high-im- pedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until

14、 Ready/Busy be- comes high-impedance. See Table 15., Reset/ Block Temporary Unprotect AC Characteristics and Figure 15., Reset/Block Temporary Unprotect AC Waveforms. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low

15、 will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Se- lect is Low, VIL, the memory is in 8-bit mode, when it i

16、s High, VIH, the memory is in 16-bit mode. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Pro- gram, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from ac-

17、 cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1F capacitor should be connected between the VCC Supply Volta

18、ge pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3. VSS Ground. The VSS Ground is the reference for all voltage measurements. 191 AVR245 h ha ar rmmanan/k

19、/karard do on n 11/42 M29W800DT, M29W800DB BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby and Automatic Standby. See Tables 2 and 3, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Ena

20、ble or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Com- mand Interface. A valid Bus Read operation in- volves setting the desired address on the Address Inputs, applying a Low signal,

21、VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 12., Read Mode AC Waveforms, and Table 12., Read AC Characteristics for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command I

22、nterface. A valid Bus Write operation begins by setting the desired address on the Ad- dress Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Com- mand Interface on th

23、e rising edge of Chip Enable or Write Enable, whichever occurs first. Output En- able must remain High, VIH, during the whole Bus Write operation. See Figures 13 and 14, Write AC Waveforms, and Tables 13 and 14, Write AC Characteristics, for details of the timing require- ments. Output Disable. The

24、Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data In- puts/Outputs pins are placed in the high-imped- ance state. To reduce the Supply Current to the Standby Supply Current, ICC2, C

25、hip Enable should be held within VCC 0.2V. For the Standby current level see Table 11., DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations un- til the operation completes. Automatic Standby. I

26、f CMOS levels (VCC 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is re- duced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

27、Special Bus Operations. Additional bus opera- tions can be performed to read the Electronic Sig- nature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usu- ally used in applications. They require VID to be applied to some

28、 pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 2 and 3, Bus Operations. Block Protection and Blocks Unprotection. Each block can be separately

29、protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on pro- gramming equipment and the other for in-system use. Block Protect and Chip Unprotect operati

30、ons are described in APPENDIX C. Table 2. Bus Operations, BYTE = VIL Note: X = VIL or VIH. OperationEGW Address Inputs DQ15A1, A0-A18 Data Inputs/Outputs DQ14-DQ8DQ7-DQ0 Bus ReadVILVILVIHCell AddressHi-ZData Output Bus WriteVILVIHVILCommand AddressHi-ZData Input Output DisableXVIHVIHXHi-ZHi-Z Standb

31、yVIHXXXHi-ZHi-Z Read Manufacturer Code VILVILVIH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH Hi-Z20h Read Device CodeVILVILVIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH Hi-Z D7h (M29W800DT) 5Bh (M29W800DB) 192 AVR245 h ha ar rmmanan/k/karard do on n M29W800DT, M29W800DB 12/42 Table 3. Bus

32、Operations, BYTE = VIH Note: X = VIL or VIH. COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. Failure to observe a valid sequence of Bus Write operations will result in the memory r

33、eturn- ing to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes de- pending on whether the memory is in 16-bit or 8- bit mode. See either Table 4, or 5, depending on the configuration that is being used, for a summary of the comman

34、ds. Read/Reset Command. The Read/Reset com- mand returns the memory to its Read mode where it behaves like a ROM or EPROM, unless other- wise stated. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset

35、 Command can be issued, be- tween Bus Write cycles before the start of a pro- gram or erase operation, to return the device to read mode. Once the program or erase operation has started the Read/Reset command is no longer accepted. The Read/Reset command will not abort an Erase operation when issued

36、 while in Erase Suspend. Auto Select Command. The Auto Select com- mand is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are re- quired to issue the Auto Select command. Once the Auto Select command is issued the memory re

37、mains in Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/ Reset commands are accepted in Auto Select mode, all other commands are ignored. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other addre

38、ss bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29W800DT is 22D7h and for the M29W800DB

39、is 225Bh. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A18 specifying the address of the block. The other address bits may be set to ei- ther VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs

40、 DQ0- DQ7, otherwise 00h is output. Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command re- quires four Bus Write operations, the final write op- eration latches the address and data in the internal state machine and starts th

41、e Program/Erase Con- troller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ig- nore all commands. It is not possible to issue

42、any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read op- erations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. OperationEGW Address Inputs A0-A18 Data Inp

43、uts/Outputs DQ15A1, DQ14-DQ0 Bus ReadVILVILVIHCell AddressData Output Bus WriteVILVIHVILCommand AddressData Input Output DisableXVIHVIHXHi-Z StandbyVIHXXXHi-Z Read Manufacturer Code VILVILVIH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH 0020h Read Device CodeVILVILVIH A0 = VIH, A1 = VIL, A9 = VID

44、, Others VIL or VIH 22D7h (M29W800DT) 225Bh (M29W800DB) 193 AVR245 h ha ar rmmanan/k/karard do on n 13/42 M29W800DT, M29W800DB After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the

45、Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read mode. Note that the Program command cannot change a bit set at 0 back to 1. One of the Erase Com- mands must be used to set all the bits in a block or in the whole memory from 0 to 1. Unlock Bypa

46、ss Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memo- ry. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these com- mands. Three Bus Write operations are requ

47、ired to issue the Unlock Bypass command. Once the Unlock Bypass command has been is- sued the memory will only accept the Unlock By- pass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. Unlock Bypass Program Command. The Un- lock Bypass Program command

48、 can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Pro- gram/Erase Controller. The Program operation using the Unlock Bypass Program command behave

49、s identically to the Pro- gram operation using the Program command. A protected block cannot be programmed; the oper- ation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock By- pass Mode. See the Program command for details on the behavior. Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset co