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1、Q.,.2 _ zszm : Qsq. 60.61.70.JOt.m.105.16bAPI, (OB. PI OPES : - D(.3.3.4.5,6.7.8 = (3 09.tOJl.fi : . (0EZ HON MfiXK ; /C/P0 /V9i?/W ; , . . P ; PICO FARAD -4- ; EiHcro/?oLYr/c NOfif MARK ; OHM K ; fcito O H M 1 - ,/ . RadioFans.CN 收音机爱 好者资料库 Adjustment of power supply voltage (+85 V +0.5 V) * Before
2、 turning on switch for power supply assembly (A) , Turn VR1 and VR4 fully clockwise and the VR2 and VR3 fully counter clockwise. A). Point of measurement, B) Point of adjustment, C) Specifications, D) Notes, E) Check, F) Check, G) Check, H) Approximately DC 70 V, I) Approximately DC 85 V, J) Adjusti
3、ng both should give a reading within +0.5 V of the voltage 1s absolute value. K) Approximately DC 85 V, L) Adjusting both should give a reading within +0.5 V of the voltage fs absolute value, M) Rear panel, N) Power supply assembly (A) 4. OUTLINE OF CIRCUITS Today, the performance characteristics of
4、 amplifiers have reached a new high because of the rapid develop- ments iff NFB (negative feed back technology) . Because part of the NFB amplifiers 1 s output goes back to the input stage, compensation must be made for the fact that the output and input wave forms are different. Consequently, a sou
5、rce of TIM (Transient intermo- dulational distortion or dynamic distortion) exists. TIM can be eliminated by not using NFB, but many char- acteristics improve with NFB although S/N the indicator lamps are illuminated. For the TONE and TAPE MONITOR circuits, pushing the relevent button will input int
6、o the flip flop terminal (CK) at which time the flip flop will reverse. When the output of the flip flop is H level, the NOT gate output (Q) in the next stage will be L level (NPN transistor is on) , the relays will operate and the indicator lights will be illuminated. A) D30-37 Signals and root ind
7、icators, B) Figure 4-7 Relay control logic circuit * Output muting There is muting capacity (ground type) used for pre- venting transient noises when turning the C-Zl on and off. When the power is switched on (See figure 4-7) Q12 receives load voltage from D40 and D41 and is switched off, CI is char
8、ged and Q9 1 s base voltage is raised. After about 22 seconds, Q8 and Q9 are switched on and the output muting relay RL 8 (at brake) operates, and muting (output circuit ground) is terminated. With the charging of C2 in about 20 seconds, (about 2 seconds before muting is cancelled, Q10, Qll and Q7 a
9、re switched on and the relays in the signal circuit operate and the signal root indicator LED is il- luminated. When power is turned off, Q12 is switched on by the residual power because the reverse bias quickly dis- appears , Q7-Q11 go off and all relays are released (except for RL6 and RL7) and th
10、e muting condition is resumed. * Memory for switch position Because the D latch and flip flop IC 1 s are of the CMOS type, a small amount of current (in micro amps.) is sufficient to preserve their contents. The backup current for these IC 1s is furnished by a 2.5 F condenser (4 x 10 F capacitors) a
11、nd even if the AC current is cut off for 3 days or more, the switch position information is preserved. *Reset/Preset circuit If the back up time is exceeded on the above men- tioned condenser, the button switch positions will resume their starting position when the current is again turned on. In ord
12、er to recharge the backup con- densers (C12-C15) when the power is turned on, the Q5 emitter voltage is temporarily lowered, passing through R42 and D26, the Q6 voltage is reduced and Q6 is temp- orarily switched on. Because of this, the Q6 collector voltage rises, the reset pulse passes through Cll
13、 and is supplied to the D latch and flip flops. Output Q becomes L level and the Tone and TAPE MONITOR are put in off position.The reset pulse is input into the clock terminal of the D latch and also passes Dil of the turner circuit and inputs into the data terminal. As a result, only this circuit 1 s D latch is set at H level and becomes the TUNER function.