Aiwa-XD-DV480-DV487-Service-Manual 电路图 维修手册.pdf

《Aiwa-XD-DV480-DV487-Service-Manual 电路图 维修手册.pdf》由会员分享，可在线阅读，更多相关《Aiwa-XD-DV480-DV487-Service-Manual 电路图 维修手册.pdf（102页珍藏版）》请在收音机爱好者资料库上搜索。

1、SERVICE MANUAL DATA DVD PLAYER XD-DV487 XD-DV480 XD-DV480 XD-DV480 S/M Code No. 09-01A-358-1N3 EZ (B) EZ (B) EZ (NH) K (NH) BASIC DVD/CD MECHANISM: DP-4RM RadioFans.CN 收音机爱 好者资料库 -2- TABLE OF CONTENTS SPECIFICATIONS.3 PROTECTION OF EYES FROM LASER BEAM DURING SERVING .4 ACCESSORIES LIST .5 DISASSEMB

2、LY INSTRUCTIONS .6 7 ELECTRICAL MAIN PARTS LIST .8 21 TRANSISTOR ILLUSTRATION.22 BLOCK DIAGRAM - 1 (OVERALL) .23 BLOCK DIAGRAM - 2 (POWER) .24 BLOCK DIAGRAM - 3 (RF/CD DSP/DVD) .25 BLOCK DIAGRAM - 4 (AUDIO) .26 BLOCK DIAGRAM - 5 (MPEG) .27 BLOCK DIAGRAM - 6 (-COM) .28 WIRE HARNESS DIAGRAM .29 SCHEMA

3、TIC DIAGRAM - 1 (MAIN - 1/4, DRIVE Schmitt Trigger input. (2) Pins 22, 24, 25, 26, 27, 28; Schmitt Trigger input with pull-up resister. (3) Pin 23; Schmitt Trigger input with pull-down resister. IC DESCRIPTION - 4/9 (PCM1716E)-1/1 Pin No.Pin NameI/ODescription -64- I I I I I I I O I/O I/O I/O I/O I/

4、O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I Addresses Addresses Not used Write Enable Reset Not used Addresses Addresses Chip Enable Ground Output Enable Data Inputs/Outputs Data Inputs/Outputs I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode) Ground Selects Byte or Word

5、Mode Addresses A16 A9 A20 NC _ WE _ RESET NC A18, A17 A7 A0 _ CE GND _ OE I/O0 I/O8 I/O1 I/O9 I/O2 I/O10 I/O3 I/O11 VCC I/O4 I/O12 I/O5 I/O13 I/O6 I/O14 I/O7 I/O15/A-1 GND _ BYTE A17 1 8 9 10 11 12 13 15 16, 17 18 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 IC DESCRIPTION

6、 - 5/9 (AT49F8192A-90TC)-1/1 Pin No.Pin NameI/ODescription -65- Bi-directional data to DRAM Bi-directional data to DRAM Bi-directional data to DRAM Bi-directional data to DRAM Bi-directional data to DRAM Bi-directional data to DRAM Bi-directional data to DRAM Bi-directional data to DRAM Bi-direction

7、al data to DRAM Bi-directional data to DRAM Bi-directional data to DRAM Bi-directional data to DRAM Bi-directional data to DRAM Bi-directional data to DRAM Bi-directional data to DRAM Bi-directional data to DRAM Digital ground Address output to DRAM Address output to DRAM Address output to DRAM Addr

8、ess output to DRAM Digital power supply Address output to DRAM Address output to DRAM Address output to DRAM Address output to DRAM Address output to DRAM Master clock from oscillator for 2x decoding Digital GND Master clock from oscillator Digital power supply Row address strobe to DRAM Column addr

9、ess upper byte control strobe to DRAM Column address lower byte control strobe to DRAM Write enable signal to DRAM Output enable signal to DRAM Scan data input Test mode selection (low for normal) Test output Test output Test output Test output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 2

10、2 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 DAT8 DAT9 DAT10 DAT11 DAT12 DAT13 DAT14 DAT15 DAT16 VSS ADD1 ADD2 ADD3 ADD4 VDD ADD5 ADD6 ADD7 ADD8 ADD9 X2_MCK VSS MCK VDD RAS UCAS LCAS WE OE SCAN_IN TEST_SE TEST_OUT12 TEST_OUT11 TEST_OUT10 TEST_OUT9

11、I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O I I O O O O O I I O O O O IC DESCRIPTION - 6/9 (GDC25D801D)-1/5 Pin No.Pin NameI/ODescription -66- 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

12、 83 84 TEST_OUT8 TEST_OUT7 TEST_OUT6 T_SEL TEST_OUT5 TEST_OUT4 TEST_OUT3 TEST_OUT2 TEST_OUT1 TEST_OUT0 TEST_SEL0 TEST_SEL1 TEST_SEL2 TEST_SEL3 TESTSERVO E_SIN E_CLK E_ENB E_DRB VSS SERVO_CLK E_SOUT VDD E_ST0 E_ST1 E_ST2 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 VSS SENS VDD SCLK SDATA XLAT AOU

13、T1 AOUT2 O O O I O O O O O O I I I I I I I I I I O O O O I/O I/O I/O I/O I/O I/O I/O I/O O I I I O O Test output Test output Test output Test mode selection Test output Test output Test output Test output Test output Test output Test mode output selection Test mode output selection Test mode output

14、selection Test mode output selection TEST PIN ( NORMAL STATE = H ) SERVO DSP PGM. DOWNLOADING DATA INPUT SERVO DSP PGM. DOWNLOADING CLK SERVO DSP DOWNLOADING ENABLE SERVO DSP PGM. DOWNLOADING DIRECTION Digital GND SERVO DSP CLOCK INPUT SERVO DSP PGM. DOWNLOADING DATA OUTPUT Digital power supply SERV

15、O DSP DOWNLOADING STATUS 0 SERVO DSP DOWNLOADING STATUS 1 SERVO DSP DOWNLOADING STATUS 2 SERVO DSP GENERAL I/O: FSON(FOCUS OK INVERTING) SERVO DSP GENERAL I/O: PSEL SERVO DSP GENERAL I/O: ADADDR3 SERVO DSP GENERAL I/O: FKRST SERVO DSP GENERAL I/O: FKSET SERVO DSP GENERAL I/O: FEL SERVO DSP GENERAL I

16、/O SERVO DSP GENERAL I/O: DSP_SENSE Digital GND SERVO DSP INTERNAL STATUS MONITOR Digital power supply Serial Command CLOCK Serial Command DATA Serial Command LATCH FDO TDO IC DESCRIPTION - 6/9 (GDC25D801D) - 2/5 Pin No.Pin NameI/ODescription -67- 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101

17、 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 AVDD VCM AGND AOUT3 AOUT4 DGND RFVCM VDD AGND VREFN VREFP INP AGND AIN4 AIN3 AVDD AIN2 AIN1 AIN0 ADCVCM SCK EXT_AD0 EXT_AD1 EXT_AD2 EXT_AD3 EXT_AD4 EXT_AD5 SELEFM EXCK SQCK C16M DOTX VDD SQSO VSS PWM

18、CH1 PWMCH2 PWMCH3 PWMCH4 PWMCH5 PWMCH6 DEFECT_IN_A O O O I I I I I I I I I I O I I I I I I I I I O O O O O O O O O I Analog power supply for ADC TDF Analog GND for ADC FMQ D_VREF Digital GND for ADC TDF Analog GND for ADC TDF TDF TDF TDF Analog GND for ADC TDF TDF Analog power for ADC TDF TDF TDF TD

19、F PLL clock output ADC data input ADC data input ADC data input ADC data input ADC data input ADC data input EFMDATA INPUT SELECTION SUB DATA REQUEST INPUT SUB Q DATA REQUEST 5.6448 MHz(DIGITAL OUT CLOCK) CD DIGITAL DATA OUTPUT Digital power supply SUB Q DATA OUTPUT Digital GND PWM CHANNEL1(x3 CARRI

20、ER) PWM CHANNEL1(x3 CARRIER) PWM CHANNEL1(x3 CARRIER):SLED DRIVE OUTPUT PWM CHANNEL1(x1 CARRIER):PDO_CTR PWM OUTPUT PWM CHANNEL1(x1 CARRIER):RF_GAIN_CTL PWM OUTPUT PWM CHANNEL1(x1 CARRIER):TE_BAL_CTL PWM OUTPUT EXTERNAL DEFECT INPUT PIN IC DESCRIPTION - 6/9 (GDC25D801D) - 3/5 Pin No.Pin NameI/ODescr

21、iption -68- 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 SI_ENC1 SI_ENC2 TZC MIRR MSDATAO FOK VDD DEFECT VSS SLD_FG C_SIG COMP INT1 INT2 VSS INT3 INT4 VDD ADCSB ADCOMP_ VDCDATA0 VDC

22、DATA1 VDCDATA2 VDCDATA3 VDCDATA4 VDCDATA5 VDCDATA6 VDCDATA7 ADADDR0 DVDD ADADDR1 DGND AGND VRT AVDD RF VRM VRB MDS MDP OVER64 I I I I O O O O O O O O O O O I I I I I I I I I O O I I I I O O O SLED ENCODER1 INPUT SLED ENCODER2 INPUT TRACK CROSS PULSE 2 INPUT TRACK CROSS PULSE 1 INPUT SERVO DSP INTENA

23、L STATUS SERIAL OUTPUT INTERNAL GENERATED FOK(Focus OK) H=OK Digital power supply INTERNAL GENERATED DEFECT : H=DEFECT Digital GND SLD_FG=(SL_ENC1) XOR (SL_ENC2) TRACK CROSS PULSE TRACK CROSS MONITOR SERVO DSP INTERRUPT 1 MONITOR(MICOM COMMAND INT) SERVO DSP INTERRUPT 2 MONITOR(FOCUS SERVO INT) Digi

24、tal GND SERVO DSP INTERRUPT 1 MONITOR(TRACK SERVO INT) SERVO DSP INTERRUPT 1 MONITOR Digital power supply PLESSY D/A CHIP SELECTION A/D 7824 A/D CONVERTER A/D CONVERSION END STATUS A/D 7824 A/D CONVERTER DATA BUS0 A/D 7824 A/D CONVERTER DATA BUS1 A/D 7824 A/D CONVERTER DATA BUS2 A/D 7824 A/D CONVERT

25、ER DATA BUS3 A/D 7824 A/D CONVERTER DATA BUS4 A/D 7824 A/D CONVERTER DATA BUS5 A/D 7824 A/D CONVERTER DATA BUS6 A/D 7824 A/D CONVERTER DATA BUS7 A/D 7824 A/D CONVERTER ADDRESS Digital power supply for ADC A/D 7824 A/D CONVERTER ADDRESS Digital GND for ADC Analog GND for ADC TDF Analog power supply f

26、or ADC TDF TDF TDF Spindle motor control signal Spindle motor control signal Spindle motor reversal sensing signal output IC DESCRIPTION - 6/9 (GDC25D801D) - 4/5 Pin No.Pin NameI/ODescription -69- 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193

27、 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 MON LOCK FG_M VSS SCAN_OUT VDD INT RN WN CS A0 A1 A2 A3 A4 A5 VSS PS0 VDD PS1 PS2 PS3 PS4 PS5 PS6 PS7 RESET REQ_DIVX REQ_MPEG MPEG1 MPEG2 MPEG3 MPEG4 MPEG5 MPEG6 MPEG7 MPEG8 SENB SDCLK SERR SYNC O O I O O I I I I I I I I I I/O I/O I/O I/O

28、I/O I/O I/O I/O I I I O O O O O O O O O O O O Spindle motor ON/OFF control signal CLV servo lock signal TDF Digital GND SCAN DATA OUTPUT (Not used) Digital power supply Interrupt request to Host Read strobe from HOST Write strobe from HOST Chip select from HOST Internal register address from HOST In

29、ternal register address from HOST Internal register address from HOST Internal register address from HOST Internal register address from HOST Internal register address from HOST Digital GND Bi-directional data to Host Digital power supply Bi-directional data to Host Bi-directional data to Host Bi-di

30、rectional data to Host Bi-directional data to Host Bi-directional data to Host Bi-directional data to Host Bi-directional data to Host HARDWARE RESET Data request from DIVX module Data request from MPEG MPEG data MPEG data MPEG data MPEG data MPEG data MPEG data MPEG data MPEG data MPEG data valid s

31、ignal (low for valid) MPEG data transfer clock MPEG data error detection signal (low indicates error occurred) SERVO DSP INTERRUPT 1 MONITOR(MICOM COMMAND INT) IC DESCRIPTION - 6/9 (GDC25D801D) - 5/5 Pin No.Pin NameI/ODescription -70- IC DESCRIPTION - 7/9 (HD6417034AF112) - 1/4 1 2 3 4 11 12 13, 14

32、15 16 21 22 23 24 30 31 32 39 40 41, 42 43 44 47 48 49 50 51 52 53 54 55 _ IRQ6 TP14 PB14 _ IRQ7 TP15 PB15 VSS AD0 AD7 VSS AD8, AD9 VCC AD10 AD15 VSS A0 _ HBS A1 A7 VSS A8 A15 VSS A16, A17 VCC A18 A21 _ CS0 _ CASH _ CS1 _ CS2 _ CASL _ CS3 VSS TIOCA0 PA0 _ CS4 _ RAS PA1 _ CS5 TIOCB0 PA2 _ CS6 I O I/O

33、 I O I/O I/O I/O I/O O O O O O O O O O I/O O I/O O I/O O Interrupt request 6. Timing pattern output 14. Timing pattern output pins. Port B: 16-bit input/output pins. Input or output can be selected individually for each bit. Interrupt request 7. Timing pattern output 15. Timing pattern output pins.

34、Port B: 16-bit input/output pins. Input or output can be selected individually for each bit. Ground Data bus Ground Data bus Power. Data bus Ground Address bus Upper/lower byte strobe: Upper and lower byte strobe signals. (Also used as WRH and A0.) Address bus Ground Address bus Ground Address bus P

35、ower. Address bus Chip select 0. Chip select signals for accessing external memory and devices. Column address strobe high. DRAM column address strobe timing signal. Output to access the upper eight data bits. Chip select 1. Chip select signals for accessing external memory and devices. Chip select

36、2. Chip select signals for accessing external memory and devices. Column address strobe low. DRAM column address strobe timing. Output to access the lower eight data bits. Chip select 3. Chip select signals for accessing external memory and devices. Ground ITU input capture/output compare (channel 0

37、). Input capture or output compare pins. Port A. 16-bit input/output pins. Input or output can be selected individually for each bit. Chip select 4. Chip select signals for accessing external memory and devices. Row address strobe. DRAM row-address strobe timing signal. Port A. 16-bit input/output p

38、ins. Input or output can be selected individually for each bit. Chip select 5. Chip select signals for accessing external memory and devices. ITU input capture/output compare (channel 0). Input capture or output compare pins. Port A. 16-bit input/output pins. Input or output can be selected individu

39、ally for each bit. Chip select 6. Chip select signals for accessing external memory and devices. Pin No.Pin NameI/ODescription -71- IC DESCRIPTION - 7/9 (HD6417034AF112) - 2/4 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 _ WAIT _ CS7 PA3 _ WRL _ WR PA4 _ WRH _ LBS PA5 _ RD PA6 _ BACK PA7 VSS _ BREQ

40、PA8 _ IRQOUT _ AH _ ADTRG PA9 DPL TIOCA1 PA10 DPH TIOCB1 PA11 _ IRQ0 TCLKA DACK0 PA12 _ IRQ1 TCLKB DREQ0 PA13 _ IRQ2 DACK1 PA14 _ IRQ3 DREQ1 PA15 VCC I O I/O O I/O O I/O O I/O O I/O I I/O O I I/O I/O I/O I O I/O I I/O I O I/O I I/O Wait. Requests the insertion of wait states (TW) into the bus cycle

41、when the external address space is accessed. Chip select 7. Chip select signals for accessing external memory and devices. Port A. 16-bit input/output pins. Input or output can be selected individually for each bit. Lower write. Indicates write access to the lower eight bits of an external device. _

42、 Write. Brought low during write access. (Also used as WRL.) Port A. 16-bit input/output pins. Input or output can be selected individually for each bit. Upper write. Indicates write access to the upper eight bits of an external device. Upper/lower byte strobe. Upper and lower byte strobe signals. (

43、Also used as WRH and A0.) Port A. 16-bit input/output pins. Input or output can be selected individually for each bit. Read. Indicates reading of data from an external device. Port A. 16-bit input/output pins. Input or output can be selected individually for each bit. Bus request acknowledge. Port A. 16-bit input/output pins. Inp