Philips-DVDR-3465-H-Service-Manual 电路图 维修手册.pdf

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1、Published by KC-TE 0739 V however, the SYSCLK output remains active. If the LPS input remains low for more than 26 s (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the disabled

2、state upon hardware reset. The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1, and is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0. 48CMOSILLC request input. The LLC uses this input to initiate

3、 a service request to the TSB41AB1. Bus holder is built into this terminal. 16 17 18 CMOSIPower class programming inputs. On hardware reset, these inputs set the default value of the power class indicated during self-ID. Programming is done by tying these terminals high or low. Refer to Table 9 for

4、encoding. NAME DGND DVDD FILTER0 FILTER1 ISO LPS LREQ PC0 PC1 PC2 PD12CMOSIPower-down input. A high on this terminal turns off all internal circuitry except the cable-active monitor circuits, which control the CNA output (64-terminal PAP package only). Asserting the PD input high also activates an i

5、nternal pulldown on the RESET terminal to force a reset of the internal control logic. (PD is provided for legacy compatibility and is not recommended for power management in place of IEEE 1394a-2000 suspend/resume LPS and C/LKON features.) EN 513139 785 331208.IC description TERMINAL TYPEI/ODESCRIP

6、TION NAMEPHP NO. TYPEI/ODESCRIPTION 41SupplyPLL circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. 40SupplyPLL circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paral

7、leled 0.1 F and 0.001 F. Lower frequency 10 F filtering capacitors are also recommended. This supply terminal is separated from DVDD and AVDD inside the device to provide noise isolation. It should be tied at a low-impedance point on the circuit board. 33 34 BiasCurrent setting resistor terminals. T

8、hese terminals are connected through an external resistor to set the internal operating currents and cable driver output currents. A resistance of 6.34 k 1.0% is required to meet the IEEE Std 1394-1995 output voltage limits. 37CMOSILogic reset input. Asserting this terminal low resets the internal l

9、ogic. An internal pullup resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the Application Information section). The RESET terminal also incorporates an internal pulldown which is activated when the PD input is asserted h

10、igh. This input is otherwise a standard logic input, and may also be driven by an open-drain type driver. 23CMOSITest control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal may be tied to GND through a 1-k pulldown resistor or it may be tied to GND dire

11、ctly. 24CMOSITest control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal should be tied to GND. 1CMOSOSystem clock output. Provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC. 22CMOSITest control input. This input is used in

12、 manufacturing test of the TSB41AB1. For normal use this terminal should be tied to VDD. 30CableI/OTwisted-pair cable A differential signal terminals. Board traces from the pair of positive and negative differential signal terminals should be kept matched and as 29CableI/O positive and negative diff

13、erential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. 28CableI/OTwisted-pair cable B differential signal terminals. Board traces from the pair of positive and negative differential signal terminals should be kept matched

14、and as 27CableI/O positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. 31CableI/OTwisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for proper operation of the twiste

15、d-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection. PLLGND PLLVDD R0 R1 RESET SE SM SYSCLK TESTM TPA+ TPA TPB+ TPB TPBIAS XI XO 42 43 CrystalCrystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant fundamenta

16、l mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see crystal selection in the Application Information section). When an external clock source is used, XI should be the input and XO should be left open, and the clock must be

17、 supplied before the device is powered on. EN 523139 785 331208.IC Description IC7401 - 4x10bit DigitalVideo Decoder with microvision BLOCK DIAGRAM Composite and S-Video Processor Y/C Separation 5-line Adaptive Comb Luma Processing Chroma Processing ADC1 ADC2 ADC3 ADC4 M U X Component Processor CVBS

18、/Y C Y/G Pb/B Pr/R Gain/Offset Color Space Conversion C Y Output Formatter Y9:0 YCbCr VBI Data Slicer Copy Protection Detector C9:0 Host Interface Timing Processor with Sync Detector VI_1_A VI_1_B VI_1_C VI_2_A VI_2_B VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A CVBS/ Y/G CVBS/ Pb/B/C CVBS/ Pr/R/C CVBS/Y CVBS

19、/Y/G Analog Front End Sampling Clock GPIO FSS HS/CS VS/VBLK FID AVID XTAL1 XTAL2 DATACLK RESETB GLCO DR DG DB FSO PWDN SCL SDA YCbCr Figure 8-14 PIN CONFIGURATION 22 23 C_6/GPIO/RED C_7/GPIO/GREEN C_8/GPIO/BLUE C_9/GPIO/FSO DGND DVDD Y_0 Y_1 Y_2 Y_3 Y_4 IOGND IOVDD Y_5 Y_6 Y_7 Y_8 Y_9 DGND DVDD 60 5

20、9 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VI_1_B VI_1_C CH1_A33GND CH1_A33VDD CH2_A33VDD CH2_A33GND VI_2_A VI_2_B VI_2_C CH2_A18GND CH2_A18VDD A18VDD_REF A18GND_REF CH3_A18VDD CH3_A18GND VI_3_A VI_3_B VI_3_C CH3_A33GND CH3_A33VDD 25

21、 26 27 28 PFP PACKAGE (TOP VIEW) 7978777675807472 71 7073 2930 31 32 33 69 68 21 67 66 65 64 34 35 36 3738 39 40 63 62 61 VI_1_A CH1_A18GND CH1_A18VDD PLL_A18GND PLL_A18VDD XTAL2 XTAL1 VS/VBLK/GPIO HS/CS/GPIO FID/GPIO C_0/GPIO C_1/GPIO DGND DVDD C_2/GPIO C_3/GPIO C_4/GPIO C_5/GPIO IOGND IOVDD CH4_A3

22、3VDD CH4_A33GND VI_4_A CH4_A18GND CH4_A18VDD AGND DGND SCL SDA INTREQ DVDD DGND PWDN RESETB FSS/GPIO AVID/GPIO GLCO/I2CA IOVDD IOGND DATACLK Figure 8-15 EN 533139 785 331208.IC description PIN DESCRIPTION TERMINAL I/ODESCRIPTION NAMENUMBER I/ODESCRIPTION Analog Video VI_1_A VI_1_B VI_1_C VI_2_A VI_2

23、_B VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A 80 1 2 7 8 9 16 17 18 23 I VI_1_x: Analog video input for CVBS/Pb/B/C VI_2_x: Analog video input for CVBS/Y/G VI_3_x: Analog video input for CVBS/Pr/R/C VI_4_A: Analog video input for CVBS/Y Up to 10 composite, 4 S-video, and 2 composite or 3 component video inp

24、uts (or a combination thereof) can be supported. The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 F. The possible input configurations are listed in the input select register at I2C subaddress 00h (see Section 2.11.1). Clock Signals DATACLK40OLine-locked data output clock. XT

25、AL174I External clock reference input. It may be connected to an external oscillator with a 1.8-V compatible clock signal or a 14.31818-MHz crystal oscillator. XTAL275OExternal clock reference output. Not connected if XTAL1 is driven by an external single-ended oscillator. Digital Video C9:0/ GPIO9:

26、0 57, 58, 59, 60, 63, 64, 65, 66, 69, 70 O Digital video output of CbCr, C9 is MSB and C0 is LSB. Unused outputs can be left unconnected. Also, these terminals can be programmable general-purpose I/O. For the 8-bit mode, the two LSBs are ignored. D_BLUE58IDigital BLUE input from overlay device D_GRE

27、EN59IDigital GREEN input from overlay device D_RED60IDigital RED input from overlay device FSO57IFast-switch overlay between digital RGB and any video Y9:0 43, 44, 45, 46, 47, 50, 51, 52, 53, 54 O Digital video output of Y/YCbCr, Y9 is MSB and Y0 is LSB. For the 8-bit mode, the two LSBs are ignored.

28、 Unused outputs can be left unconnected. Miscellaneous Signals FSS/GPIO35I/O Fast-switch (blanking) input. Switching signal between the synchronous component video (YPbPr/RGB) and the composite video input. Programmable general-purpose I/O GLCO/I2CA37I/O Genlock control output (GLCO). Two Genlock da

29、ta formats are available: TI format and real time control (RTC) format. During reset, this terminal is an input used to program the I2C address LSB. INTREQ30OInterrupt request PWDN33I Power down input: 1 = Power down 0 = Normal mode RESETB34IReset input, active low EN 543139 785 331208.IC Descriptio

30、n TERMINAL I/ODESCRIPTION NAMENUMBER I/ODESCRIPTION Host Interface SCL28II2C clock input SDA29I/OI2C data bus Power Supplies AGND26IAnalog ground. Connect to analog ground. A18GND_REF13IAnalog 1.8-V return A18VDD_REF12IAnalog power for reference 1.8 V CH1_A18GND CH2_A18GND CH3_A18GND CH4_A18GND 79 1

31、0 15 24 IAnalog 1.8-V return CH1_A18VDD CH2_A18VDD CH3_A18VDD CH4_A18VDD 78 11 14 25 IAnalog power. Connect to 1.8 V. CH1_A33GND CH2_A33GND CH3_A33GND CH4_A33GND 3 6 19 22 IAnalog 3.3-V return CH1_A33VDD CH2_A33VDD CH3_A33VDD CH4_A33VDD 4 5 20 21 IAnalog power. Connect to 3.3 V. DGND 27 32 42 56 68

32、IDigital return DVDD 31 41 55 67 IDigital power. Connect to 1.8 V. IOGND39 49 62IDigital power return IOVDD38 48 61IDigital power. Connect to 3.3 V or less for reduced noise. LL_A18GND77IAnalog power return LL_A18VDD76IAnalog power. Connect to 1.8 V. Sync Signals HS/CS/GPIO72I/O Horizontal sync outp

33、ut or digital composite sync output Programmable general-purpose I/O VS/VBLK/GPIO73I/O Vertical sync output (for modes with dedicated VSYNC) or VBLK output Programmable general-purpose I/O FID/GPIO71I/O Odd/even field indicator output. This terminal needs a pulldown resistor. Programmable general-pu

34、rpose I/O AVID/GPIO36I/O Active video indicator output Programmable general-purpose I/O EN 553139 785 331208.IC description IC7595 - Voltage Detector Series with Programmable Delay BLOCK DIAGRAM NCP303LSNxxT1 Open Drain Output Configuration Vref 2Input 3Gnd5CD RD 1Reset Output Figure 8-18 PIN DESCRI

35、PTION AND CONFIGURATION PIN CONNECTIONS AND MARKING DIAGRAM 1 3N.C. Reset Output 2 Input Ground 4 CD5 xxxYW (Top View) xxx = 302 or 303 Y= Year W= Work Week Figure 8-19 EN 563139 785 33120 Exploded View Figure 9-1 190 1001 266(8x) 189 269 272 271(2x) 185 191 249 179 180 130 191 191 191 269 269 269 1

36、10 127 121 122 1003 131 255 161 1005 259(4x) 182 254(2x) 252(2x) 253 240 264(3x) 263(4x) 256(3x) 1004 184 260 265 273(2x) 230 187 1002 258(3x) 257(4x) 1006 183 186 251(8x) 1003 125 124 126 123 250 181 101 129 128 ENVIRONMENTAL REQUIREMENT: NO BANNED SUBSTANCES ACC. TO UAT-0480/100 P002 P001 270 (for

37、 DVDR3455H/DVDR3465H) 274 (for DVDR3450H/DVDR3460H/DVDR3452H) Exploded View 3139 249 36541_110-1_a1.eps 2007-09-27 9.Exploded View & Spare Parts List EN 573139 785 331209.Exploded View & Spare Parts List DVDR3465H/96 0110 313924414511 COVER TRAY DVDR3465H 0131 313924125081 CLIP ESD DVDR3380 0179 313

38、924125041 SPRING EMC 0180 313924124361 SPRING AV DVDR3400 0184 313911426671 BUSH, AC CORD 0186 313911435693 SPACER 5MM 0189 282203100051 FAN 12VDC 0.6W 3000RPM B 0191 313924409101 HDD DAMPER 0230 313924124081 PLATE REAR DVDR3455H/96 0240 313924124232 COVER TOP 0269 252220000027 SCR WAFER PH STZN BU

39、6/32X12 0341 242254900971 REMOTE CONTR DVDR3455H/NAFTA B 0345 242207000093 MAINSCORD TWN 7A 1M8 VH BK B 0350 242207600718 AV CABLE 1M5 0488 242207600873 RF CABLE 1M5 1001 313924851312 PCBAS DVDR3455H DIGI BOARD/96 1002 313924888701 PCBAS DVDR3455H ANA BOARD NA 1003 313924889112 FRONT COMBI PCBA 1004

40、 313924712864 PSU 06H85 WR AC7012X LF PIE 1005 313924800561 DRIVE D6.8 CLOSED 1006 282206200152 HDD 3.5” 250GB ST3250820ACE B 8002 313911028301 CBLE PH 12P/220/12P PH 26ST BK 8003 313924102541 FFC FOIL 18P/180/18P AD 1MMP 8004 313924102551 FFC FOIL 19P/180/19P AD 1MMP 8005 313924102531 FFC FOIL 24P/

41、140/24P AD 1MMP 8006 313924102061 CBLE HR 04P/120/04P LC UL 8007 313924102361 CBLE EH 04P/220/04P F6001 UL 8008 313924102181 FFC FOIL 14P/280/14P BD 1MMP 8009 313924102162 CBLE IDE 40P/220/40P IDE UL SP 8010 313924100921 CBLE IDE 40P/280/40P IDE UL 8011 313924101521 FFC FOIL 09P/280/09P BD 1MMP 8012 313911027881 CBLE PH 06P/180/06P PH 26ST BK 8013 313924102241 CBLE VH 05P/180/05P VH 22ST BK 8015 313924101751 CBLE SRA 1P/100/1P SRA 18ST BK P001 314107939701 FRONT CAB. ASSY DVDR3455H APAC P002 314107936761 FRAME ASSY