Kenwood-KDVS-240-P-Service-Manual电路原理图.pdf

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1、 2004-5 PRINTED IN JAPANB53-0171-00 (N)2703DVD PLAYERKDV-S210P/S220P/S230P/S240PSERVICE MANUALSize AAA battery(Not supplied)Remote controller assy(A70-2066-08)Panel assy(A64-3526-08): KDV-S210P(A64-3528-08): KDV-S220P(A64-3529-08): KDV-S230P(A64-3530-08): KDV-S240PTapping screw(N09-6274-08) x4Magic

2、tape(H30-0514-05) x2Remote control sensor assy (6m)(T95-0264-08)Mounting hardware(J22-0237-08) x2Metallic cabinet(A01-2845-08)Cord with DC plug (2.4m)(E03-0405-08)Cord with pinplug (3m)(E30-6389-08)SEMS(N09-6273-08) x4RC-DV500Except KDV-S210P2KDV-S210P/S220P/S230P/S240PBLOCK DIAGRAMPROCESSOR-DIGITAL

3、 SERVO CONTROLDVD/CD DATA DECODINGSU6SU1SU3MOTOR DRIVERPWMSU2BTLMOTOR DRIVERHEAD AMPLIFIER-GENERATING SERVO-AUTO GAIN CONTROLLINGS+7VMMVCMVCCDECODING & CORRECTING-F/E CONTROL uP-DATA BUFFERINGSVCC-F/E PROGRAMINGFLASH MEMORY3.3VRFVCC3.3VVCC27RFVCC-DATA BUFFERINGDVD MPEG DECODING PROCESSOR-MPEG DECODI

4、NG-B/E & SYSTEM CONTROL uPU1SU7-B/E FRAMESDRAM-DVD/CD DATA U34CIRCUITLASER DRIVESQ4,5U3-F/E FRAME BUFFERSDRAM 1Mx16BITS-WORKING MEMORYACTUATOR &BRUSHLESSSY1-F/E SYSTEM CLOCK33.8688MHzCERAMIC RESONATORCODE STORED128kx8-B/E SYSTEM CLOCKCRYSTAL RESONATOR27MHzY1VCC27-INCLUDING OVER2ch AUDIO DACU35DIGITA

5、L FILTERSAMPLINGU9-RESETINGRESET ICfor U1STORED-SETUP & RESUMEEEPROMINFORMATIONU2U28CODE STORED-B/E PROGRAMINGFLASH ROMVCC33Q1MMVCMVCCSVCC3.3VRFVCCVCC33 AVCCAVCCRESET VCCVCCAS+7VU5REGULATOR3.3V FIXEDSQ3+7VS7VVCCVCC+7VU23-1U23-2BUFFERU27POST LPF-2nd ORDERACTIVE LPFx23.3VCB5 CBP5CBP7CB7CB502 CBP502CB3

6、CBD31MBITx8BUFFER4Mx16BITSSERVO SIGNALRF AMPLITUDEERROR SIGNALSINSERTIONDISCSLITINDICATOREJECT SWUD3NAND GATESPOWER SWINDICATORPOWERCBD1 CBP1VCCS7VUP1REGULATORSWITCHINGREGULATORSWITCHINGUP2+B1REGULATOR5VQP30REGULATORQP4028VCIRCUITBU VCC-GENERATINGTIMINGON/OFF SWDELAY CIRCUITVCCRESETREDUCING +B1CIRCU

7、ITMUTE-SENDINGDRIVING-MUTE TR+B1ACTIVE LPFx2LPF-2nd ORDERUP3-2UP3-1S7VMUTE TRQP4,5UP4VCC75 OhmVIDEODRIVERTRP1PULSE TRANSBU VCCEYE INPUTREMOTEDC INPUTANALOGOUTAUDIOVIDEOOUTCOMPOSITEDIGITALOUTAUDIOREMOTEEYESPINDLEMOTORtoSLEDGEMOTORtoPICKUP HEADfrom SENSOR ofACTUATOR COIL ofPICKUP HEADtoto CD LDto DVD

8、LD+BERROR SIGNALINPUTRF & SERVOI/OVPAVMPVCCVCCINTERFACECOMMANDDSPCDLD DVDLDDSP COMMANDINTERFACE SIGNAL INPUTRF & SERVOCONTROLLOADINGMECHANISMOUTPUTSERVO DRIVE SIGNALINTERFACEFLUSH MEMORYINTERFACESDRAMAVDD5INTERFACEATAPIVDD 3.3INTERFACESDRAMINTERFACEATAPIFLUSH MEMORYEEPROMRESETDIGITAL AUDIOVC25INTERF

9、ACEINTERFACEINTERFACESPDIF OUTSPDIFUDACVIDEO DAC OUTVC33VCCOUTPUTSIGNALERRORRF & SERVORESETHARDWAREfor F/EINCLUDINGAUX4AUX2AUX7VCCVDDVOUTRVAAVOUTLVDDZRRVCCVCCVCCLEDREDP DWNP ON+B DWNLEDGREENIRVSWENVINVSWENVINP ONZERO MUTEVCCV+ V+CH-RCH-LVCC+B DWNP ONIRZERO MUTESLOT-INLOADING MECHANISMDISPLAY PCB POW

10、ER & OUTPUT PCBCOMBO PCBTRAVERSE MECHANISM3KDV-S210P/S220P/S230P/S240PCOMPONENTS DESCRIPTION COMBO PCBRef. No. Application / Function Operation / Condition / CompatibilityMPEG decoding control DVD MPEG images are decoded.Dolby digital decoding control Outputs of Dolby digital audio are decoded.LPCM

11、audio decoding control LPCM audio of CD and DVD are decoded.DVD navigation control DVD navigation is controlled.ATAPI communication control ATAPI communication is control in order to control F/E.U1Built-in microcomputer for controllingSystem as a whole and B/E are controlled. 32bit RISC microcompute

12、r is built-in.system and B/E systemBuilt-in video DAC Video DAC is built-in to output current for composite video output from No. 106 pin.Digital audio DAC control outputAudio signals are output from No. 32 (TWS), 33 (TSD0), 39 (MCLK), and 40 (TBCK) pins. Also,DAC system control is conducted using N

13、o. 160 (AUX0), 161 (AUX1), and 168 (AUX6) pins.Controls for keys and remote controlNo. 162 pin is input for EJECT key. When receiving input, it is in L. No. 166 pin is forremote control input. When receiving input, there will be pulse input.U2EEPROM for storing system settingEEPROM for storing syste

14、m setting information and resume information.information and resume informationU3Frame buffer memory Decoding data buffer memory.Program memory Memory for program control.U5 3.3V regulator From No. 3 pin, VCC (5V) is input and from No. 2 pin, VCC33 (3.3V) is output.U9 System reset control Rising/Fal

15、ling of VCC (5V) is detected by No. 5 pin, and L-reset output is made from No. 4 pin.U23 For audio post LPF CH1-side is Rch and CH2-side Lch. Constitutes a multiple feedback-type active LPF.U27 SPDIF output, Pulse transformer driverInverters are connected in 3-step parallel connection for increased

16、current capacity andoutput to the pulse transformer.U28 B/E program memory Flash memory for storing B/E program memory.U34 Program memory Flash memory for storing programs.Digital audio signal is input from No. 3 (TWS), 2 (TSD0), 16 (MCLK), and 1 (TBCK) pins.U35 Digital audio 2ch DAC Also, signals f

17、or DAC system control are input from No. 15 (AUX0), 14 (AUX1), and 13 (AUX6) pins.Output for Lch analog audio is made from No. 7 pin and that for Rch is made from No. 8 pin.DVD/CD digital servo control Built-in DVD/CD digital servo equalizer and various timing generation circuit.DVD/CD data decoding

18、 controlData generation from RF of DVD/CD, error correction and control over scramble analysisSU1and release.F/E section built-in system controlF/E section 8bit microcomputer for system control.microcomputerATAPI communication control ATAPI communication control with B/E.Pickup actuator driverContro

19、l signals for focus and tracking actuator signals of the pickup are received by No. 1 andNo. 26 pins respectively and currents are output from No. 13 and14 and No. 15 and 16 pins.SU2 Feed motor driverControl signals for the feed motor is received at No.6 pin and currents are output fromNo. 11 and 12

20、 pins.Motor driver for slot loading mechanismControl signals for slot loading mechanism motor is received at No. 23 pin and currentsare output from No. 18 and 17 pins.4KDV-S210P/S220P/S230P/S240PRef. No. Application / Function Operation / Condition / CompatibilitySpindle motor driverTiming is contro

21、lled by No. 18 pin control signal for the 3-phase brushless spindle motor, usingSU3 No. 16 pins Hall element input signals, while current outputs are made from No 20, 22 and 24 pins.Spindle motor rotation detection Rotation FG output for controlling spindle motor is output from No. 27 pin.DVD/CD ser

22、vo error signal replayGeneration of various servo signals from pick up signals.SU6 amplifier controlBuilt-in DVD/CD laser APC circuit Built-in LD current control circuit for DVD/CD.SU7Frame buffer memory Memory for temporarily caching read data of DVD/CD.System memory External microcomputer memory f

23、or F/E system control.CH1-side CH1-sideServo reference voltage generation Signal after dividing VC25 (2.5V) into 2.1V enters the positive phase and output from theSU8amplifier output terminal as buffer output.CH2-side CH2-sideRFRP (mirror detection signal) RF bottom hold signal and its DC are input

24、to reverse input and positive input respectivelygeneration amplifier for canceling DC fluctuation. These then can be used as mirror signals.SQ3 3.3V regulator VCC (5V) is input from No. 3 pin and 3.3V is output from No. 2 pin.SQ4 Driver for LD-driving for CDCDs LD current control signals output from

25、 SU6 are received at base and the currentamount for LD driving is controlled.SQ5 Driver for LD-driving for DVDDVDs LD current control signals output from SU6 are received at base and the currentamount for LD driving is controlled. THERMISTER PCBRef. No. Application / Function Operation / Condition /

26、 CompatibilityUT1 InverterOutput from UT2 comparator is inverted. Input is made on No. 2 pin and output on No. 4pin. Active L.UT2 ComparatorSignal from thermister is inverse input and reference voltage is input to positive-phaseinput. Output from thermister is comparated and output from No. 4 pin. A

27、ctive H.QT1 Switching TRUT1 output is received on the base and output is inverted when it is made. The output isfeedback into the positive-phase input at UT2 for containing the fluctuations in outputs.THT1Temperature detection thermister forResistance value is low at low temperature and high at high

28、 temperature.thermal shutdown DISPLAY PCBRef. No. Application / Function Operation / Condition / CompatibilityUD3Power supply ON/OFF delay circuit With +B_DWN of reduced voltage detection circuit and OR of /P_ON signal, /P_DWNNOR gate IC signal is generated. POWER & OUTPUT PCBRef. No. Application /

29、Function Operation / Condition / CompatibilityUP1VCC (+5V) generation switching Power supply is input from No. 2 pin and switching output is made from No. 3 pin.regulator IC Going via choke coil, it becomes VCC (+5V) power supply output.COMPONENTS DESCRIPTION5KDV-S210P/S220P/S230P/S240PCOMPONENTS DE

30、SCRIPTIONRef. No. Application / Function Operation / Condition / CompatibilityUP2 S7V generation switching regulator ICPower supply is input from No. 2 pin and switching output is made from No. 3 pin.Going via choke coil, it becomes S7V power supply output.UP3 Analog audio output LPF amplifier CH1-s

31、ide is Rch and CH2-side is Lch. Constitutes non-inverse active LPF composition.UP4Composite video output 75 driverInput is made on No. 3 pin and output is made from No 6 pin.amplifier ICQP1 Mute circuit driving TRWhen QP2 is ON, input is made to the emitter. Mute circuit driving power supply is outp

32、utfrom the collector.QP2 Mute circuit switching TR When this TR comes ON, muting is ON and when it comes OFF, muting is OFF.QP3 Mute circuit switching TRThis is a TR for switching QP2. Therefore, the logic is inverted and when the TR comesON, muting is OFF, and when the TR comes OFF, the muting is O

33、N.QP4 Rch mute TR When base is H, Rch is muted.QP5 Lch mute TR When base is H, Lch is muted.QP8 Composite video output buffer driver TR When the input signal comes in on the base, output is made from the emitter.QP9 Power supply ON/OFF delay circuit SW TRWhen this TR is ON, base current of QP21 is s

34、hut off. QP21 is OFF and switching powersupply is ON.QP10 Mute circuit switching TRWhen Z_MUTE signal in the base of this TR is active, (H on no signal), QP1 is turned ONand the mute circuit is driven.QP11 Mute circuit switching TR/P_ON in the base becomes L when the power switch comes ON. Therefore

35、, it is H whenthe power is OFF. When this happens, QP3 is forced to go OFF and muting is driven.QP12 Power supply ON/OFF delay circuit SW TROn the base of this TR, power switch triggered /P_ON signal comes in. When this is L, and QP22is turned ON, base current of QP20 is shut off. When QP20 is OFF,

36、switching power supply is ON.QP15Reduced voltage detection switchingAt the time of reduced +B1, base current is shut off and the circuit goes OFF.TR for resume operationQP20 Power supply ON/OFF delay circuit SW TR When this TR is ON, switching power supply is OFF.QP21 Power supply ON/OFF delay circu

37、it SW TR When this TR is ON, switching power supply is OFF.QP22 Power supply ON/OFF delay circuit SW TRWhen this TR is ON, base current at QP20 is shut off. This means QP20 is OFF andswitching power supply is ON.QP30 BU_VCC (+5V) regulator driving TRReceives batter power supply (+B1) by the collecto

38、r and outputs regulation voltage 28V(+B1) from the emitter.QP40 28V regulator drive TRReceives battery current (+B) with collector and outputs regulated voltage 28V (+B1) from theemitter. This is used to counter the surge current, and it is normally about +B - +B1 = 1.4V.QP41 TR for comprising Darli

39、ngton connection Along with QP40, constitutes Darlington connection and works to enhance compound hfe.6KDV-S210P/S220P/S230P/S240PMICROCOMPUTERS TERMINAL DESCRIPTION B/E Microcomputer : ES6008 (COMBO PCB : U1)Pin No. Pin Name I/O Application Processing Operation Description1 VEE - I/O power supply (

40、+3.3V) input27 LA4LA9 O Flash ROM address bus8 VSS - Digital GND9 VCC - Core power supply (+2.5V) input1016 LA10LA16 O Flash ROM address bus17 VSS - Digital GND18 VEE - I/O power supply (+3.3V) input1921 LA17LA19 O Flash ROM address bus22,23 LA20,LA21 O Flash ROM address bus NC24 /RESET I Chip reset

41、 input25 TDMDX O NC25 RSEL I ROM selection terminal Selected by 8bit ROM26 VSS - Digital GND27 VEE - I/O power supply (+3.3V) input28 TDMDR I NC29 TDMCLK I NC30 TDMSF I NC31 TDMTSC# O NC32 TWS O Audio frame synchronization output32 SEL_PLL2 I System and DSCK output clock selection 2 Selected by DCLK

42、 x 433 TSD0 O Audio serial data port 033 SEL_PLL0 I System and DSCK output clock selection 0 Selected by DCLK x 434 VSS - Digital GND35 VCC - Core power supply (+2.5V) input36 TSD1 O Audio serial data port 1 NC36 SEL_PLL1 I System and DSCK output clock selection 1 Selected by DCLK x 437,38 TSD2,TSD3

43、 O Audio serial data port 2,3 NC39 MCLK O Audio master clock40 TBCK O Audio bit clock output41 SPDIF O SPDIF output41 SEL_PLL3 I Clock source selection Selected by crystal oscillator42 NC - NC43 VSS - Digital GND44 VCC - Core power supply (+2.5V) input45 RSD I Audio input serial data NC46 RWS I Audi

44、o input frame synch NC47 RBCK I Audio input bit clock NC48 NC - NC49 XIN I Crystal input7KDV-S210P/S220P/S230P/S240PPin No. Pin Name I/O Application Processing Operation Description50 XOUT O Crystal output51 AVEE - PLL analog power source (+3.3V) input52 VSS - Digital GND5358 DMA0DMA5 O DRAM address

45、 bus 0559 VEE - I/O power supply (+3.3V) input60 VSS - Digital GND6166 DMA6DMA11 O DRAM address bus 61167 VSS - Digital GND68 VEE - I/O power supply (+3.3V) input69 /DCAS O DRAM Column address strobe70 /DOE O DRAM output enable Not used.70 DSCK_EN O DRAM clock enable71 /DWE O DRAM write enable72 /DR

46、AS O DRAM low address strobe73,74 DMBS0,DMBS1 O SDRAM bank select 0,175 VEE - I/O power supply (+3.3V) input76 VSS - Digital GND7782 DB0DB5 I/O DRAM data bus 0583 VCC - Core power supply (+2.5V) input84 VSS - Digital GND8590 DB6DB11 I/O DRAM data bus 61191 VSS - Digital GND92 VEE - I/O power supply

47、(+3.3V) input9396 DB12DB15 I/O DRAM data bus 121597 /DCS1 O SDRAM chip select 1 NC98 VSS - Digital GND99 VEE - I/O power supply (+3.3V) input100 /DCS0 O SDRAM chip select 0101 DQM O DATA input/output mask102 DSCS O SDRAM clock output103 VSS - Digital GND104 VEE - I/O power supply (+3.3V) input105 DC

48、LK I PLL 27MHz clock input NC106 YUV0 O YUV0 pixel output data Not used.106 CAMIN2 I Camera input 2 Not used.106 UDAC O U video DAC output Output for composite video out107 YUV1 O YUV1 pixel output data Not used.107 VREF I Video DAC reference voltage input108 YUV2 O YUV2 pixel output data NC108 CDAC

49、 O Video DAC output NCMICROCOMPUTERS TERMINAL DESCRIPTION8KDV-S210P/S220P/S230P/S240PPin No. Pin Name I/O Application Processing Operation Description109 YUV3 O YUV3 pixel output data Not used.109 COMP I Compensation input110 YUV4 O YUV4 pixel output data Not used.110 RSET I DAC current adjust input111 ADVEE - Video DAC analog power supply input112 VSS - Digital GND113 YUV5 O YUV5 pixel output data NC113 YDAC O Y video DAC output NC114 YUV6 O YUV6 pixel output data NC114 VDAC O V video DAC output NC115 YUV7 O YUV7 pixel output