Arcam-DV29-dvd-sm维修电路图 手册.pdf

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1、Service Manual DV29 DVD Player Issue 1.0 ARCAMARCAM Bringing music +5VD is used for all 5v Digital/Video supplies the +12VD is used for Scart switching and to power the HDMI circuit (not DV78). The 1V8 rail is derived from the 3V3 rail and is regulated by the adjustable regulator at location REG1003

2、. FMJ Dv29 Circuit description. RadioFans.CN The DV29 uses a separate isolated Toroid transformer and Rectification stages based around Bridge rectifiers DBR1000 and DBR1001 and bulk smoothing caps C1048 and C1049 to supply the Analogue stages the smoothed D.C output from this stage is fed L1013 (+)

3、 and L1015 (-). Regulator REG1001 is fed from the +15V3 rail and forms the Audio DAC supply. The Display board requires several supply voltages these are simply passed through the main board, being filtered on the way to prevent transmission of noise through to the surrounding electronics. The displ

4、ay takes the +5V, -19V, -13V5 and -9V the 13V5 and 9V form a floating 4.5V supply biased relative to the 19V grid voltage. Display Board The main component of the Display board is IC1 this is a Vacuum Florescent Display driver with keyboard san and a serial data in/out interface. The Chip receives d

5、isplay drive serial data from the Vaddis V chip on the main board via Con1 on pins 12, 13 and 14 these will be seen a DIN, STS and CLK this data is used to drive the VFD a DOUT line interfaces with the VADDIS V and supplies Keyboard Scan information. The keyboard scan is a 6 x 4 matrix with the Key

6、Source appearing at S3, S4, S5, S6 and the Keyscan data returns appearing a K2, K3 and K4. Please see: above for power supply information. The Infra red pick-up at location RXI receives RC5 data and send the data to the Vaddis V on the main board via transistors TR2 and TR3, LED 2 is used to mix the

7、 rear panel RC5, this is covered in-depth within the Coms and Video output section of this guide. Main Board electronics Zoran Vaddis V. The main processor/control chip on the main board is the Zoran Vaddis V at location IC202, this is the latest incarnation of the very popular Vaddis range of proce

8、ssors and allows for a much lower component count when compared to our earlier players as many of the playback functions have moved onto the Vaddis V silicon. Below you will see the major functions of the Vaddis V o 20 Bit digital video output for external Video DACs and HDMI output stage. o Decoded

9、 Analogue Video output (internal DAC) used on the DV78 only. o Digital Audio output 3 data lines 6 channels for internal L + R DACs and L + R + C + LS + RS for DV79 and DV29 also used for HDMI for the DV79 and DV29. o SPDIF output. o Internal display interface. o Internal ATAPI interface. o Internal

10、 IR interface. o Serial in/out for RS232 DV79/DV29 A more detailed explanation of the Vaddis V and peripheral components follows. Vaddis Power The Vaddis V is powered by two separate supplies the Vaddis requires a 1.8v supply for the core, this is regulated from the 3.3v rail by REG1003, the 3.3v ra

11、il is used to supply power to the I/P O/P ports of the chip. ATAPI interface CON203 is an ATAPI interface on a 40 way IDE connector. This is decoupled from the Drive via an array of decoupling resistors as required by the ATAPI spec. RadioFans.CN Display Board interface The display board interface i

12、s on the 16 way FFC flexi foil connector at location CON202. Power for the display also travels on the connector. There are 4 wires to interface with the VFD driver chip these are seen as. o XFPDIN - Data to the display board o FPDOUT - Data from the display board o XFPCLK - Clock o XFPSEL - Chip se

13、lect The above control lines are level shifted to 5v logic from 3.3v levels by IC200 (74HCT125) these are the levels required by the VFD drive chip. The IR output from the Display board arrives as IRRCV this is an open collector signal, which can be wire-Ord with the re-panel remote input. Digital A

14、udio The Digital audio leaves the chip 3 sets of data lines labelled as. o ADAT0 - Left and Right channel data o ADAT1 - Left and Right surround o ADAT2 - Centre and Sub Along with the ADAT line we will also see the ABCLK and ALRCK as required for IS2 data conversion. The Vaddis V also supplies a di

15、rect SPDIF output for interfacing with ancillary processing equipment. Digital Video The Digital Video output from the Vaddis V consists of the following signals: o VIDPO to 19 - 20 Bit wide digital video data o CLK_27M - 27 Mhz Video clock o VSYNC - Vertical sync o HSYNC - Horizontal Sync The 20 bi

16、t wide bus VIDP0 to 19 provides video data as follows. Interlaced video mode: VIDP0 to 7 provide multiplexed 8 bit Y, Cb and Cr data with VIDPO being the Isb. Progressive scan video mode: VIDP0 to 9 provide 10 bit multiplexed Cb, Cr data with VIDP0 being the Isb. VIDP10 to 19 provide 10 bit Y data w

17、ith VIDP10 being the Isb. Flash/ SDRAM IC203 is a 64Mbit (32 bit x 2Meg) SDRAM. It runs at 135MHz IC205 is a 16Mbit (16 bit x 1Meg) intel type flash IC for program storage (Player software). The flash interfaces to the Vaddis V using the SDRAM bus it may appear that the bus connects to the flash in

18、a random manner, however this is simply because the Vaddis bus is multiplexed that way. The Flash will be accessed at power up and the contents are copied to the SDRAM the program will then be run from the SDRAM. Series resistors are employed to isolate the flash bus from the main SDRAM bus. EEPROM

19、IC204 is a 8kBit (1K x 8) Serial EEPROM. This is used for storage of non-volatile storage of player settings, region settings and bookmark data. Clocks CLK27MV is the 27Mhz clock for video. It is used to generate the 135Mhz clock for the Vaddis microprocessor and DSP. The MCLKV is the audio master c

20、lock for the Vaddis. We run the Vaddis in PLL bypass mode and generate or own master clock (see main clock section of manual) for higher accuracy and improved performance across Audio and Video. RESET IC201 is a reset generator chip that monitors the +3.3V rail and ensures a reset signal PWR_ON_RESE

21、T* is generated on power up, or if the mains power dips below an operational level. This signal is used to reset the Vaddis V and Flash micro only. The Vaddis V line labelled as RESET* resets the remaining circuitry of the player apart from the HDMI chip, this has its own reset line labelled as HDMI

22、_RESET this is necessary if we require to reset the HDMI chip only (for example when the HDMI sink is connected and then disconnected). Serial Port The VADDIS V can interface with the external world via the RS232 connector at location CON900 and the RS232 Transceiver at location IC900, the serial da

23、ta lines are shown as SERIAL RX and SERIAL TX these lines allow for direct control over the unit via RS232. RadioFans.CN Fig 3. GPIO control signals from the Vaddis V Single Name I/P-O/P Function PSUFSO-1 Output Control PSU Clock divider ENABLE_AV Output SCART control High in normal operation and lo

24、w in standby 16/9 Output Scart 16/9 anamorphic control line 9190INT* Input Interrupt signal from SII9190 HDMI transmitter GAIN_SCALING Output High for HDCD gain scaling ML_8740_0-2 Output SPI load signal for Audio DACs 0,1 and 2 (see note 1) MC Output SPI clock signal for DAC control MD Output SPI d

25、ata signal for DAC control FSELE0-1 Output Frequency select generator MUTE* Output Active low audio mute signal DDC_SDA,DDC,SCL I/O 12C bus for DDC channel on HDMI interface PROG_INT* Output High for Progscan mode, Low for interlaced mode. Controls Sil9130 data mux HDMI_RESET* Output Reset signal fo

26、r HDMI transmitter RESET* Output System reset Clocks and SPDIF stage. IC300 is a SM8707E clock generator IC. This IC is sensitive to noise on its power supply, which causes clock jitter for this reason we have a independent Low dropout low noise +3v3 power supply for the chip based around the regula

27、tor at location REG300. X300 is a 27Mhz crystal that IC300 uses to generate all the video and audio clocks required by the system the crystal sits on the XTI and XTO pins of the chip, the 27Mhz output at Pin 4 (MO2) is used to drive the Vaddis chip directly bypassing the internal PLL. The frequency

28、of the audio master is dependent on the on the current audio sample rate (I.e the sample rate required by the format CD=44.1Khz and DVD=48khz etc) and this is set by the system micro via the FSLO and FSEL1 this selects either the 22.5792Mhz or 24.576Mhz clock from frequency from IC300 this may then

29、be divided by 2 by the clock divide chip at location IC306 depending on the status of FSEL1. Therefore 4 clock frequencies may be obtained to support all required audio samples rates. Nand gate IC303 is used to gate FSEL1 with ENABLE_AV (which is low in standby mode) as such when in standby mode the

30、 audio clock is disabled. Clock Buffer IC301 us used to buffer the audio master clock. The circuit is arranged so that each device that requires the audio master clock has its own driver these are seen as. o MCLK_DAC0 - Pin 18 o MCLK_DAC1 Pin 16 o MCLK_DAC2 Pin 14 o MCLK_VADDIS Pin 3 o MCLK_HDMI Pin

31、 9 We also run the Mute Line from the Vaddis V IC301 this can be seen on Pin 12 and drives transistor TR401, the transistor pulls the relays RLY400, RLY500, RLY600 to ground and un-mutes the audio outputs. IS2 Audio Data IC302 and IC309 are buffers for the 12S signals these ensure that the signals t

32、ravelling to the DACs are point to point. IC302 deals with the ALRCK and ABCLK and IC309 the ADAT0,1,2 all signal are split into three separate lines for the three stereo DACS. PSU Clock Divider IC304 and IC305 form a clock divide by 1, 2 or 4 to ensure the PSU clock is always either 44.1kHz or 48Kh

33、z (See fig 1 within the power supply description section). This circuit will also switch the PSUCLK off when switching between sample rates (the PSU will free run when the PSUCLK is not present). SPDIF Output The SPDIF output consists of IC308 implemented as a inline buffer and parallel output buffe

34、r. Gate A buffers the signal so that the SPDIF line from the VADDIS sees fewer loads and form a feed to the Optical output transmitter, gates B,C and D drive the SPDIF in parallel so that we can drive a 75ohm load adequately. The resistors at the output of IC308 are arrange so that the output will b

35、e 500mV pk- pk when the output is terminated with a 75 ohm load at the same time the output impedance of the circuit is 75ohms as required by the Sony Philips Digital Interface specification, the transformer at location TX301 electrically isolates the SPDIS output. RadioFans.CN Left and Right channe

36、l D to A stages The Wolfson WM8740 stereo DAC requires +5V(A) and a +3V3 supply along with the Digital Audio data lines already described in this guide. The Left channel output only will be described in this section as all audio output stages are the identical (all six channels of a DV79) apart from

37、 the HDCD gain switching for L + R only. IC400B and associated components for a 2nd order Bessel filter with a differential input and a gain of 1 this follow by a output buffer IC401B, the gain of IC401B is control by the switching chip at location IC402, in normal use the Gain of IC401B is set to 1

38、.1 but in HDCD mode the IC402 switches a second 10k resistor in parele with R413 and the gain is set to 2.2 allowing for the higher audio output required by the HDCD standard. C436 is a A.C coupling capacitor used to remove the few mV of offset that the DAC produces, D400 provides protection against

39、 from ESD. The all output relays are under control of the Vaddis V chip but will also mute the outputs instantly under mains failure conditions. Switching drive is provided by TR401 (MUTE_BUF) and TR400 (AC_PRES) the relays are in mute mode if either the input to TR401 is Low or if the input to TR40

40、0 is high. Please note: The Scart left/right audio is fed from the outputs of the left/right audio stages. Video Encoder The video encoder at location IC703 is an Analogue devices ADV7310 video encoder, supporting interlaced and progressive scan video. Please note the 0.1% tolerance components aroun

41、d this stage. IC703 runs on a 2.5V supply provided by REG700 the voltage reference for the chip of 1.225V is provided by REF700 and should be seen on Pin 46. C730-731 and R736 form an external PLL filter. The Data lines into the encoder arrive as VIDP0 19 from the outputs of the VADDIS V chip. The e

42、xternal current setting resistors for the internal DACS are seen as R721-R722 and R738-R739 these set the correct output level for the DACS. The encoder gives out 6 video signals, for composite, S-Video (Y and C) and shared YUV/RGB signals. The setting of the RGB or YUV mode is select with the Video

43、 settings page of the Setup menu. The six analogue output signals are seen as. o DAC_A = Composite o DAC_B = SVID Y o DAC_C = SVID C o DAC_D = Y or Green o DAC_E = U or Blue o DAC_F = V or Red Please note: When the player is in Progressive scan mode the composite and S-Video signals will be switched

44、 off. The Video outputs from IC703 are filtered by six identical filters. For instance if we look at the Composite stage we will see a very slow roll off filter comprising of C719, C721 with L701 and L703 the 3dB point of the filter stage is around 40Mhz, resistors R700 and R702 form a load for the

45、current output DAC and as such set the relative output level. The outputs are driven by the Video op-amp at location IC700A this has a gain of 2.15 and is terminated by a 75ohm resistor, D701 forms protection against ESD. These signals now travel to the COMMS and Video extension card on Con 901. SCA

46、RT Output RGB and Composite video signals as well as left and right audio signals are all present on the SCART output socket. As the RGB and YUV signals share the same output port at the Vaddis V the player must be set to RGB SCART operation to have a RGB output on the SCART. Please note: When in RG

47、B SCART mode the RGB does not contain a Sync signal and the sync must be taken from the Composite out (4 wire RGB). Also present at the Scart are a number of control flags for the monitor these include 2 GPIO control lines direct from the Vaddis. o ENABLE_AV o 16/9 These are seen at the SCART output

48、 pins as. o O/6/12 o RGB STAT The 0/6/12 line (SCART pin 8) is used to inform the monitor of the screen format being sent by the player as set in the video set-up section of the software. o Standby = 0V o 16:9 aspect ratio = 6V o 4:3 aspect ration = 12V The RGB status line (SCART pin 16) will be see

49、n as 0v = no RGB and 1v is RGB present. RadioFans.CN HDMI output stage Please note: Due to the plug and play nature of the HDMI/DVI interface, if presented with a reported no HDMI problem it is worth checking all set-up parameters of both the DVD player and the Plasma/Projector in use before performing component level diagnostics on this section. HD