Denon-AVR981-avr-sm维修电路图 手册.pdf

《Denon-AVR981-avr-sm维修电路图 手册.pdf》由会员分享，可在线阅读，更多相关《Denon-AVR981-avr-sm维修电路图 手册.pdf（127页珍藏版）》请在收音机爱好者资料库上搜索。

1、Hi-Fi Component SERVICE MANUAL MODEL AVR-2801/981 AV SURROUND RECEIVER ? Some illustrations using in this service manual are slightly different from the actual set. TUNING BAND TITLEMENU/GUIDE MODE MEMORY USE/LEARNT.TONEMULTIOUTPUTSET UP RETURN STATUS DISPLAY ON SCREEN SYSTEM SETUP SURROUND PARAMETE

2、R CH SELECT SELECT ENTER RadioFans.CN 2 AVR-2801/981 SPECIFICATIONS AUDIO SECTION (Power Amplifier) Rated output:Front:90 W + 90 W(8 /ohms, 20 Hz 20 kHz with 0.05 % T.H.D.) 135 W + 135 W(6 /ohms, 1 kHz with 0.7 % T.H.D.) Center:90 W(8 /ohms, 20 Hz 20 kHz with 0.05 % T.H.D.) 135 W(6 /ohms, 1 kHz with

3、 0.7 % T.H.D.) Surround:90 W + 90 W(8 /ohms, 20 Hz 20 kHz with 0.05 % T.H.D.) 135 W + 135 W(6 /ohms, 1 kHz with 0.7 % T.H.D.) Dynamic power:120 W 2 ch (8 /ohms) 170 W 2 ch (4 /ohms) 200 W 2 ch (2 /ohms) Output terminals:Front:A or B6 16 /ohms A + B8 16 /ohms Surround/Center:6 16 /ohms (Analog) Input

4、 sensitivity/input impedance:200 mV/47 k/kohms Frequency response:10 Hz 100 kHz: +0, 3 dB (DIRECT mode) S/N:102 dB (DIRECT mode) Distortion:0.008 % (20 Hz 20 kHz) (DIRECT mode) Rated output:1.2 V (Digital) D/A output:Rated output 2 V (at 0 dB playback) Total harmonic distortion - 0.008% (1 kHz, at 0

5、 dB) S/N ratio 102 dB Dynamic range - 96 dB Digital input:Format Digital audio interface (Phono equalizer (PHONO input-REC OUT) Input sensitivity:2.5 mV RIAA deviation:1 dB (20 Hz to 20 kHz) Signal-to-noise ratio:74 dB (A weighting, with 5 mV input) Rated output/Maximum output:150 mV/7 V Distortion

6、factor:0.03% (1 kHz, 3 V) VIDEO SECTION (Standard Video Jacks) Input/output level and impedance:1 Vp-p, 75 /ohms Frequency response:5 Hz 10 MHz +0, 3 dB (S-video jacks) Input/output level and impedance:Y (brightness) signal 1 Vp-p, 75/ohms C (color) signal 0.286 Vp-p, 75/ohms Frequency response:5 Hz

7、 10 MHz +0, 3 dB TUNER SECTION FM (Note: V at 75 /ohms, 0 dBf = 1 10-15 W)AM Receiving range:87.50 MHz 107.90 MHz520 kHz 1710 kHz (for North America model)(for North America model) 87.50 MHz 108.00 MHz522 kHz 1611 kHz (for Europe, China, Hong Kong,(for Europe, China, Hong Kong, Taiwan R.O.C. and Mul

8、tiple voltage models)Taiwan R.O.C. and Multiple voltage models) Usable sensitivity:1.0 V (11.2 dBf)18 V 50 dB quieting sensitivity:MONO1.6 V (15.3 dBf) STEREO23 V (38.5 dBf) S/N ratio:MONO80 dB STEREO75 dB Total harmonic distortion:MONO0.15 % STEREO0.3 % GENERAL Power supply:AC120 V, 60 Hz (for Nort

9、h America and Taiwan R.O.C. models) AC230 V, 50 Hz (Europe model) AC220 V, 50 Hz (for China model) AC115/230 V, 50/60 Hz (for Hong Kong and Multiple voltage) Power consumption:5.0 A (for North America model) 270 W (for Europe, China, Hong Kong, Taiwan R.O.C. and Multiple voltage models) Maximum exte

10、rnal dimensions:434 (W) 171 (H) 416 (D) mm (17-3/32 6-11/32 16-3/8) Weight:11.5 kg (25 lbs. 6 oz.) REMOTE CONTROL UNIT(RC-881: for North America, China, Hong Kong, Taiwan R.O.C. and Multiple voltage models) (RC-882: for Europe model) Batteries:R6P/AA Type (two batteries) External dimensions:70 (W) 2

11、15 (H) 24 (D) mm (2-3/4 8-15/32 15/16) Weight:200 g (Approx. 7 oz.) (including batteries) SAFETY PRECAUTIONS The following check should be performed for the continued protection of the customer and service technician. LEAKAGE CURRENT CHECK Before returning the unit to the customer, make sure you mak

12、e either (1) a leakage current check or (2) a line to chassis resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the power cord is less than 460 kohms, the unit is defective. RadioFans.CN 3 AVR-2801/981 WIRE ARRANGEMENT If wire bundles

13、 are untied or moved to perform adjustment or parts replacement etc.,be sure to rearrange them neatly as they were originally bundled or placed afterward. Otherwise, incorrect arrangement can be a cause of noise generation. Wire arrangement viewed from the top RadioFans.CN 4 AVR-2801/981 DISASSEMBLY

14、 (Follow the procedure below in reverse order when reassembling) 1. Top Cover Remove 3 screws on the rear and 6 screws on both sides to detach the Top Cover as shown in the arrow direction. 2. Front Panel (1) Remove 7 screws from the top and bottom edges of the Front Panel. (2) Release 4 top and bot

15、tom hooks, then detach the Front Panel as shown in the arrow direction. Top Cover Front panel 12 3 3. Inner Panel Pull out the Inner Panel in the arrow direction after removing 3 screws .4 Inner panel Hook Hook 1 2 2 3 3 3 4 4 Hook Hook RadioFans.CN 5 AVR-2801/981 4. Inner Panel Assy (1) Remove 3 ro

16、und and 1 square knobs, and unscrew 4 nuts. (2) Remove 19 screws fixing each P.W.B. 5. Amp Unit (1) Remove 2 screw to detach Pre-out Unit . (2) Take off the Amp Unit as shown in the arrow direction after removing 1 screw . Nut 5 67 8 9 10 6. Regulator Unit Take off the Regulator Unit as shown in the

17、 arrow direction after removing 8 screws .11 5 5 5 Round knob Square knob Round knob 6 7 8 9 10 11 Nut RadioFans.CN 6 AVR-2801/981 7. S-Video / C-video / Audio-in Edge detection is “Ed”; Detection by both shifting is “E Serial data detection is “S” (Serial data output is also “S”). Res: State at res

18、et. “H”= Outputs High Level at reset “L”= Outputs Low Level at reset “Z”= Becomes High impedance mode at reset Ini: Initial output state. Function: Function and logical level explanation of signals to be interface. 124 25 40 4164 65 80 1313 AVR-2801/981AVR-2801/981 RadioFans.CN TMP93CS41F (AU: IC301

19、)TMP93CS41F (AU: IC301) NameNameFunctionFunction TMP93CS41F Terminal FunctionTMP93CS41F Terminal Function PinPin No.No. 1 1V REFLV REFLA/D ref. GNDA/D ref. GND 2 2A VssA VssA/D GNDA/D GND 3 3A VccA VccAD +5VAD +5V 4 4_NMI_NMII INot used (fixed to H)Not used (fixed to H) 5 5P70/TI0P70/TI0C15C15O OC C

20、L LL LFixed to L (DSP ROM address cont. out bit 15, not used)Fixed to L (DSP ROM address cont. out bit 15, not used) 6 6P71/TO1P71/TO1C16C16O OC CL LL LDSP program ROM address cont. output bit 16DSP program ROM address cont. output bit 16 7 7P72/TO2P72/TO2C17C17O OC CL LL LDSP program ROM address co

21、nt. output bit 17DSP program ROM address cont. output bit 17 8 8P73/TO3P73/TO3O OC CL LL L 9 9P80/INT4/TI4P80/INT4/TI4_INTREQ_INTREQI/OI/OC CEuEuE E &L&LZ ZDSP request input and cont. output (L: Rq & cont.)DSP request input and cont. output (L: Rq & cont.) 1010P81/INT5/TI5P81/INT5/TI5B. DOWN_B. DOWN

22、_I IEuEuE E &L&LZ ZPower down detect (H: Detected)Power down detect (H: Detected) 1111P82/TO4P82/TO4DSP SSDSP SSO OC CZ ZL L 1212P83/TO5P83/TO5_REQ_REQO OC CEuEuH HL L MAIN-SUB CPU comm. control output (L: Comm. request fromMAIN-SUB CPU comm. control output (L: Comm. request from sub)sub) 1313P84/IN

23、T6/TI6P84/INT6/TI6_ACK_ACKI IEuEuE E &L&LMAIN-SUB CPU comm. control input (L: Ack. return from main)MAIN-SUB CPU comm. control input (L: Ack. return from main) 1414P85/INT7/TI7P85/INT7/TI7ERRERRI IE E &L&LDIR control input terminal (LC89055Q)( H: ERR)DIR control input terminal (LC89055Q)( H: ERR) 15

24、15P86/TO6P86/TO6_DSP RESET_DSP RESETO OC CL LL LDSP reset output terminal (L: Reset)DSP reset output terminal (L: Reset) 1616P87/INT0P87/INT0_CS_CSI IE E &L&L DIR control input terminal (LC89055Q), when CH status changeDIR control input terminal (LC89055Q), when CH status change L LH H 1717P90/TXD0P

25、90/TXD0SISIO OC CMAIN-SUB CPU comm. control terminal (data output)MAIN-SUB CPU comm. control terminal (data output) 1818P91/RXD0P91/RXD0SOSOI IMAIN-SUB CPU comm. control terminal (data input)MAIN-SUB CPU comm. control terminal (data input) 1919P92/_CTS0/SCLK0P92/_CTS0/SCLK0CLKCLKI IC CMAIN-SUB CPU c

26、omm. control terminal MAIN-SUB CPU comm. control terminal (I2C clock in/output)(I2C clock in/output) 2020P93/TXD1P93/TXD1DSP DATADSP DATAO OC CZ ZL L 2121P94/RXD1P94/RXD1DSP SODSP SOO OC CLvLvZ ZL L 2222P95/SCLK1P95/SCLK1DSP CLKDSP CLKO OC CZ ZL L 2323AM8/_16AM8/_16Fixed to +5VFixed to +5V 2424CLKCL

27、KO OC CEuEu 2525VccVcc+5V+5V 2626VssVssI/O1I/O1GNDGND 2727X1X1XinXinI IX X tal connectiontal connection 2828X2X2XoutXoutO OX X tal connectiontal connection 2929_EA_EAFixed to GNDFixed to GND 3030_RESET_RESETRESET2_RESET2_I IEuEuLvLvL LReset input (controlled by main CPU)Reset input (controlled by ma

28、in CPU) 3131P96/XT1P96/XT1A/D RESETA/D RESETO ON NEuEuH HH HA/D control terminal (L: Reset)A/D control terminal (L: Reset) 3232P97/XT2P97/XT2O OC CEdEdL LL L 3333TEST1TEST1 Connected to TEST2Connected to TEST2 3434TEST2TEST2 Connected to TEST1Connected to TEST1 3535PA0PA0DINADINAO OC CEdEdL LL LDigi

29、tal input switching control outputDigital input switching control output 3636PA1PA1DINBDINBO OC CEdEdL LL LDigital input switching control outputDigital input switching control output 3737PA2PA2DINCDINCO OC CEdEdL LL LDigital input switching control outputDigital input switching control output 3838P

30、A3PA3O OC CEdEdL LL L 3939PA4PA4DIRECTDIRECTO OC CEdEdL LL LDigital direct data switch cont. terminal (H: Direct)Digital direct data switch cont. terminal (H: Direct) 4040PA5PA5O OC CEdEdL LL L SymbolSymbolI/OI/OTypeTypeOpOpDetDetResResInitInit NameNameFunctionFunction PinPin No.No. 4141PA6PA6DEEMPD

31、EEMPO OC CEdEdL LL LDAC de-emphasis filter cont. out terminal (H: ON)DAC de-emphasis filter cont. out terminal (H: ON) 4242PA7/SCOUTPA7/SCOUT96k-DAC96k-DACO OC CZ ZL LDAC control terminal (H: Sample frequency 96kHz)DAC control terminal (H: Sample frequency 96kHz) 4343ALEALEO OC CL LL LAddress latch

32、enableAddress latch enable 4444VccVcc+5V+5V 4545P00/AD0P00/AD0AD0AD0I I 4646P01/AD1P01/AD1AD1AD1I I 4747P02/AD2P02/AD2AD2AD2I I 4848P03/AD3P03/AD3AD3AD3I I 4949P04/AD4P04/AD4AD4AD4I I 5050P05/AD5P05/AD5AD5AD5I I 5151P06/AD6P06/AD6AD6AD6I I 5252P07/AD7P07/AD7AD7AD7I I 5353P10/AD8/A8P10/AD8/A8A8A8I I

33、5454P11/AD9/A9P11/AD9/A9A9A9I I 5555P12/AD10/A10P12/AD10/A10A10A10I I 5656P13/AD11/A11P13/AD11/A11A11A11I I 5757P14/AD12/A12P14/AD12/A12A12A12I I 5858P15/AD13/A13P15/AD13/A13A13A13I I 5959P16/AD14/A14P16/AD14/A14A14A14I I 6060P17/AD15/A15P17/AD15/A15A15A15I I 6161_WDTOUT_WDTOUTO OC CZ ZH H 6262VssVs

34、sGNDGND 6363VccVcc+5V+5V 6464P20/A0/A16P20/A0/A16A16A16I I 6565P21/A1/A17P21/A1/A17DIR CLKDIR CLKO OC CZ ZL LDIR control terminal (LC89055Q) control clock outputDIR control terminal (LC89055Q) control clock output 6666P22/A2/A18P22/A2/A18DIR CEDIR CEO OC CZ ZL LDIR control terminal (LC89055Q) contro

35、l chip enable outputDIR control terminal (LC89055Q) control chip enable output 6767P23/A3/A19P23/A3/A19DIR MOSIDIR MOSIO OC CZ ZL LDIR control terminal (LC89055Q) control data outputDIR control terminal (LC89055Q) control data output 6868P24/A4/A20P24/A4/A20DIR MISODIR MISOI ILvLvDIR control termina

36、l (LC89055Q) control data inputDIR control terminal (LC89055Q) control data input 6969P25/A5/A21P25/A5/A21SW-SUMSW-SUMO OC CL LL LSubwoofer output summation cont. outputSubwoofer output summation cont. output 7070P26/A6/A22P26/A6/A22DAC-RESETDAC-RESETO OC CL LH HDAC control terminal (L: Power down m

37、ode, DAC control terminal (L: Power down mode, (rising edge) Reset)(rising edge) Reset) 7171P27/A7/A23P27/A7/A23SEL CKSEL CKO OC CZ ZL LADC/DIR data clock switching control terminal (L: ADC)ADC/DIR data clock switching control terminal (L: ADC) 7272P30/_RDP30/_RD_RD_RDO OC CZ ZL L 7373P31/_WRP31/_WR

38、_WR_WRO OC CZ ZL L 7474P32/_HWRP32/_HWRCSICSII ILvLvDIR control input terminal (L: PCM)DIR control input terminal (L: PCM) 7575P33/_WAITP33/_WAITERR MUTE_ERR MUTE_O OC CL LL LPop noise preventive mute control output (L: Mute)Pop noise preventive mute control output (L: Mute) 7676P34/_BUSRQP34/_BUSRQ

39、I I 7777P35/_BUSRQP35/_BUSRQDIG. (AC3) MUTEDIG. (AC3) MUTEO OC CZ ZL LDigital mute control output (L: AC-3 or DTS decode enable)Digital mute control output (L: AC-3 or DTS decode enable) 7878P36/_R/WP36/_R/WI I 7979P37/_RASP37/_RASDIR RESETDIR RESETO OC CZ ZL LDIR control output (LC89055Q) (L: Reset

40、)DIR control output (LC89055Q) (L: Reset) 8080P40/_CS0/_CAS0P40/_CS0/_CAS0O OC CZ ZL L 8181P41/_CS1/_CAS1P41/_CS1/_CAS1O OC CZ ZL L 8282P42/_CS2/_CAS2P42/_CS2/_CAS2_CS0_CS0O OC CZ ZL LFlash memory control terminalFlash memory control terminal 8383P60/PG00P60/PG00DSP C. RESETDSP C. RESETO OC CZ ZL LD

41、SP reset output terminal (L: Reset)DSP reset output terminal (L: Reset) 8484P61/PG01P61/PG01SCDOUTSCDOUTI ILvLvDSP status data input terminalDSP status data input terminal 8585P62/PG02P62/PG02DSP_C. CSDSP_C. CSO OC CZ ZL LDSP chip select cont. output (L: Data out)DSP chip select cont. output (L: Dat

42、a out) 8686P63/PG03P63/PG03DSP C. CLKDSP C. CLKO OC CZ ZL LDSP data clock output terminalDSP data clock output terminal 8787P64/PG10P64/PG10SCDINSCDINO OC CZ ZL LDSP data output terminalDSP data output terminal 8888P65/PG11P65/PG11O OC CZ ZL L 8989P66/PG12P66/PG12O OC CZ ZL L 9090P67/PG13P67/PG13O O

43、C CZ ZL L 9191VssVssGNDGND 9292P50/AN0P50/AN0I I 9393P51/AN1P51/AN1I I 9494P52/AN2P52/AN2EMPEMPI ILvLvH: EMP onH: EMP on 9595P53/AN3P53/AN396K DET96K DETI ILvLv96k signal detect input, H: 96k96k signal detect input, H: 96k 9696P54/AN4P54/AN4I I 9797P55/AN5P55/AN5I I 9898P56/AN6P56/AN6I I 9999P57/AN7

44、P57/AN7I I 100100V REFHV REFHAD ref. +5VAD ref. +5V SymbolSymbolI/OI/OTypeTypeOpOpDetDetResResInitInit 75 76 100 1 25 26 50 51 1414 AVR-2801/981AVR-2801/981 RadioFans.CN 15 AVR-2801/981 LC89055W (AU: IC800) Pin NameFunction LC89055W Terminal Function Pin No. 1DISELIData input terminal (select input

45、pin of DIN0, DIN1) 2DOUTOInput bi-phase data through output terminal 3DIN0IAmp built-in coaxial/optical input correspond data input terminal 4DIN1IAmp built-in coaxial/optical input correspond data input terminal 5DIN2IOptical input correspond data input terminal 6DGNDDigital GND 7DVDDDigital power

46、supply 8RIVCO gain control input terminal 9VINIVCO free-run frequency setting input terminal 10LPFOPLL loop filter setting terminal 11AVDDAnalog power supply 12AGNDAnalog GND 13CKOUTOClock output terminal (256fs, 384fs, 512fs, Xtal osc., VCO free-run osc.) 14BCKO64fs clock output terminal 15LRCKOfs

47、clock output terminal (L: Rch, H: Lch, I2S: Reverse) 16DATAOOData output terminal 17XSTATEOInput data detecting result output terminal 18DGNDDigital GND 19DVDDDigital power supply 20XMCKOXtal osc. clock output terminal (24.576MHz or 12.288MHz) 21XOUTOXtal osc. connection output terminal 22XINIXtal o

48、sc. connection output terminal 23EMPHAOEmphasis information output terminal of channel status 24AUDIOOBit1 output terminal of channel status 25CSFLAGOTop 40bit revise flag output terminal of channel status 26F0/P0/C0OInput fs cal. sig. out / data type out / input word inf. output terminal 27F1/P1/C1

49、OInput fs cal. sig. out / data type out / input word inf. output terminal 28F2/P2/C2OInput fs cal. sig. out / data type out / input word inf. output terminal 29VF/P3/C3OValidity flag out / data type out / input word inf. output terminal 30DVDDDigital power supply 31DGNDDigital GND 32AUTOONon PCM burst data transfer detect sig. output terminal 33BPSYNCONon PCM burst data preamble Pa, Pb, Pc, Pd sync sig. output terminal 34ERROROPLL lock error, data error flag output terminal 35DOOCPU I/F read data output terminal 36DIICPU I/F