Arcam-DV88-dvd-sm维修电路原理图.pdf

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1、DV88 DiVA DV88 DVD Player + Progressive Scan Service Manual ARCAM Issue 2.0 RadioFans.CN 收音机爱 好者资料库 Contents List ! Contents list ! Circuit description ! Frequently asked questions issue 1 ! Software release notes 1.1 to 1.76 ! Progressive scan upgrade instructions ! Service guide ! Circuit diagrams

2、 ! Component overlays ! Circuit board parts list ! General assembly parts list RadioFans.CN 收音机爱 好者资料库 Circuit Descriptions L875 DSP Circuit Summary This board is used in the DV88 and DV27 DVD players. It can be considered to be the central digital core of the player, and is based around the Zoran V

3、addis III DVD decoder IC. A Siemens C161 microcontroller is used as the system CPU and software runs on this which controls the whole system. A video DAC is also present, as well as an ATAPI bridge device. The board interfaces with the display board, the DVD drive, and the AV board. Overview The hea

4、rt of the system is the Zoran Vaddis III IC, which receives a data stream on its AV interface. The chip has 2 separate DSPs, one for audio and one for video. The MPEG video/ audio decoding and Dolby digital audio decoding are performed in these DSPs as well as other post processing on audio and vide

5、o, OSD generation, decryption of DVD and other functions. The vaddis is controlled by the system CPU via its host bus interface. The system uses an ATAPI type DVD drive. With the AV interface the Vaddis AV input comes directly from the drive, and the drive is controlled from the system CPU via an SS

6、C bus (standard synchronous control). The design was modified to use the ATAPI standard by the inclusion of the ATAPI bridge chip. This has an ATAPI interface to the drive, and an SSC interface to the CPU. A data stream is provided which interfaces to the Vaddis AV input. On the output side of the s

7、ystem, the digital audio output from the Vaddis is passed to the AV board in I2S format. The video output from the Vaddis is in the form of a digital 8 bit parallel bus, with 27MHz clock, containing multiplexed chroma and luma data. H and V synchronisation is performed by the use of embedded sync pa

8、tterns in the data. This type of bus is a standard interface known as BT-656. This bus connects to the video DAC, an Analog Devices ADV7172. This does PAL/NTSC encoding and D-A conversion, and gives out 6 channels of analogue video. These are composite, S-Video, and 3 lines that are switchable YUV/R

9、GB. All video outputs are passed to the AV board where they are filtered and buffered before going to the outside world. Circuit Description Refer to L875 circuit diagrams Sheet 1 - Top level This is the top level of the schematic and shows how the sheets link together plus some of the board interfa

10、ces. CN8 provides a serial port which may be connected to a PC via an RS232 transceiver, for debugging purposes. CN6 is the interface to the front panel. A 4 wire serial interface communicates with the VFD driver chip, which drives the display, scans the buttons and drives the LEDs on the front pane

11、l. This interface consists of FPDIN (serial data from panel), FPSEL (chip select), FPCLK (serial clock) and FPDOUT (serial data to front panel). IRIRQ is the signal from the IR remote receiver on the front panel, driven by an open collector circuit. This is because that line also goes to the progres

12、sive scan board in the DV27, which has the remote bus input on it. CN1 is the power input. +5V and +3.3V rails are provided. The Vaddis and its SDRAM operate on 3.3V, everything else runs on +5V. CN5 is the audio connector to the AV board. Digital audio in I2S and SPDIF formats are passed to the AV

13、board from here, as well as a number of control signals: FSEL0.1 Selects 1 of 4 audio clock frequencies MD, MC, ML8716_L, ML_8716_R, ML_8716_X 5 wire SPI bus to configure audio DACs GAIN_SCALING HDCD gain scaling signal. The audio master clock also comes on to the board here. It is generated on the

14、AV board and fed to the DSP board to synchronise the audio, of which more later. CN2 and CN3 are not fitted. They are the AV and host interface for the AV type drive that the system was originally designed to use. Sheet 2 - CPU The system CPU, U3, is a Siemens C161 16 bit ROM-less microcontroller ru

15、nning at 16MHz. ROM and RAM are external to the micro, so we have a CPU bus with 19 bits of address and 16 bits of data. The ROM memory is provided by U4 and U5 which contain the lower and upper 8 bits of program memory respectively. These are 28SF040 4Mbit (512K x 8) FLASH EEPROMs. These must be pr

16、ogrammed and fitted in their sockets before the board can be tested. Once in place they can be re-programmed in system, and the software has a feature where new software can be uploaded from a CD. It is important to note that these devices are re-programmable. The system RAM is provided by U6 and 7

17、which contain the lower and upper 8 bits of memory respectively. These are 1 Mbit (128K x 8) devices, making 256KByte memory altogether. U12 is an 8 bit wide latch that provides a few extra control output lines - these being a 5 wire serial control interface for the audio DACs, a reset signal for th

18、e AV drive (not used), and 16/9 which is used on the SCART status line. U1 is a power on reset generator, this resets the micro, and the micro has an output RSTOUT which provides the signal RESET. This goes to many devices on this board and the AV board and progressive scan board. U2 is a serial EEP

19、ROM, providing non-volatile storage of setup data. All the parameters from the setup menu are stored here, as well as bookmarks and the region code. The resistor packs RP1-3, are important pullup/pulldown resistors which configure the mode of the micro on power up. The resistors R2 and R12-15 are pr

20、ovided so we may configure the board for different devices. All must be fitted except R12 and R15 for normal configuration. Sheet 3 - Vaddis DVD decoder This sheet shows the Vaddis DVD decoder IC, U8, and its associated components. Going back to the block diagram, various bus interfaces were mention

21、ed. These can be seen on the schematic as follows: The AV interface This is used for carrying audio/video data from the ATAPI bridge to the Vaddis. The following lines are used. DVDDAT0:7 8 bit parallel data DVDSTRB Strobe signal DVDSOS Start of sector indicator DVDVALID Valid data indicator DVDREQ

22、Request signal (Vaddis output) DVDERR is not actually used in the ATAPI configuration we are using. The HOST bus interface The CPU uses this to control the Vaddis, it carries information both to and from the micro. HD0.7 The lower 8 bits of the system data bus HA1.4 Lower 4 bits of system address bu

23、s HWR- Write strobe HRD- Read strobe MPGCS- Chip select MPEGIRQ-Interrupt line generated by Vaddis Digital Video bus The 8 bit bus YUV0:7, with CLK27 provides the BT-656 type parallel digital video bus. The 27MHz clock is provided on 2 different lines. CLK27 is used for the video DAC (and also goes

24、to the ATAPI chip). CLK27PS is used for the progressive scan board. Digital Audio The audio output of the Vaddis is given out on the following signals SPDIF-I34 IEC 958 SPDIF output ASDAT0 Serial data for Left and right ASDAT1 Serial data for Lsurround, ASDAT2 Serial data for Centre, sub ALRCLK Word

25、clock ABCLK Bit clock Audio/Video clocks Special note should be made of the audio and video clocks in the system, there are separate asynchronous clocks used for video and audio. The video runs on the system 27MHz clock, which is generated by the Vaddis in conjunction with the crystal Y2. The audio

26、clock is generated on the AV board and this is totally asynchronous with respect to the 27MHz clock. This is slightly unusual, since most DVD players derive the audio clock from the video clock via a phase locked loop The Vaddis has a PLL which generates the audio clock, but we dont use it because i

27、t has horrendous jitter. Instead, we bypass the Vaddis PLL and configure AMCLK as an input. Our clock source is on the AV board and this is a very low jitter oscillator. The Vaddis maintains AV sync by dropping or repeating 1 frame of video to re-synchronise the streams when they start to get out of

28、 sync. In practice this happens very rarely because the 2 clocks are very accurate so the difference in frequency will be very small. It is important to note that without the audio clock present, no audio or video material can be played. CD-DSP interface (CDERR, CDFRM, CDDAT, CDCLK.) The Vaddis chip

29、 has a CD-DSP interface designed to connect to DVD drives with this type of interface for CDs. These signals are tracked on the board but they are not used. The data path for CDs is exactly the same as for DVDs. Reset and standby signals The signal MPGRST- is an active low signal that the micro uses

30、 to reset the Vaddis and ATAPI bridge chip. The signal MPGSTBY- is an active low signal that the micro uses to put the Vaddis in a low power mode while the player is in standby. SDRAM The Vaddis requires some memory for video and audio decoding and processing. This is provided by a 16MBit synchronou

31、s DRAM (512K x 16 bit x 2 banks). The board is arranged to allow 2 SDRAMs, but at present we only use one. U11 is fitted while U10 is not fitted. The Vaddis interfaces directly to the SDRAM with no other device being involved. PSU Synchronisation An interesting feature of the Arcam DVD player is tha

32、t the switch mode supply on the PSU is synchronised to the audio sampling frequency. This is done to reduce the switch mode noise on the audio output. The PSU will free run on its own, when tested, but when connected to the DSP board it will lock to the audio word clock. The signal ALRCLK is buffere

33、d by U14 to provide the signal LRCK_PSU which goes to the PSU. Sheet 4 - Video DAC This sheet shows the video encoder/DAC and output buffers. U9 is an Analog Devices ADV7172, which does PAL/NTSC encoding and has 6 DACs providing all our video outputs. It takes its input from the BT-656 video bus YUV

34、0.7, this bus is clocked by CLK27 (27MHz). No H/V sync signals are required since the H and V synchronisation is done with embedded sync patterns in the data. The chip has its operating parameters loaded by the system CPU via the I2C bus. There are 6 analogue outputs from U9. These are composite PAL

35、/NTSC, S-Video, and 3 lines that are configurable (via setup menu) to be YUV or RGB. The DACs have current outputs, so R16-21 have been chosen to give the required output level voltage, in conjunction with R22/24 and R23/25 which program the DAC current outputs. All channels are buffered by op-amps

36、U13,16,17. These have a gain of +2, and drive out to the AV board through a source impedance of 75R. The AV board has filtering and another buffer stage. There are 2 control signals that also go to the AV board video section. ENABLE_AV Used for SCART status signal. High when player is not in standby

37、 16/9 Used for SCART status signal. High when 16:9 TV type has been selected in setup menu. Digital Video output Connector CN4 provides a digital video output. This is used in the DV27 only, for connection to the progressive scan board. YUV0.7 are present on this connector along with clock CLK27PS.

38、The system reset signal RESET- is provided, and the I2C bus for control of devices on the progressive scan board. The signal IRIRQ is connected to pick up the output of the remote bus circuit which is on the progressive scan board. This is an open collector signal which can be driven from either the

39、 front panel or the remote bus input. Sheet 5 - ATAPI Bridge and interface U18 is a Zoran ZR36701 ATAPI to AV port bridge. It interfaces with the system CPU via the SSC bus, made up of the following signals: SSC_SCLK Clock (input to ZR36701) SSC_MTSR Data input (CPU to ZR36701) SSC_MRST Data output

40、(ZR36701 to CPU) SSC_ATN- Port ready signal (output from ZR36701) DRV_IRQ- Interrupt request generated by ZR36701 The chip also receives MPGRST- to reset it from the CPU. The system video clock CLK27 is connected to generate timing signals. The chip has an interface with the Vaddis referred to as th

41、e AV interface. See the section on the Vaddis for a description. The ZR36701 acts as a bridge between the SSC and AV interfaces on one side, and the ATAPI drive on the other. The ATAPI interface of the chip connects to the DVD drive via 40 way IDC connector CN10. Signal descriptions: ATCRESET-Active

42、 low reset generated by ZR36701 to ATAPI drive DD0.15 Bidirectional data bus DA0.2 Address lines - output from ZR36701 CS0-,CS1- Chip selects - output from ZR36701 make up part of ATAPI address INTRQ Interrupt request from drive to ZR36701 DIOW- Write strobe - output from ZR36701 DIOR- Read strobe -

43、 output from ZR36701 IORDY Device ready signal from drive Board Specifications Power Supply: +5V +/- 5% at 280mA nominal 3.3V +/-5% at 400mA nominal. Video output levels: Composite: 700mV nominal (in PAL) black-peak white into 75R S-Video: Y 700mV nominal (in PAL) black-peak white (in PAL) into 75R

44、S-Sideo: C 885mV pk-pk nominal (in PAL) into 75R Component Y: 700mV nominal (in PAL) black to peak white into 75R. Component U: 700mV pk-pk nominal for 100% colour bars, into 75R. Component V: 700mV pk-pk nominal for 100% colour bars, into 75R. L877 Circuit The PSU consists of 4 function blocks. The

45、se are : 1. Mains to DC block 2. -19V5 supply. 3. PSU Sync Cicuit. 4. Switch Mode PSU . The Mains to DC Block. The mains to DC Block provides an unregulated Isolated DC Voltage from the mains supply. The Mains Transformer TX1 (which is now toroidal - for reduced induced hum) has dual 115V primaries

46、which are connected in series for 230V operation and in parallel for 115 V operation by the rear panel operated slide switch SW2. F1 and F2 provide fusing for each primary winding and the switching is arranged to obviate the requirement for different fuses for 115V and 230V operation. For a given ou

47、tput power the current requirements for 115V operation are twice that for 230V operation. This requirements is met by having the fuses in parallel for 115V operation and having only F2 in circuit for 230V operation. The VDRs (Voltage Dependent Resistors) VDR1 and VDR2 ensure that the fuses will blow

48、 in the event of the rear panel switch being set for 115V and 230V being applied. It is likely that the VDRs will fail short in such circumstances and will then also require replacement. C1 and C2 are Y capacitors which form an EMC suppression network to common mode signals with common mode choke L1

49、. Connector SK6 provides connection for the analogue windings to the AV PCB. SK7 optionally allows a further transformer to be added to provide the analogue supply in a more expensive model. In such a model SK6 will then not be used and the additional transformer secondary will be plugged directly into the AV PCB. The mains transformer TX1 is specified to provide 25V DC at 195V Input and maximum load across C3 and give +/- 14.5V DC with 200mA on each rail when