Marantz-PMD661MKll-pssr-sm 电路图 维修手册.pdf

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1、START:|g1cz3Z09ximWbk6cjE4rRA=|2yz0ZLU8ZQ5HEnIFgE6VjCqckbnoDwdB2Yvj36wDyKg=|PLXqzLbC2dLvdexZ9XDk1w=|:END SERVICE MANUAL Portable Solid State Recorder MODEL PMD661MK For U.S.A., Canada, Europe, Japan model D A0A8 x8; A0A7 x16; with A10 defining auto precharge) to select one location out of the memory

2、 array in the respective bank. A10 is sampled during a precharge command to determine if all banks are to be precharged (A10HIGH) or bank selected by BA0, BA1 (A1LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50,

3、51, 53 A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 DQ0DQ15x16: I/OData input/output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51 are NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for x4). 2, 5, 8, 11, 44, 47, 50, 53 DQ0DQ7x8: I/OData input/output: D

4、ata bus for x8 (2, 8, 47, 53 are NCs for x4). 5, 11, 44, 50 DQ0DQ3x4: I/OData input/output: Data bus for x4. 40E2NCNo connect: These pins should be left unconnected. 36G1NCAddress input (A12) for the 256Mb and 512Mb devices 3, 9, 43, 49A7, B3, C7, D3 VDDQSupplyDQ power: Isolated DQ power on the die

5、for improved noise immunity. 6, 12, 46, 52 A3, B7, C3, D7 VSSQSupplyDQ ground: Isolated DQ ground on the die for improved noise immunity. 1, 14, 27A9, E7, J9VDDSupplyPower supply: +3.3V 0.3V. 28, 41, 54A1, E3, J1VSSSupplyGround. PIN/BALL DESCRIPTIONS 46 Q006 : S29AL016D70BFI020 (FROM) October 27, 20

6、08 S29AL016J_00_07S29AL016J9 D a t aS h e e t 1.Product Selector Guide Note See AC Characteristics on page 44 for full specifications. 2.Block Diagram Family Part NumberS29AL016J Speed OptionVoltage Range: VCC = 2.7-3.6V70 VCC = 3.0-3.6V55 Max access time, ns (tACC)5570 Max CE# access time, ns (tCE)

7、5570 Max CE# access time, ns (tOE)3030 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator Timer VCC Detector State Control Command Register VCC VSS WE# BYTE# WP# CE# OE# DQ0DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gatin

8、g Cell Matrix Address Latch A0A19 BLOCK DIAGRAM 10S29AL016JS29AL016J_00_07 October 27, 2008 D a t aS h e e t 3.Connection Diagrams Figure 3.1 48-pin Standard TSOP (TS048) Figure 3.2 48-ball Fine-pitch BGA (VBK048) A1 A15 A18 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC WP# RY/BY# A17 A7 A6 A5 A4 A

9、3 A2 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 A16 DQ2 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 A1B1C1D1E1F1G1H1 A2B2C2D2E2F2G2H2 A3B3C3D3E3F3G3H3 A4

10、B4C4D4E4F4G4H4 A5B5C5D5E5F5G5H5 A6B6C6D6E6F6G6H6 DQ15/A-1VSSBYTE#A16A15A14A12A13 DQ13DQ6DQ14DQ7A11A10A8A9 VCCDQ4DQ12DQ5A19NCRESET#WE# DQ11DQ3DQ10DQ2NCA18WP#RY/BY# DQ9DQ1DQ8DQ0A5A6A17A7 OE#VSSCE#A0A1A2A4A3 (Top View, Balls Facing Down) CONNECTION DIAGRAM 48-pin Standard TSOP 47 October 27, 2008 S29AL

11、016J_00_07S29AL016J13 D a t aS h e e t 4.Pin Configuration 5.Logic Symbol A0A1920 addresses DQ0DQ1415 data inputs/outputs DQ15/A-1DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE#Selects 8-bit or 16-bit mode CE#Chip enable OE#Output enable WE#Write enable WP#Write protect

12、: The WP# contains an internal pull-up; when unconnected, WP is at VIH. RESET#Hardware reset RY/BY#Ready/Busy output VCC 3.0 volt-only single power supply (see Product Selector Guide on page 9 for speed options and voltage supply tolerances) VSSDevice ground NCPin not connected internally 20 16 or 8

13、 DQ0DQ15 (A-1) A0A19 CE# OE# WE# RESET# BYTE#RY/BY# WP# PIN CONFIGURATION October 27, 2008 S29AL016J_00_07S29AL016J13 D a t aS h e e t 4.Pin Configuration 5.Logic Symbol A0A1920 addresses DQ0DQ1415 data inputs/outputs DQ15/A-1DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BY

14、TE#Selects 8-bit or 16-bit mode CE#Chip enable OE#Output enable WE#Write enable WP#Write protect: The WP# contains an internal pull-up; when unconnected, WP is at VIH. RESET#Hardware reset RY/BY#Ready/Busy output VCC 3.0 volt-only single power supply (see Product Selector Guide on page 9 for speed o

15、ptions and voltage supply tolerances) VSSDevice ground NCPin not connected internally 20 16 or 8 DQ0DQ15 (A-1) A0A19 CE# OE# WE# RESET# BYTE#RY/BY# WP# LOGIC SYMBOL 48 Q409 : TLV320AIC3106 (CODEC) Audio?Serial?Bus?Interface MIC3L /?LINE3L PGA 0/+59.5dB 0.5dB?steps ADC + + + HPRCOM HPLCOM HPLOUT VCM

16、VCM DAC L + Volume Control Effects DIN DOUT BCLK WCLK DINL DINR DOUTL DOUTR AGC SW-D2 SW-D1 SPI?/?I2C?Serial?Control?Bus SELECT CSEL/I2C_ADR0 SCLK/I2C_ADR1 MOSI/GPIO MISO/GPIO Bias/ Reference MICBIAS SCL/GPIO SDA/GPIO RESET MICDET Voltage?Supplies DVDD DRVDD DRVDD DRVSS DRVSS DVSS IOVDD AVDD_ADC AVS

17、S_ADC AVDD_DAC AVSS_DAC Audio?Clock Generation MCLK GPIO_1 GPIO_2 + + + HPROUT MIC3R?/?LINE3R ADC PGA 0/+59.5dB 0.5dB?steps +DACR Volume Control Effects AGC SW-D3 SW-D4 + MONO_LOP MONO_LOM LINE1RP LINE2RM LINE2RP LINE1RM SW-R0 SW-R3 SW-R1 SW-R2 SW-R4 SW-R5 RIGHT_LOP RIGHT_LOM LINE1LP LINE2LM LINE2LP

18、 LINE1LM SW-L0 SW-L3 SW-L1 SW-L2 SW-L4 SW-L5 LEFT_LOP LEFT_LOM MIC2RM?/?LINE2RM MIC2RP /?LINE2RP LINE2RP LINE2RM MIC1RM?/?LINE1RM MIC1RP /?LINE1RP LINE1RP LINE1RM MIC2LM?/?LINE2LM MIC2LP /?LINE2LP LINE2LP LINE2LM MIC1LM?/?LINE1LM MIC1LP /?LINE1LP LINE1LP LINE1LM TLV320AIC3106 SLAS509DDECEMBER 2006RE

19、VISED OCTOBER 2007 PACKAGING/ORDERING INFORMATION(1) PACKAGEOPERATINGORDERINGTRANSPORT PRODUCTPACKAGEDESIGNATORTEMPERATURENUMBERMEDIA, QUANTITY RANGE TLV320AIC3106IZQETrays, 360 BGA-80ZQE TLV320AIC3106IZQERTape and reel, 3000 TLV320AIC310640C to 85C TLV320AIC3106IRGZTape and reel, 250 QFN-48RGZ TLV3

20、20AIC3106IRGZRTape and reel, 2000 (1)For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at . Copyright 20062007, Texas Instruments IncorporatedSubmit Documentation Feedback3 Product Folder Link(s): TLV320AIC3106 B

21、LOCK DIAGRAM A 123456789 B C D E F G H J 48lead?QFN?Package (Bottom?View) 5x5mm?80Ball?BGA Package (Bottom?View) 4?8 1 1?2 1?3 2?4 2?5 3?6 3?7 (Not?to?scale) TLV320AIC3106 SLAS509DDECEMBER 2006REVISED OCTOBER 2007 Solder the QFN thermal pad to the ground plane (DRVSS). The shaded balls on BGA packag

22、e are not connected to the die, but are electrically connected to each other. TERMINAL FUNCTIONS TERMINAL DESCRIPTION BGA BALLQFNNAME A213MICBIASMicrophone bias voltage output A114MIC3RMIC3 input (right or multifunction) C2,D215AVSS_ADCAnalog ADC ground supply, 0 V B1,C116,17DRVDDADC analog and outp

23、ut driver voltage supply, 2.7 V3.6 V D118HPLOUTHigh-power output driver (left +) E119HPLCOMHigh-power output driver (left or multifunctional) E2,F220,21DRVSSAnalog output driver ground supply, 0 V F122HPRCOMHigh-power output driver (right or multifunctional) G123HPROUTHigh-power output driver (right

24、 +) H124DRVDDADC analog and output driver voltage supply, 2.7 V3.6 V J125AVDD_DACAnalog DAC voltage supply, 2.7 V3.6 V G2,H226AVSS_DACAnalog DAC ground supply, 0 V J227MONO_LOPMono line output (+) J328MONO_LOMMono line output () J429LEFT_LOPLeft line output (+) J530LEFT_LOMLeft line output () J631RI

25、GHT_LOPRight line output (+) J732RIGHT_LOMRight line output () H833RESETReset General-purpose input/output #2 (input/output)/digital microphone data input/PLL clock J834GPIO2 input/audio serial data bus bit clock input/output 4Submit Documentation FeedbackCopyright 20062007, Texas Instruments Incorp

26、orated Product Folder Link(s): TLV320AIC3106 CONNECTION DIAGRAMS 49 TERMINAL DESCRIPTION BGA BALLQFNNAME A213MICBIASMicrophone bias voltage output A114MIC3RMIC3 input (right or multifunction) C2,D215AVSS_ADCAnalog ADC ground supply, 0 V B1,C116,17DRVDDADC analog and output driver voltage supply, 2.7

27、 V3.6 V D118HPLOUTHigh-power output driver (left +) E119HPLCOMHigh-power output driver (left or multifunctional) E2,F220,21DRVSSAnalog output driver ground supply, 0 V F122HPRCOMHigh-power output driver (right or multifunctional) G123HPROUTHigh-power output driver (right +) H124DRVDDADC analog and o

28、utput driver voltage supply, 2.7 V3.6 V J125AVDD_DACAnalog DAC voltage supply, 2.7 V3.6 V G2,H226AVSS_DACAnalog DAC ground supply, 0 V J227MONO_LOPMono line output (+) J328MONO_LOMMono line output () J429LEFT_LOPLeft line output (+) J530LEFT_LOMLeft line output () J631RIGHT_LOPRight line output (+)

29、J732RIGHT_LOMRight line output () H833RESETReset General-purpose input/output #2 (input/output)/digital microphone data input/PLL clock J834GPIO2 input/audio serial data bus bit clock input/output General-purpose input/output #1 (input/output)/PLL/clock mux output/short circuit interrupt/AGC J935GPI

30、O1 noise flag/digital microphone clock audio serial data bus word clock input/output H936DVDDDigital core voltage supply, 1.525 V1.95 V G837MCLKMaster clock input G938BCLKAudio serial data bus bit clock (input/output) F939WCLKAudio serial data bus word clock (input/output) E940DINAudio serial data b

31、us data input (input) F841DOUTAudio serial data bus data output (output) D942DVSSDigital core / I/O ground supply, 0V E843SELECTControl mode select pin (1 = SPI, 0 = I2C) C944IOVDDI/O voltage supply, 1.1 V3.6 V B845MFP0Multifunction pin #0 SPI chip select / GPI / I2C address pin #0 B946MFP1Multifunc

32、tion pin #1 SPI serial clock / GPI / I2C address pin #1S A847MFP2Multifunction pin #2 SPI MISO slave serial data output / GPOI A948MFP3Multifunction pin #3 SPI MOSI slave serial data input/GPI/audio serial data bus data input C81SCLI2C serial clock/GPIO D82SDAI2C serial data input/output/GPIO A7NCNo

33、 connect A63LINE1LPMIC1 or Line1 analog input (left + or multifunction) A54LINE1LMMIC1 or Line1 analog input (left or multifunction) B75LINE1RPMIC1 or Line1 analog input (right + or multifunction) B66LINE1RMMIC1 or Line1 analog input (right or multifunction) A47LINE2LPMIC2 or Line2 analog input (lef

34、t + or multifunction) B58LINE2LMMIC2 or Line2 analog input (left or multifunction) B49LINE2RPMIC2 or Line2 analog input (right + or multifunction) A310LINE2RMMIC2 or Line2 analog input (right or multifunction) B311MIC3LMIC3 input (left or multifunction) B212MICDETMicrophone detect C4-C7, D3-D7, E3-E

35、7, NCDo not connect. F3-F7, G3-G7, H3-H7 PIN DESCRIPTION 50 Q210 : IS62WV51216BLL (SRAM) FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTIONSPIN CONFIGURATION 48-Pin mini BGA (7.2mm 8.7mm) 51 Q207 : M66592FP (USB ) M66592FP/WG Rev1.00 2004.10.01 page 3 of 125 1.3 Pin layout diagram Figure 1.1 shows the pin lay

36、out diagram (top view) of the controller. AFED33G AFED33V DM DP VBUS AFEA15V AFEA15G REFRIN AFEA33G XIN XOUT AFEA33V AFED15V AFED15G VIF TEST D8 D7 D6/AD6 D5/AD5 D4/AD4 D3/AD3 D2/AD2 D1/AD1 D0 A6/ ALE A5 A4 A3 A2 A1 MPBUS M66592FP (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5

37、6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SD6 SD7 INT_N SOF_N RD_N WR0_N WR1_N CS_N DREQ0_N DACK0_N DEND0_N DREQ1_N DACK1_N/DSTB0_N DEND1_N RST_N VIF SD5 SD4 SD3 SD2 SD1 SD0 VIF DGND VDD D15 D14 D13 D12 D11 D10 D9 Pac

38、kage M66592FP : 64pinLQFP (0.5mm pitch) *The “_N” in the signal name indicates that the signal is in the “L” active state. Figure 1.1 Pin layout diagram of M66592FP PIN LAYOUT DIAGRAM 52 State of pin *7) Category Pin name NameI/OFunction Pin count (Pin nos.) RST_N=” L” RST_N goes “H” PCUT=1 D15-0 Da

39、ta Bus I/O This is a 16-bit data bus. 24-39*4) *4) AD6-1 Multiplex Address Bus I/O When a multiplex bus is specified, this group of pins is used on a time-shared basis for some of the data buses (D6-D1), or for 6 bits of the address bus (A6-A1). Input (Hi-z) A6-1 Address Bus IN This is a 6-bit addre

40、ss bus. Because the data bus consists of 16 bits, there is no A0. 18-23Input *5) Input *5) ALE Address Latch Enable IN When a multiplex bus is specified, the A6 pin is used as the ALE signal. Input Input Input (Hi-z) Input CS_N Chip Select IN Setting this to the “L” level selects this controller. 56

41、Input *6) Input *6) Input RD_N Read Strobe IN Setting this to the “L” level reads data from the controller registers. 53Input Input Input WR0_N D7-0 Byte Write Strobe IN At the rising edge, D7-D0 are written to the registers of the controller. 54Input *6) Input *6) Input WR1_N D15-8 Byte Write Strob

42、e IN At the rising edge, D15-D8 are written to the registers of the controller. 55Input *6) Input *6) Input CPU bus interface MPBUS*3 Bus Mode Selection IN Setting this to the “L” level selects a separate bus. Setting this to the “H” level selects a multiplex bus. This should be fixed at either the

43、“H” or “L” level. 17Input *3) Input *3) Input *3) Split bus interface SD7-0 Split Data Bus I/O If a split bus is selected, this functions as the data bus for the split bus. 43-50Input (Hi-z) Input (Hi-z) Input (Hi-z) DREQ0_N*1 DREQ1_N*1 DMA Request OUT This notifies the system of a D0FIFO port or D1

44、FIFO port DMA transfer request. 57, 60H H H/L *8) DACK0_N*1 DACK1_N*1 DMA Acknowledge IN Input the DMA Acknowledge signal for the D0FIFO or D1FIFO port. 58, 61Input Input DSTB0_N*2 Data Strobe 0 IN This functions as the data strobe signal for the D0FIFO port. Because it is also used for the DMA Ackn

45、owledge signal of the D1FIFO port, the DSTB0_N function cannot be used if the DACK1_N function is being used. Input DMA bus interface DEND0_N*1 DEND1_N*1 DMA Transfer End I/O This receives the Transfer End signal from another peripheral chip or the CPU as an input signal. This indicates the transfer

46、 end data as an output signal. 59, 62Input (Hi-z) Input (Hi-z) Input (Hi-z) INT_N Interrupt OUT In the “L” active state, this notifies the system of various types of interrupts relating to USB communication. 51H H H Interrupt/ SOF output SOF_N SOF pulse output OUT When an SOF is detected in the “L”

47、active state, an SOF pulse is output. 52H H H 10 NI tupn i no i ta l l i csO NIXClock XOUT Oscillation output OUT A crystal oscillator should be connected between XIN and XOUT. When using external clock input, the external clock signal should be connected to XIN, and XOUT should be open. 11 PIN DESC

48、RIPTIONS 53 State of pin *7) Category Pin name NameI/OFunction Pin count (Pin nos.) RST_N=” L” RST_N goes “H” PCUT=1 RST_N Reset signal IN At “L” level, the controller is initialized. 63 Input (L) Input (H) Input (H) System control TEST Test signal IN This should be fixed at “L” or open. 16 DP USB D

49、+ data I/O This should be connected to the D+ pin of the USB bus. 4Input (Hi-z) Input (Hi-z) Input (Hi-z) USB bus interface DM USB D- data I/O This should be connected to the D- pin of the USB bus. 3Input (Hi-z) Input (Hi-z) Input (Hi-z) VBUS monitor input VBUS VBUS input IN This should be connected directly to the Vbus of the USB bus. The connected or disconnected state of the Vbus can be detected. If This pin is not connectted with Vbus of a USB bus, connect it with 5V. 5Input (Hi-z) Input (Hi-z)