Yamaha-RXA-700-Service-Manual-Part-3电路原理图.pdf

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1、A 1 2 3 4 5 6 7 8 9 10 BCDEFGHIJKLMN RX-V667/HTR-6063/RX-A700 108 DIGITAL 2/7 All voltages are measured with a 10M/V DC electronic voltmeter. Components having special characteristics are marked and must be replaced with parts having specifications equal to those originally installed. Schematic diag

2、ram is subject to change without notice. 1.8 1.9 3.3 3.3 0 3.3 1.8 1.8 1.8 0 0.60 0 0 0 1.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1.8 0 3.3 1.1 1.7 1.8 0.6 0.5 0.5 0.4 3.3 1.9 1.9 1.9 1.8 3.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3.3 0 0 0 0 0 3.3 1.8 0 1.6 1.5 3.3 3.3 1.8 0 0 0

3、0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.7 3.3 3.3 3.1 3.1 0 3.3 3.3 1.5 1.5 1.9 0.4 0 0 0 0.4 0.4 0.5 0.5 3.3 1.8 0 1.8 0 1.6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3.3 3.3 2.5 3.1 5.5 0 0 0 0 0 0 0 0 0 0.9 0.9 0.7 0.7 5.0 0 1.9 0.9 3.3 1.2 1.4 2.0 3.3 0 2.5 1.3 1.2 1.6 1.6 3.1 3.3 3.3 0 0 0 3.3

4、3.3 0.7 0.9 0.7 1.3 1.3 3.2 0 3.1 3.3 3.3 3.1 0 0 1.7 3.3 3.3 3.3 3.3 3.3 1.5 3.1 3.1 1.3 3.1 3.1 3.3 3.3 3.3 0 0 0 0 1.80 00 0 0 0 0 0 0 0 0 1.7 1.1 3.4 0.6 0.5 0.5 0.4 0 0 0 0 0 0 0 0 3.1 3.3 3.4 2.5 1.6 3.4 3.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3.1 3.3 2.6 1.7 0.6 0.5 0.5 0.4 1.7 1.2 POINT A XL

5、31 (Pin 81 of IC32) A IC41: ADV7172KSTZ Digital PAL/NTSC video encoder 8 8 RSET1 COMP1 ADV7172/ADV7173 COLOR DATA P0 VREF RSET2 COMP2 P7 DAC E DAC F DAC D DAC A DAC B DAC C BRIGHTNESS AND CONTRAST CONTROL + ADD SYNC + INTERPOLATOR 10 LUMA PROGRAMMABLE FILTER + SHARPNESS FILTER SATURATION CONTROL + A

6、DD BURST + INTERPOLATOR 10 PROGRAMMABLE CHROMA FILTER 10 8 8 8 REAL-TIME CONTROL CIRCUIT SCRESET/RTC MODULATOR + HUE CONTROL 10 10 10 10 10 10 Y U V 8 4:2:2 TO 4:4:4 INTER- POLATOR 1010 SIN/COS DDS BLOCK DAC CONTROL BLOCK DAC CONTROL BLOCK 10 10 10 10 10 10-bit DAC 10-bit DAC 10-bit DAC 10-bit DAC 1

7、0-bit DAC 10-bit DAC 10 M U L T I P L E X E R M U L T I P L E X E R YUV TO RBG MATRIX + YUV LEVEL CONTROL BLOCK I2C MPU PORT HSYNC FIELD/ VSYNC BLANK TTX TTXREQ VAA RESET TELETEXT INSERTION BLOCK YCrCb TO YUV MATRIX CLOCKCSO_HSO VSO CLAMPSCLOCKSDATAALSB VIDEO TIMING GENERATOR GND PAL_NTSC 36 35 34 3

8、3 32 31 30 29 28 27 26 25 13 1415 1617181920 21 22 2324 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 454439 38 3743 42 41 40 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) ALSB HSYNC FIELD/VSYNC BLANK GND VAA P0 P1 P2 P3 P4 P5 P6 P7 CSO_HSO VAA GND VAA SCLOCK SDATA RSET2 ADV7172/ADV7173 DAC F COMP1 DAC A VAA DAC B

9、 VAA GND VAA DAC C DAC D VAA GND DAC E CLOCK GND VAA VSO RESET PAL_NTSC CLAMP TTXREQ SCRESET/RTC RSET1 VREF COMP2 GND TTX INPUT MUX OUTPUT FIFO AND FORMATTER IC32: ADV7800BSTZ-80 10-bit, SDTV/HDTV 3D comb filter, video decoder and graphics digitizer CLAMP 12 ANTIALIAS FILTER ADC 24 P30 TO P53 GRAPHI

10、CS RGB AIN1 AIN12 CVBS S-VIDEO SCART- (CBVS+RGB) YPrPb TO CVBS OUT FB HS_IN2 VS_IN2 HS_IN VS_IN SOG SOY SCLK SCLK2 SDA SDA2 ALSB INT CLK_IN DE_IN 10 CLAMP ANTIALIAS FILTER ADC 10 CLAMP ANTIALIAS FILTER ADC 10 2D COMB CLAMP DIGITAL INPUT PORT DVI OR HDMI SYNC PROCESSING AND CLOCK GENERATION SERIAL IN

11、TERFACE CONTROL AND VBI DATA COLORSPACE CONVERSION SSPDSTDI ANTIALIAS FILTER ADC 10 10 10 10 10 DAC CORE CLK COMPONENT PROCESSOR (CP) STANDARD DEFINITION PROCESSOR (SDP) DDR/SDR-SDRAM INTERFACE DDR/SDR-SDRAM INTERFACE VBI DATA PROCESSOR (VDP) GAIN CONTROL MACROVISION DETECTION ACTIVE PEAK AND AGC DI

12、GITAL FINE CLAMP AV CODE INSERTION OFFSET CONTROL LLC SFL/SYNC_OUT FIELD/DE VS CS/HS PIXEL DATA P0 TO P53 AV CODE INSERTION FAST BLANK OVERLAY CONTROL VERTICAL PEAKING MACROVISION DETECTION HORIZONTAL PEAKING CTI LTIITOP STANDARD AUTODECTION COLORSPACE CONVERSION 525p/625p SUPPORT 3D COMB TBC MUX 54

13、 VDD CE Pin No. 1 2, 5 3 4 6 Symbol VOUT GND CE NC VDD Description Output Pin of Voltage Regulator Ground Pin Chip Enable Pin No Connection Input Pin Vref 61 32,5 Current Limit VOUT GND IC33: R1172S331B-E2-F CMOS-based positive-voltage regulator IC 1DIR A1 A2 A3 A4 A5 A6 A7 A8 GND Vcc OE B1 B2 B3 B4

14、 B5 B6 B7 B8 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 IC36-40: SN74LVC245APWR Octal bus transceivers with 3-state outputs VDD CE Vref 43 12 Current Limit VOUT GND Pin No. 1 2 3 4 Symbol VOUT GND CE VDD Description Output Pin Ground Pin Chip Enable (H Active) Input Pin IC31: RP130Q181D-TR-F V

15、oltage regulator To DIGITAL 6/7 To DIGITAL 3/7 To DIGITAL 1/7 DIGITAL (1) VIDEO DECODER and I/P VIDEO ENCODER to VIDEO (1)_CB304 Page 118K9 to VIDEO (9)_CB391 (B, G, F models) Page 120C3 A 1 2 3 4 5 6 7 8 9 10 BCDEFGHIJKLMN 109 DIGITAL 3/7 RX-V667/HTR-6063/RX-A700 All voltages are measured with a 10

16、M/V DC electronic voltmeter. Components having special characteristics are marked and must be replaced with parts having specifications equal to those originally installed. Schematic diagram is subject to change without notice. 3.4 1.7 2.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

17、0 0 0 2.8 2.8 2.8 2.8 2.8 2.8 2.8 2.8 2.8 2.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3.4 3.4 3.4 3.4 3.30.9 1.8 1.8 0 1.2 1.2 1.2 1.6 1.6 3.4 0 0 0 0 0 0 1.4 3.1 0 0 0 2.0 2.8 1.3 1.4 1.3 2.0 2.5 0 0 0 0 0 3.3 0.3 3.3 3.3 3.3 1.0 1.0 2.3 2.3 2.5 2.5 2.4 2.8 2.8 2.8 2

18、.8 2.8 2.8 2.8 2.8 2.8 2.8 2.8 1.4 3.3 2.3 2.3 3.3 3.1 3.1 1.4 2.9 2.8 0 1.7 1.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.4 0.5 0.5 0.7 1.9 1.5 1.7 2.6 3.1 1.5 1.9 0 0 0 0 1.7 1.2 0.6 3.4 3.4 3.4 3.4 3.4 3.4 3.4 3.4 3.4 3.4 3.4 3.4 3.4 3.4 3.4 3.4 3.4 3.4 3.4 3.4 0 0 3.2 3.4 1.2 1.2 1.2 1.2 1.2 1.2

19、 1.2 1.2 1.2 1.2 3.2 3.2 0 1.61.6 3.3 0 3.4 2.8 2.8 2.8 3.1 3.4 3.4 3.4 3.4 3.4 3.4 3.4 2.8 2.9 2.3 2.8 0 0 0 0 0 0 0 0 0 0 1.4 1.4 1.4 3.3 2.3 2.3 2.5 2.4 3.3 3.3 1.0 1.0 3.3 3.3 2.3 2.0 2.8 1.4 1.3 2.3 3.1 3.1 3.1 0.3 0 0 1.7 POINT B XL61 (Pin 3) B VDD CE Pin No. 1 2 3 4 5 Symbol VOUT GND CE NC VD

20、D Description Output Pin of Voltage Regulator Ground Pin Chip Enable Pin No Connection Input Pin Vref 54 21 Current Limit VOUT GND IC63: R1172H121D-T1-F CMOS-based positive-voltage regulator IC 1 3 2 5 4GND VCC IC65: TC7SH125FU Bus buffer IN A G OUT Y IC62: M12L128168A-5TG2T 2 M x 16-bit x 4 banks s

21、ynchronous DRAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 VDD DQ0 VDDQ DQ1 DQ2 DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS VSS DQ15 VSSQ DQ1

22、4 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS L(U)DQM DQ Mode Register Control Logic Column Address Buffer and Counter Row Address Buffer and Refresh Counter Bank D Row Decoder Bank A Bank B Bank C Sense Amplifier Column Decoder Data Control Circuit Latch

23、Circuit Input and Output Buffer Address Clock Generator CLK CKE Command Decoder CS RAS CAS WE To DIGITAL 2/7 To DIGITAL 4/7 To DIGITAL 1/7 To DIGITAL 6/7 DIGITAL (1) To DIGITAL 6/7 To DIGITAL 2/7 No replacement part available. No replacement part available. No replacement part available. FPGA FPGA A

24、 1 2 3 4 5 6 7 8 9 10 BCDEFGHIJKLMN RX-V667/HTR-6063/RX-A700 110 DIGITAL 4/7 All voltages are measured with a 10M/V DC electronic voltmeter. Components having special characteristics are marked and must be replaced with parts having specifications equal to those originally installed. Schematic diagr

25、am is subject to change without notice. 0 0 0 0 0 0 0 0 0 4.9 4.9 4.9 4.9 4.95.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3.4 3.4 1.8 1.8 3.3 0 0 5.6 5.6 1.2 3.3 0 3.4 3.3 3.3 3.4 0 3.3 5.5 5.0 0 1.8 3.3 1.3 1.3 3.3 0 1.8 3.4 0 0 0 3.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1.7 1.7 1.3 1.8 0 3.4 3.5 0 5

26、.1 5.5 0 3.4 0 00 00 00 00 00 00 00 00 3.4 0 1.7 3.3 0 3.3 3.22.1 0 4.9 0 5.0 0 0 0 0 0 0 0.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3.4 1.8 1.8 0 0 0 0 1.6 1.7 1.3 1.3 3.1 3.1 3.4 4.9 4.9 0 0 0 0 0 0 0 0 0 0 0 0 0 1.8 1.8 1.8 1.8 1.8 0 0 0 0 1.6 1.7 1.7 3.4 4.9 5.5 3.4 3.4 5.5 0 0.8 1.4 3.3 3.

27、3 3.3 5.5 3.4 3.4 3.4 3.4 3.4 0 0 0 0 0 0 5.5 5.5 1.8 1.8 5.5 0 0.8 1.4 3.4 3.3 5.5 1.8 1.8 1.8 1.8 1.8 0 0 0 0 0 0 5.5 VOUTVIN Control GND 1 45 2 IC72: NJM2867F3-05 (TE1) Low dropout voltage regulator Bandgap Reference Thermal Protection VDD CE Pin No. 1 2 3 4 5 Symbol VOUT GND CE NC VDD Descriptio

28、n Output Pin of Voltage Regulator Ground Pin Chip Enable Pin No Connection Input Pin Vref 54 21 Current Limit VOUT GND IC76: R1172H121D-T1-F CMOS-based positive-voltage regulator IC VDD CE Vref 43 12 Current Limit VOUT GND Pin No. 1 2 3 4 Symbol VOUT GND CE VDD Description Output Pin Ground Pin Chip

29、 Enable (H Active) Input Pin IC79: RP130Q501D-TR-F Voltage regulator IC71: SiI9134CTU HDMI transmitter XOR Mask DSCL DSDA EXT_SWING Tx0 Tx1 Tx2 TxC CSDA RESET# MCLK S/PDIF SCK WS DE IDCK VSYNC HSYNC SD3:0 DL3:0 DR3:0 D35:0 INT HPD CSCL Registers and Configuration Logic HDCP Keys EEPROM E-DDC Master

30、CI2CA Slave Video Data Capture Logic/DE Generator HDCP Encryption Engine HDMI 1.3 TMDS Core Audio Capture Logic YCbCr to RGB Color Space Converter/ 4:2:2 to 4:4:4 Converter 1DIR A1 A2 A3 A4 A5 A6 A7 A8 GND Vcc OE B1 B2 B3 B4 B5 B6 B7 B8 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 IC80: SN74LVC2

31、45APWR Octal bus transceivers with 3-state outputs 1 3 2 5 4GND VCC IC84: TC7SH08FU 2-input AND gate IN A IN B OUT Y IC82: TC7WHU04FU Triple inverter 8 1 1A VCC 7 2 3Y 1Y 6 3 2A 3A 5 4 GND 2Y IC81: TC74VHC157FT Quad 2-channel multiplexer SELECT1 1A2 1B3 1Y4 2A5 2B6 2Y7 GND8 Vcc16 ST15 4A14 4B13 4Y12

32、 3A11 3B10 3Y9 ASG BA YB AY BA YYB IC73, 77: EN5327QI DC DC converter (-) PWM Comp (+) (-) (+) Error Amp Compensation Network Voltage Reference Regulated Voltage Power Good Logic PLL / Sawtooth Generator UVLO Current Limit N-Drive P-Drive Over Voltage Thermal Limit Soft Start SS EAOUT ENABLE EAOUT X

33、FB POK 30 29 AGND 32 27 SYNC26 31 19 1, 2, 12, 34-38 5-11 13-18 28 33 AVIN PGND VOUT NC(SW) PVIN VDD CE Vref 43 12 Current Limit VOUT GND Pin No. 1 2 3 4 Symbol VOUT GND CE VDD Description Output Pin Ground Pin Chip Enable (H Active) Input Pin IC83: RP130Q121D-TR-F Voltage regulator HDMI OUT No repl

34、acement part available. To DIGITAL 1/7 To DIGITAL 7/7 To DIGITAL 6/7 To DIGITAL 3/7 DIGITAL (1) HDMI Tx SELECTOR BUFFER to VIDEO (3)_W3801 Page 120I8 A 1 2 3 4 5 6 7 8 9 10 BCDEFGHIJKLMN 111 DIGITAL 5/7 RX-V667/HTR-6063/RX-A700 All voltages are measured with a 10M/V DC electronic voltmeter. Componen

35、ts having special characteristics are marked and must be replaced with parts having specifications equal to those originally installed. Schematic diagram is subject to change without notice. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5.6 3.1 0 0 0 0 0 0 0

36、 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 05.6 0 0 0 0 0 3.1 0 0 3.4 3.4 3.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3.4 3.4 3.4 3.4 3.4 3.4 3.4 GND EN SDAB SCLB SDAA SCLA CCA V CCB V CCB pull-up resistor V IC91: PCA9517DP Level translating I2C-bus repeater 3 18 4 6 72 5 VDD CE Vr

37、ef 43 12 Current Limit VOUT GND Pin No. 1 2 3 4 Symbol VOUT GND CE VDD Description Output Pin Ground Pin Chip Enable (H Active) Input Pin IC95: RP130Q331D-TR-F Voltage regulator IC94: TMDS141RHAR HDMI switch IC981: TRS3221ECPWR 3 V to 5.5 V single channel RS-232 line driver/receiver with 15 kV IEC E

38、SD protection 1 2 3 16 14 EN C1+ V+ 4 5 6 C1- C2+ C2- 7 8 V- RIN 15 VCC GND FORCEOFF 13DOUT 12FORCEON 11DIN 10 INVALID 9 ROUT 1113 10 8 1 DIN FORCEOFF FORCEON ROUT Auto-Powerdown 16 12 9 EN RIN INVALID DOUT TMDS Receiver w/EQ VCC RINT RX2 Rx2 RX1 TMDS Driver TMDS Receiver w/EQ VCC RINT TMDS Driver T

39、MDS Receiver w/EQ VCC RINT TMDS Driver TMDS Receiver w/EQ VCC RINT TMDS Driver OE PRE VSADJ RX1 RX0 RXC RX0 RXC RSCL RSDA OVS I2CEN TX2 Tx2 TX1 TX1 TX0 TXC TX0 TXC TSCL TSDA 30 6 7 9 10 12 13 15 16 18 19 22 23 2 1 39 38 36 35 33 32 28 25 5 29 VIDEO AUX HDMI IN RS-232C RX-A700 model DIGITAL (2) DIGIT

40、AL (3) to DIGITAL (1)_CB901 Page 112A3 to DIGITAL (1)_CB8 Page 107L1 A 1 2 3 4 5 6 7 8 9 10 BCDEFGHIJKLMN RX-V667/HTR-6063/RX-A700 112 DIGITAL 6/7 All voltages are measured with a 10M/V DC electronic voltmeter. Components having special characteristics are marked and must be replaced with parts havi

41、ng specifications equal to those originally installed. Schematic diagram is subject to change without notice. FRONT L CENTER/SUBWOOFER SURROUND L SURROUND BACK L DIGITAL IN ANALOG IN C 1 D 2 POINT C XL901 (Pin 20 of IC908) 1IC908 (+3.3M) IC908 (MCPU_N_RESET) 2 1IC908 (+3.3M) IC908 (MCPU_N_RESET) 2 A

42、C POWER ON (Connect the power cable) AC POWER ON (Connect the power cable) AC POWER OFF (Disconnect the power cable) POINT D 1 / IC908 (142 pin, +3.3M), 2 / IC908 (19 pin, MCPU_N_RESET) IC903: LE25LB2562M-TLM-E 256 k-bit serial SPI EEPROM SERIAL INTERFACE Y DECODER 1 2 3 4VSS WP# SO CS# SI SCK HOLD#

43、 VDD8 7 6 5 X DECODER EEPROM Ce l Array CONTROL LOGIC I/O BUFFERS and DATA LATCHES ADDRESS BUFFERS and LATCHES CS#SCKSISOWP#HOLD# VDD CE Vref 43 12 Current Limit VOUT GND Pin No. 1 2 3 4 Symbol VOUT GND CE VDD Description Output Pin Ground Pin Chip Enable (H Active) Input Pin IC915: RP130Q501D-TR-F

44、Voltage regulator A H L H L H L L HH H H L BY 1 3 2 5 4GND VCC IC910: TC7SH32FU 2-input OR gate IN A IN B OUT Y IC913: TC74VHCT08AFT Quad 2-input AND gate Vcc14 4B 4A 4Y 3B 3A 3Y 1A1 2 3 13 12 11 10 9 8 4 5 6 7 1B 1Y 2A 2B 2Y GND IC914: TC74VHC08FT Quad 2-input AND gate Vcc14 4B13 4A12 4Y11 3B10 3A9

45、 3Y8 1A1 1B2 1Y3 2A4 2B5 2Y6 GND7 IC901, 902: SN74LV4051APWR 8-channel analog multiplexers/demultiplexers Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 COM INH C B A 11 10 9 6 3 13 14 15 12 1 5 2 4 1 2 3 4 5 6 7 89 10 16 15 14 13 12 11 Y4 Y6 COM Y7 Y5 INH GND GND VCC Y2 Y1 Y0 Y3 A B C INPUTSON CHANNEL INH L L L L L L L L

46、 H L L L H H H H X C L L H H L L H H X L H L H L H L H X L Y1 Y2 Y3 Y4 Y5 Y6 Y7 None Y0 BA A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC

47、 Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 MX29LV640EBTI-70G CONTROL INPUT LOGIC PROGRAM/ERASE HIGH VOLTAGE WRITE STATE MACHINE (WSM) STATE REGISTER FLASH ARRAY X-DECODER ADDRESS LATCH AND BUFFER Y PASS GATE Y-DECODER ARRAY SOURC

48、E HV COMMAND DATA DECODER COMMAND DATA LATCH I/O BUFFER PGM DATA HV PROGRAM DATA LATCH SENSE AMPLIFIER Q0 Q15/A 1 A0 AM AM MSB address CE# OE# WE# RESET# BYTE# WP#/ACC IC909: MX29LV640EBTI-70G 64 M-bit single voltage 3 V only flash memory IC908: R5F64169DFD Single chip 32-bit microprocessor Port P0P

49、ort P1Port P2Port P3Port P4Port P5Port P6 8888888 Port P7P8_5Port P9Port P10 8788 Peripheral functions Timer: Timer A 16 bits 5 timers Timer B 16 bits 6 timers Three-phase motor controller Watchdog timer: 15 bits D/A converter: 8 bits 2 channels A/D converter: 10 bits 1 circuit Standard: 10 inputs Maximum: 34 inputs Serial interface: 9 channelsX-Y converter: 16 bits 16 bits Clock generator: 4 circuits - XIN-XOUT - XCIN-XCOUT - On-chip oscillator - PLL frequency synthesizer DMAC CRC calculator (CCITT) X16 + X12 + X5+ 1 Intelligent I/O Time Measur